Interface Requirements; Testing And Troubleshooting - HP 10312D Operating Manual

Interface
Requirements
Testing and
Troubleshooting
General Information
2-4
The preprocessor detects the start of an 80286 bus cycle when the
LSO
or
LSl
status line goes true. The interface latches address and status at
the end of the Ts state of the bus cycle. At the end of the first Tc state
of the bus cycle, the interface samples the READY signal and,
if
found
·true, the bus cycle
is
terminated and the logic analyzer
is
clocked at the
end of the next bus state.
If
the READY signal
is
not sampled true at
the end of the first Tc state, it
is
sampled at the end of each subsequent
Tc state until found true (each extra Tc state
is
equivalent to adding
one wait state). Since the 80286 microprocessor has a
10
ns setup,
5
ns
hold specification for data reads, the interface module samples data on
every clock cycle.
If
the data
is
later determined to be good
(if
READY was also sampled true), the data
is
transferred to a set of
secondary latches. Address and status in the primary latches and data
in the secondary latches are transferred to the logic analyzer at the end
of the bus state following the last Tc state of the bus cycle.
Table 2-1 lists the 80286 signals and their corresponding lines to the
logic analyzer.
The HP
103120
Preprocessor Interface Module operates with an
80286 microprocessor clocked at rates up to 20
MHz.
The card adds
one "F' load to the data, CLK,
LSO, LSl,
and HLDA lines, and one
ALS TTL load to AO-A23, LBHE, MJLIO, COD/LINTA, LLOCK,
RESET, and LREADY.
There are no automatic performance tests or adjustments for the
HP
103120
Preprocessor Interface Module.
If
a failure
is
suspected in
the HP
103120
Preprocessor Interface Module, contact your nearest
Hewlett-Packard Sales/Service Office for information on servicing the
board.