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The 20-bit buffer is intended for interconnecting DATANET-30's. Usually system considerations
indicate that a WBC should be used on lines operating at more than 300 bits per second. The
following rates are selectable with standard speed connectors: 600, 1200, 1800, 2000, 2400, and
3000 bits per second. Two WBC' s can be mounted in a buffer module and the speeds of operation
may be independently selected.
Each buffer selector address of each WBC is independently
assigned and is specified by the wiring of the address plug for the module.
WORD BUFFER INSTRUCTION
Mnemonic
Operand
Word Times
Register Transfer
R,
(TRA from R, to_· __ )
The 20 bits in the data register are distributed as follows:
20 bits
20
19
18
I I I
Register Transfer
,T
Bits 18-1 go to R {18-1).
Bit 19 goes to the
control bit 1 flip-flop and bit 20 goes to the
control bit 3 flip-flops.
The receive flag and
data register are reset.
1
-----------R
(18-1)
(TRA from _ _ to T)
Bits 18-1 of the B-register are transferred
to bits 18-1 of the transmit data register.
Bits 19 and 20 of the transmit data register
come from control bit 1 and the word parity
network .
. . - - - - - - - - - - - W o r d Parity Network
. . - - - - - - - - - - - - C o n t r o l Bit 1 F-F
T (18-1)
20
19
18
1
V-26
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