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If the VCO is too
h
ig h, fo r exam ple, the phase
d
etector
p
uts out α more
p
ositive voltage
w
hich is
f
ilte r e d an d
inverted by an integrator and app
h
ed to the
V
CO (Narrow
Oscillator ) to lower the
f
re qu ency .
3.14,2
M
IX ER
T
he phase
d
etecto r cannot operate at UH F frequencies,
so the
V
CO is
m
ixe d with 1200 MHz CW, T h is
p
rovi des
an offset frequency wh ic h is the va ria ble input to the ph ase
detector . The
d
eviation ο + this variable signal from 2 MHz
is precisely t he sa m e as the deviation of the VCO from
1198 ΜΗτ.
3 .14 .3
PH AS E
D
ETECTO R FO R PLL 5
T
his circuit compares t he 2 kH z reference from
t
h e Μ 30 .1
to the va riable fre qu ency wh ic h is the Μ29-2
o
utpu t
d
ivided by 1000 so t h at even when t
h
e Μ292 is fre qu ency
mo du lated,
t he variable frequ ency will remain in the
capture
range-
of
the
phase
detector .
Any frequency
modulation (a bove 50 Hz) is
f
iltered out
b
y the integrator
filter and τhε error voltage is fed to th e Μ 29-2 .
3 .14 .4
UN L OC K
I
N DICATO R
Window
d
etecto rs are fe d by the integrator outputs. If the
integrators put out α voltage outside
t
h eir
n
ormal operating
range, t h e window detectors apply voltage (ο the
m
odu le's
un loc k indicator and to
t
he flasher circu it on
t
he Modu-
lation Board .
3.15 Μ 34 - WID E OSCI LL ATO R LOC K
T
his mo du le p rovi des the fine tuning
p
rogram for the .
W
ide
Oscillator in
t
h e
M
9W . F ig u re 3-20 is the bloc k diagram of
the Μ 34 .
T
he letters Α thru F relate the signals at
t
he
associated p oints in
t
he modu le to
t
he graph s Α t hru F in
Figures 3-21 and 3-22 . The Μ34 phase locks the VCO to
1198 MHz
p
lus t h e frequency in d icated on all six
f
ro n t
panel switches . The
f
re que ncy offset circuit converts the
fre quency of
t
h e V CO to α lower frequency w h ic h retains
the freque ncy error information for use by the phase
d
etector. In
a
dd ition to
t
he
f
requency offset circuit and
t h e ph ase
d
etecto r, several auxiliary ci rcu its a re incl uded.
3.15,1
PH AS E DETECTOR
T
he phase
d
etector co mpares the "offset"
V
CO freq u ency
to the
r
eference frequ ency from the Μ31 Α. ( Re fe ι to
t
he
description of the Μ31 Α
f
or α more
d
etaile d description
of this 10 .000-9 .001 MHz
r
eference .)
The ph ase
d
etecto r output voltage goes
p
ositive or negative
[ο ulti mately
d
rive the
W
ide Oscillator higher or lowe r in
frequ ency until both in pu ts 2ο
t
he phase
d
etector are the
same frequency . The integrator serves as α low
p
ass filter
for the phase
d
etector,
3-18
3 .15 .2
FRFOUENCY OFFSET CIRCUIT
The VCO errnr information must b. converted to η Ire
qu ency useable by the phase detector . This conversion
is modo Ιι y ιιιίχνι 1, α 270 MHz low
p
ass filler . ηιίκίτ 2,
and α 10 MHz low
p
ass filter .
R
e fer to F igures 3-2Λ, 3-21 .
a
n d 3-22 for
d
escri ptions of signals.
M
ixer 1
h
etero
d
ynes the VCO frequ ency with the "MHz
steps" reference frequ e n cy (1448 ι R MHz) . The
d
iffe rence
frequ ency, Ι 1448 + R - V CO Ι, is
b
elow 270 MHz.
T
h is
signal is sent to mixer 2
w
here it is
h
etero d yned with
t
he
40 MHz comb. For any output frequency, graph D in
F ig ure 3-21 shows only the comb frequency whic h will
yiel d t he desire d
o
utput ( below 20 MHz) of
m
ixer 2. If the
loop is loc ked, mixer 2 will produce α 10 MHz
d
iffe r ence
as shown in F ig ure 3-21 (assuming t he "kH z" switches are
set for 0001 . Fig ur e 3. 22 shows sig n als Α t hru F for α case
when the kHz switch es are not 000.
The
f
ίιπ~r after mixer 2 blocks
all the
output, of the mixer
except the . lower fr οριια r ιcγ signal containing
t
he VCO
e
r
ror
information, When th e unit is unlocked, the filter passes
tip to 20 MHz Ιτο be able to capture over t he 20 MHz
ra nge allowe d for analog tuning), Once t he loop is locked,
t he
f
ilter decreases to 10 MH z 1ο further elim i nate phase
locked loop-related spu rious signals.
3.15.3
AU XILIARY CI RC U ITS
The "s μι 9ιd up circuit" is activate d when
t
he phase loc k ed
loop becomes unlocked . The output of this ci rcuit is sent
to th,
M
9W to cause the VCO to be tuned faster
b
y t he
αΠλΙυί (
voltage .
T
he "unlock - amp monitors
b
ot h
t
he tuning voltage from
t
he
phase d
etector
and the
leveler voltage to
d
etect
an
ιιηιοε k p . d cond ition of t h e Μ34 .
W
hen un lock occurs, it
sends α voltage to the flas h e r circuit .
T
he levele r ci rcuit
m
aintains α constant input amplitude
to
t
he phase
d
etector
b
y controlling the am p lit ude of the
input
f
rom t he
M
9W Wide Oscillator . The i nput to the
phase
d
etector
(about
10
MHz)
is
peak
detected
and
compa red to α DC refere nce in the leveler ci rcuit . The
leveler circuit controls α PIN
d
iode attenuator wh ic h is
between
t
h
e
V
CO input and
m
ixer 1 .
3.16 M115 -DOW N -CO N Y ¬ R TER ( MOD EL 3002)
T his mo du le ta kes the RE outpu t from the ΜΙΛ W- Β (wh en
the front- panel "MHz" selector switches are set to "D ΟΛ .")
and converts it to
t
h e
p
ro pe r
1 to 999 kHz output
frequency.
T
he BCD signals from t h e front-panel "MH z" selector
switches are fed into α 13-input
N
AND gate . (Two ο 1 the
inputs
a
re
h
el d hig h.) This gate
d
etermines whether the
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