Wavetek 3001 Instruction Manual page 19

3,2 .2
P
H ΑSF- LOCKED Ι OOPS
T
h e
b
asic signal generator d isc ussed in Sectio n :1 .21
h
as α
f
requency range of 1 1 π 570 MHz, has ;in ιιιιΙΙωιΙ νπΙ t.ιq-
ω h ιε h is leveled and
a
dj usta ble and has the ability to be
amplitude mo dulated.
W
it h
t
h
e above circuitry,
h
owever,
t
he fre qu e n cy accu racy is only 3 MHz with 1 MHz reso-
l u tion . To ac h ieve the desi red 1 kH z
r
esol u tion and .00196
accuracy, the instrument includes five phase-locked loops.
Α down-conversion (Model 3002 only) system enables
t h e instrument to output Ire qucrκies less than 1 ΜΗτ.
Its
o
p r ιration will be covere d in Section 3.16.
PLL 1, 2, and 4 are
u
se
d
to stab ilize t h e Wide Oscillator and
t
u ne it in 1 kHz steps . Th e
W
i de VCO is part of PILL 4.
PLL 1 an d 2 cοπνεrτ the
L
ever/i nd icator switc h setting
to refere nce frequencies for PLL 4.
PLL 3 an d 5
p
rovi de stabilization and allow FM operation
The
N
arrow VCO is part ο1 PLL 3. PLL 5 converts α ιηοd υ-
lating τί gηωΙ fif present) to α re ference 1reμυνπεγ for PLL 3-
F igure 3-2 illustrates
t
he relationsh ip between the five
numbered loops and the basic signal generator
PILL 1
The purp ose of PLL 1 is to ge nerate α C
W
signal whic h
changes in 1 kH z step s from 10 .000 to 9 .001 MHz as t
h
e
front-ραrκΙ frequ ency selector is switc
h
e d
f
rom .000 MHz
to .999 MHz . This signal will
b
t used as a reference signal
for PLL 4.
Figure 3 .3 shows α simp lified b loc k diagra m ο 1 PLL 1 . It
i
n
cl
ud
es α voltage controlle
d oscillator
ca
p
able
of
f re-
que n cies f r o m 9 to 10 MHz, σ ph ase
d
etecto r, and α =Ν
counter Α sample ο ! t h e outp ut signal from the VCO ά
fed to α
p
rogrammable countifir. The divisor of the counter
is controlled by the three fro nt-panel " kH z" selector
switches, T he output from
t
he counter is
f
eel [ο α ph ase
d
etector wher e it
is compared to α 1 kH z crystal
r
eference
signal . If t h e two input signals to the ph ase detector are not
t
h e same fre quency, an
error signal is produced This error
voltage corrects the fre qu ency of t he VCO until the ph ase
detector input from the counter is exactly I kHz, See
Section 3,12 for α move
d
etailed ex pla nation.
PLL 2
The purp ose of PLL 2 is to gene rate α CW signal w
h
ich
changes in 1 MHz steps
f
ro m 1448 to 1487 MHz when the
front- pa n el frequency selector is switc
h
ed from 001 to 039
MHz.
T
h ese C
W
steps are then re peated every 40 MHz
t
hrough out the
e
n ti re 1 to 620 MHz
r
ange . The
u
se of this
signal !ο cont rol the Wide Oscillator will
b
e
d
iscussed in
t
h
e description of PLL 4r
3-4
Figure 3- Λ shows α simplified block diagra m ο 1 PLL 2.
PLL 7 σμεrαιρs in t he same manner as PLL 1 with on,,
εκ cνςιυσπ . T he circuit includes α mixer and ban d-pass
αιημ f 1ίνι
Th r 1 κιιριηι- of this αιk 1ι t ιυπαΙ rαειιιrrγ ιτ to
offset the 1448 to 1487 MHz output
f
ro m
t
he VCO to
Θ to 47 MHz. T h is offset is necessary i n o
rder to
m
ake
t he
f
req uency compatible with
t
h e
p
rogram mable counter
a
nd ph ase d etecto r circ u its. Th e ot her ci rcuits in t his loop
o
perate the same as
t
hose in PLL 1 . In
t
h is case,
t
he pro-
grammable counter is cont r olled by the t
hr ee "MHz"
selector switches an d
t
h e loop reference frequency is I
MHz- For α more complete description, see Section 3.13.
PLL
4
The
p
ur pose of PLL 4 is to adjust
t
he
W
ide Oscillator in
1 kH z steps from 1198 MHz 2ο 1718 MHz υ
t
h e front-
panel fre que ncy selector is adjusted from 1 [ο 520-000.
The
W
" dε Oscillator Iregιιency is offset
b
y mixers 1 and 2
αηλ rίιιιι1 ιαικ d to th e wlerence ifrn m PILL 11 by
t
he ph ase
(letectm . Α
d
ίΓ feινπιe in phase οι fre qu en cy causes an
error
signal to lone
t
he
W
ide Oscillator
u
ntil both ph ase detector
inputs
are
identical . Now
t
his loop locks on α Particular
freηυeocγ can tx st be explained in
t
h ree stem : 1) ph ase
lock ing at 40 MHz intervals across the
b
and, 21f phase
locking at 1 MHz intervals, 3) ph ase lock ing at 1
kHz
Ιπτη rυα
h
. Fig ure 3-6 is α si mplifie d bloc k diagram of PILL 4,
To understand locking at
40
MHz intervals, assume
te mp orari
l
y t h at t h e reference frequencies from PILL 1
and PLL 2 are fixed 110 MHz and 1448 MHz respectively) .
F i
y ιιιe 3-5 shows
t
he frequ encies throughout the loop lot
t
his dι sειιςsίοπ. This stop of the PL L 4 expla nation can be
d
escr ι
h
ed
m
ore clea rly
b
y considering the entire Wi d e
ΟsειΙΙαtοι range rather
t
han discussing single frequencies .
The Wide Oscillator covers the range ο( 1198 to 1718 MHz
as the output frequ ency c hanges
from
0 to 520 MHz
( Figu re 3-5, lines Α and C) .
Wh en ιΙιο
W
ide Oscillator range is h
eterodyned in mixe r 1
with 1448 MHz,
t
he
d
iffe rence freq uency produced ra nges
from 250 to 0 to 270 MHz Wigure 3-5, line ΕΙ . This signal
is then mixed with α 40 MHz comb fall harmonics of 40
MH z) in mixer 2 (Figure 33, li n e
F
I . Ta ki ng t h e
d
ifference
between lines Ε avid F yiel ds the
r
epetitive frequ ency range
of from Π to 20 to 0 ΜΗτ as s hown in line G. Th is signal
is
f
e d to t h e phase d
etecto r.
The
r
eference to the phase detector is 10 MHz, but the loop
will not lock on every 10 MHz outpu t of mixer 2. The only
10 MHz signals whic h will produce lock
are
t
hose which
would
d
ecrease in freq uency if the Wi de VCO tried to d
rift
h
igher . T h erefore, at
eve
r
y
40 MHz interval of the ou tpu t
frequ ency, an inpu t to
t
he ph ase
d
etector wo ul
d allow the
loop to lock. Sectio n 3.2 ,1 explains
t
hat an analog signal
drives the Wi de Oscillator to within
t
hr ee MHz of
t
he