Wavetek 193 Instruction Manual page 33

4-7
4.4.8 Trigger Circuit
Refer to sheet 5. The trigger input at J8 is added to the
voltage from the trigger level control R119 and com-
pared at U12 pin 5 with a reference at U12 pin 4.
When the signal at U12 pin 5 exceeds pin 4 by a few
millivolts, U12 pin 3 goes high. R120 and C60 ensure a
noise free pulse at U12 pin 3 which is one of two wire
ORed inputs to U4 pin 7. The second input originates
from the MAN TRIG switch circuit. When this switch is
depressed, R115 pulls U12 pin 10 low. Pin 10 is com-
pared to the Vbb reference voltage at pin 9, latching
pin 6 high and preventing false triggering due to
switch contact bounce. Pin 13 connected to pin 6, is
4.4.7 Sine Converter
Refer to sheet 6 of the schematic. The sine con-
verter converts the buffered ± 1.0 volt peak triangle
to a sinusoidal current of 2mA peak. The input triangle
voltage (TRIBUFC) passes through a voltage divider
network to the input of the diode at pins 1, 4 and 6. As
this signal progressively increases, the diode between
pins 1 and 9 is progressively reversed biased, sinking
less current and causing the diode between pins 2
and 5 to pass increasingly more current in a sinusoidal
manner to IFUNC. This produces the positive half of
the sine wave at the output of the preamplifier. At the
same time, the diode between pins 2 and 8 is progres-
sively reversed biased. This slows and eventually pre-
vents current from flowing from the negative portion
of the sine converter.
When the input waveform moves negatively, the diode
between pins 2 and 5 is reversed biased and the diode
between pins 2 and 8 progressively conducts, produc-
ing the negative half of the sine wave.
R159 sets the input amplitude for correct biasing of
the sine conversion diodes, while R165 adjusts the
input signal offset. Thermister R161 adjusts the input
voltage to compensate for the diode voltage change
with temperature. The network consisting of R166,
R167 and C102 provides a signal (SINCMP)to the non-
inverting input of the preamplifier to compensate for
the effects of diode capacitance which would other-
wise distort the sinewave peaks at high frequencies.
are identical, only the square wave component of the
waveform at U11 pin 12 is across the timing resistor.
The amount of current supplied to charge C55 is
therefore this voltage divided by the range resistor
value. As the range resistor is increased, the feed-
back for U11 between pins 1 and 12 is also increased,
causing less current to charge C55 and increasing the
amount of current being shunted to U11 pin 12 by a
factor of 10 for each lower frequency range.
4.4.6 Capacitance Multiplier
Refer to schematic diagram sheet 5. The capacitance
multiplier is a precision current splitter which shunts
up to 99.990% of the VCG current away from the inte-
grating capacitor (C57)to produce the 100 through 0.1
frequency ranges. Timing current is divided between
C57 and R114, then again between R113 and the
selected timing resistor (R110 through R112 or R108).
The signal at U11 pins 2, 6, and 7 is a ± 1.0 volt
triangle. U11 (pins 6, 7, and 10) is a non-inverting
amplifier with a gain of 8. The waveform at U11 pin 1
is a ± 1.0 volt triangle with 0.5 volt spikes at each
peak. At any given moment, the junction of R103 and
C55 (differentiator circuit input) has 8 times the
voltage as the junction of R104 and C55. This voltage
difference causes a constant current to charge C55
through R104 and the selected timing resistor. Thus a
frequency dependent charging current flows into the
summing node of U11 pin 1, producing an inverted
square wave component at the differentiator output
U11 pin 12 sinking or sourcing current from the main
current sources and limiting the amount of current
available to charge C57. The ± 1.0 triangle at U11 pin
2 provides the triangle portion of the waveform at U11
pin 12. Since the triangle slopes on U11 pins 1 and 12
4.4.5 Loop DC Delay Compensation
The ci rcuit is also located on sheet 2 of the schematic
diagram. The purpose of this circuit is to adjust the
reference voltages on the comparators in the two
highest frequency ranges so that the triangle peaks
do not increase in amplitude due to loop delay. 02
functions as a variable positive current source con-
trolled by the range switch and the main current
source. As the generator frequency is increased, the
base voltage of 02 progressively moves negative
causing positive current through R15 and increasing
the reference voltage on U10 pin 9 in a positive direc-
tion. This causes the negative peak to switch earlier in
time, compensating for the loop delay and maintain-
ing constant triangle amplitude and correct frequency
tracking.
The positive peak comparator reference is changed in
an identical way, except that the voltage on U10 pin 4
becomes more negative with increased frequency.
04 is a variable negative current source. 01 and 03
function as temperature compensating diodes.
switch signal (ISWCTRL) high and producing a posi-
tive going ramp. In addition to being used to store the
first peak comparison pulse from U10 pins 3 and 6, U5
also ignores' 'chatter" from both positive and nega-
tive comparators.