Wavetek 193 Instruction Manual page 32

4.4.4 Hysteresis Switch
Refer to sheet 2. U10 pin 5 is the input to the positive
peak comparator, while pin 10 is the input to the nega-
tive peak comparator. A level shifted triangle signal of
- 0.9 volts to - 2.Svolts is present at pins 5 and 10 of
U10. Assume a positive going ramp. R1Sand R19 set
the reference voltage on U10 pin 4 at - 0.9 volts.
When the voltage on pin 5 exceeds the reference volt-
age on pin 4, the positive comparator changes state
and the voltage on pin 3 pulses from an ECl low
( - 1.SV) to an ECl high ( - O.SV).This signal is con-
nected to clear direct (pin 4) of D flip flop U5. The out-
put of U5 pin 2 goes low, while U5 pin 3 goes high.
These outputs toggle the differential pair 07 and OS
so that 07 is on and OS is off. This causes the current
switch control signal (ISWCTRl) to go low, which con-
nects the negative current source to the timing
capacitor, and causes the triangle to begin to ramp
negative. The negative peak comparator functions in
an identical manner to the positive comparator except
that the reference voltage at U10 pin 9 is - 2.S volts.
At the negative triangle peak, U10 pin 6 pulses high,
causing a set direct at U5 pin 5, toggling the current
4.4.3 Triangle Buffer Amplifier
Refer again to sheet 3 of the schematic. The signal on
the selected timing capacitor is present at both the
gate of 011 , and at U9 pin 2. These devices provide a
very high input impedance for the signal to avoid leak-
age which would otherwise cause poor triangle
linearity. The output current of 011 controls the base
drive to emitter follower 013 and hence the output
voltage on the emitter. This voltage is sensed at U9
pin 3, causing U9 to adjust the base voltage of 012
until the differential input of U9 is zero. The low
impedance source output voltage at the emitter
follower 013 now follows the high impedance input
signal at the gate of 011 with a circuit gain of unity.
square wave signal (ISWCTRl) from the hysteresis
switch. level shifting transistor 010 provides a con-
trol signal for the diode bridge CRS, CR9, CR30 and
CR31. When the control signal is
+
1.S volts, CR30 is
reversed biased, allowing CRS to conduct current
from the positive current source to the timing capaci-
tor selected by SW9-D.This produces a positive going
ramp. CR31 is also turned on, which reverse biases
CR9 and prevents current sinking from the timing
capacitor to the negative current source. When the
control signal is - 1.S volts, both CR30 and CR9 are
forward biased, while CR31 and CRS are reversed
biased. At this time, current from the negative current
source sinks from the timing capacitor, producing a
negative going ramp.
4-6
4.4.2 Current Switch
Refer to sheet 3. The current switch is driven by the
On the 1M and 10M ranges, the timing current is
increased by approximately 25%, allowing the use of
larger timing capacitors and hence, minimizing the
effect of any stray capacitance. On the higher ranges,
the parallel resistance across RS3 (at ISCAl) is
greater than the resistance on the lower ranges. This
would decrease the current through US pin S were it
not for the servo loop action of U13 pin 12, 014 and
US pins 6, 7 and S. For any VCG setting at U14 pin 7
and U13 pin 1, no matter which range is selected, this
servo loop maintains the voltage at U13 pin 2 equal to
pin 1. Because the voltage at U 13 pin 2 remains con-
stant from range to range, the voltage across, and
therefore the current through RSO and RS1 also
remains constant. This current also flows through US
pins 7 and S. To enable this current to remain con-
stant, the servo loop drives the base voltage at US pin
6 in a positive direction. Because all of the bases in
US are at the same point, the current relative to the
lower ranges increases in RS4 through RS7 and also
in the collectors of US pins 1, 14, 2, and 9.
Variable symmetry is controlled by RBSwhich doubles
as the frequency vernier. With VERNIER selected,
RSS functions as a frequency vernier with one end of
the control connected to ground and the other con-
nected to the -15 volt supply. The wiper supplies cur-
rent to the summing node U14 pin 6. Additionally, one
end of 1kO resistors RS4 through RS7 are aU con-
nected to the - 15 volt supply. For any given dial set-
ting, the current through each of the four resistors is
"I". With SYM selected, RSS functions as a variable
symmetry vernier with the wiper connected to the
-15 volt supply. One end of this vernier supplies cur-
rent to RS4 and RS5, while the other end supplies cur-
rent to RS6 and RS7. With the vernier centered, each
leg is approximately 50000 and reduces the current
through each of these 4 resistors to
1/10 I, dividing the
generator frequency by 10. As the symmetry control
is varied, emitter resistance in the positive and nega-
tive current sources change unequally, hence the cur-
rent sources are unbalanced and the timing for the
positive waveform is varied in respect to the negative
waveform, resulting in variable symmetry.
loop delay dc compensation currents (+ ICMP and
- ICMP), are supplied by 016 and US pin 9 and track
the timing currents.
A current (ITRGBl), is supplied by US pin 14 to the trig
baseline circuit to compensate for variations in dial
settings when the generator is in a quiescent trigger
or gated mode.