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DESCRIPTION

The Allegro MicroSystems half-bridge driver-switch APE-
K85110KNH-06-T-MH is a demonstration board containing
two APEK85110KNH GaN FET drivers and two GaN FETs
configured in a half-bridge configuration.

FEATURES

The APEK85110KNH-06-T-MH can be used to perform
double-pulse tests or to interface the half bridge to an exist-
ing LC power section.
The isolated APEK85110KNH driver does not require
secondary side power or bootstrap components. Gate-drive
power is supplied to the secondary side from the primary-
side supply voltage V
. The amplitude of the gate drive
DRV
can be varied by changing V

EVALUATION BOARD CONTENTS

• APEK85110KNH-06-T-MH Evaluation Board
APEK85110KNH-06-UM
MCO-0001510
AHV85110 Evaluation Board User Guide
between 10.8 V and 13.2 V.
DRV
APEK85110KNH-06-T-MH
Figure 1: AHV85110KNH-06-T-MH Evaluation Board

Table of Contents

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November 29, 2023

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Summary of Contents for Allegro MicroSystems APEK85110KNH-06-T-MH

  • Page 1: Table Of Contents

    APEK85110KNH GaN FET drivers and two GaN FETs configured in a half-bridge configuration. FEATURES The APEK85110KNH-06-T-MH can be used to perform double-pulse tests or to interface the half bridge to an exist- ing LC power section. The isolated APEK85110KNH driver does not require secondary side power or bootstrap components.
  • Page 2 CAUTION This product contains parts that are susceptible to damage by electrostatic discharge (ESD). Always follow ESD prevention procedures when handling the product. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com...
  • Page 3: Using The Evaluation Board

    IN_H Optional External Decoupling Figure 2: APEK85110KNH-06-T-MH Quick Start 1. Apply V = 12 V. 2. Link pins EN_PU and EN (if not using external Enable control). 3. Apply input gate signals, with adequate dead time, to the IN_L and IN_H inputs.
  • Page 4: Enable Sequence

    Figure 3. The APEK85110KNH-06-T-MH evaluation board provides direct access to the EN pin on connector CONN1. Internally, the board contains a 100 kΩ pull-up resistor connected from VDRV to the EN_PU pin on connector CONN1—see the Schematic section. If external control of the enable function is not required, pins EN and EN_PU must be linked together on CONN1 to make use of the internal 100 kΩ...
  • Page 5: Start Sequence

    Thus, the EN pin can be used via a shared EN line to flag when t has elapsed and the driver START START is ready to respond to PWM signals at the IN pin, as outlined above. Figure 4: APEK85110KNH Startup Sequence Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com...
  • Page 6: Measurement Points

    Measurement Points The APEK85110KNH-06-T-MH evaluation board contains convenient test points for monitoring the high- and low-side gate drives as well as the switch node, as shown in Figure 5. When measuring V , use a differential probe with suitable ratings for the applied bus voltage.
  • Page 7: Propagation Delay

    CH1: Driver Input CH2: Driver Output CH2: Driver Output CH2: Driver Output Low-Side Driver Output Typical Turn-On Propagation Delay Typical Turn-Off Propagation Delay Figure 6: Typical Driver Output at 100 kHz Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com...
  • Page 8: Double-Pulse Test

    An inductor is placed in parallel with the high-side switch. The goal of this inductor is to establish the test level current in the low-side switch at the end of the first on-pulse (1). The magnitude of the test level current at the end of period 1 is given by: ON_1 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A.
  • Page 9: Double-Pulse Test Results

    CH4: Inductor Current (1 A/V) CH4: Inductor Current (1 A/V) DPT Overview DPT Hard-Switching Turn-Off DPT Hard-Switching Turn-On Time Base (25 ns/div) Time Base (25 ns/div) Figure 10: DPT 400 V, 17 A Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com...
  • Page 10: Schematic

    SCHEMATIC Figure 11: APEK85110KNH-06-T-MH Schematic Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com...
  • Page 11: Layout

    LAYOUT Figure 12: APEK85110KNH-06-T-MH Top Overlay Top Copper Mid-Layer 1 Mid-Layer 2 Bottom Copper Figure 13: APEK85110KNH-06-T-MH PCB Copper Layers Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com...
  • Page 12: Bill Of Materials

    BILL OF MATERIALS Table 1: APEK85110KNH-06-T-MH Evaluation Board Bill of Materials Ref Name Description Value Manufacturer Manufacturer PN CONN1 Pin Header, 2.54 mm, 6 Contacts Connector 6 Way Molex 22284065 RES, 100 kΩ, 0.063 W, 1%, 0402 100 Ω Walsin Technologies...
  • Page 13: Related Links

    RELATED LINKS AHV85110 Product Page: https://www.allegromicro.com/en/products/motor-drivers/gate-drivers/ahv85110 AHV85110 Datasheet: https://www.allegromicro.com/-/media/files/datasheets/ahv85110-full-datasheet.pdf?sc_lang=en APPLICATION SUPPORT For applications support contact, go to https://www.allegromicro.com/en/about-allegro/contact-us/technical-assistance and navigate to the appropriate region. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com...
  • Page 14: Revision History

    Copyright 2023, Allegro MicroSystems. Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.

Table of Contents