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Section
VI
Channels
condition
the input
signals,
lurnish
square-wave
outputs that
are used
for
phase tneasurements
and produce
logarithrnic outputs
that
are
used
for
amplitude
rneasure-
ments. Thc
logarithmic outputs
are
applied
dircctly
to
the
Furution
Switching
circuits
where
they
re
individually
selected
(Log
A
or
LoB
B) or
sumned
(I-og
B/A)
and
applied
to
the
Output Filter and
Panel Nleter
i[
the
A,'npltude
Display mode. The
square-wave
outputs
arc used
to
control
J-K
flip-flops
in
the
Phase
Detector
which
provides
a
dc output
voltage
proportional
to
the
phase
difference between tbe
two input
signals. This dc
output
is
coupled
tfuough
the
l-'unction
Switching
cftcuits
aDd
Output
Fi.lter
to
the
Panel
llleter
and
Phase
Colrtrol
Logic
in
the Pluse Display mode.
The
Phase
Control
Logic
senses
the
magnitude
ard
polarity
of
the
phase
output
voltage
and,
in
turn,
applics
dc
offsets
to
the
Phase
Detertor
to
maintair
a corre,ot
phase
reading.
Thc
Dgital
Panel
Meter
is
a dc
diSital
voltmeter
which
corverts
the
analog
tunplitude
or
phase
informalion
to
a
3
1/2
digit
7
segnrent
bar
matrix,
48.
F
UNCTIO
NAL
DESCRIPTION.
4-9. lnput
Channels.
410.
Refer
to
the Furctional Block
Diagram
(Figurc
7-l).
Since
the two input
channels
are
ideltical,
the following
discussion applies
to
both
channels.
4-1
l.
Each
Input
Channel
is
comprised
of
an
lnput
Attetruator,
a
Preanrplifier,
a
l,og
A:nplifier,
a Synchronous
Rectifier
and
a
Level Tlanslator.
The
llput
Attenuator
is
controlled
by the lront
panel
voltage range
switch
and
provides either 0
dB (0.2
mV to
2
V
range)
or
20
dB
(2
mV
to
20
V
range)
of
attenuation. The
Preamplifier
provides
Unity
gain and
iinpedance
conversiol
between
the
Input
Attenuator and
thc input
of
the
Log Arnplifier. The
Log
Amplifier
oonverts
the
input
le\,el
to
a
logarithmic
value,
supplies
a
li,nited
signal
to
the
Level 'franslator
a|d
furnishes
a
logarithmic
output which
is
applied
to
the
Synchronous
Rectifier.
The Level Translator
corlditiolrs
the
applied
signal
and
produces
two
square-wave
outputs
that
are equal
in
amplitude and
180
degrees
out of
phase. These
square-wave
outputs
(desigiuted
A, A',
B and B')
arc
applied
directly
to
the
Phase
Detector
ctcuitry.
The
logaritfunij output from the Log Anrplifier is
lull-rvave
rectified
in
the
Synchronous
Rertifier
and
is
applied
to
the
Function
Switching Assembiy
(A8) lor
use
in
the
Ampti-
tud e
Display mode.
4-12.
lnput
Attenuator
(A1lA2 R5.
R6
Schematic
No.
l).
Refer
to
Figure
7-l
and
Schenlatic
No.
I
for
the
following
discussion.
4"13.
The lnput Attenuator
seryes
as
an input
voltage
divider and coupling
network
between the
input
connector
and
the
input
of
the heamplifier. With the
front
panel
range
switch
set
to
the
0.2
mV
to
2
V
position,
relay
K1
is
energized,
K2
is deenergzed and
the
input
signal
is
coupled
directly tlrrough
Cl
to
the Prearnplifier.
When
the
2
mV to
20
V
range
is
selectcd,
Kl
is dcenergizcd,
K2
is encrgized
and
the input
signal is attenuated
by 20dB by the
10:1
Model
3575A
divider network
consisting
ol
R5, R6
and
associated
ctcuitry.
The
attenuator
flalness
and
input
shunt
capaci-
tance
(<
30
pF)
is
maintained
by
compcnsating capacitors
C2
and C3.
The
circuit
configuration and capacitor
values
are s.rch
that the input
capacitance
remains
constant
regardless
of
the
voltage
range setting.
Potentiometcrs
AlR4
and
A2R.l
are
adjusted
for rnininum
phasc shift
between channels
at
13
MIIz
and
have
littlc
effect
at lorvcr
frequencies.
4-14.
Preamplifier
\A1lA2 a3
through
07
Schematic No.
1).
The Preampliliei
is
a
iow
noise.
high
input
impedance
arnplifier circuit which provides
inpcdance
conversi()n
between
the Input
Attenuator and
the input
of
the
Log
Amplifier. The
Preanrplifier
is
comprised
of
an
inpur
anplifier
stage
(Q3),
a
differential driver
stagc
(Qa, Q5).
a
colnplenrentary-symmctr)
output
stage
(Q(r, Q7) and ar
integralor
(lC1). The input
arnplifier
is a low
noise
field-effect transistor which.
havilg
a
high
inpul
impedanre.
insures
a mi,rinum
loading
effelt
on
thc input
signal. The
input circuit is
protected
against
ovcrloads
b)
lilDilins
resistor
R36.
The complenlentary-symrnetry
output
staga
provides a
low output
impedance
and
supplies
the
power
required
to
drive
the
following
llg
Amplifier
sraBes.
Overall
gain, stability and linearity
is
maintaited
bi
negativc
feedback
fror
the
junction
of
R19 and
RlO
through
the parallel
network
comprised
of
Ll
and
lll:
to
the
source
of
FET
Q3. Due
lo
the parallel
L/R
network
(Ll,
R2l)
in
the feedback
path, thc
gain
of
the preanrpLiti!'r
increases
with
frequency.
At low
ftequencies. the
reactanee
of
Ll
is
very
low,
the
feedback
is nearly 1007.
and
rhc
ltcamplifier
gain
is
approximately
l
At
high
frcclucncies
the rcactance
of
Ll
increases.
the
i'eedback
decreases and
the
gain
approaches
l.l.
The
reasoll
for
this
is
lo
compensate
for
high
lrequency roLl-off
in
the l-og
Arnplilier
and associated
circuitry.
Added
stability
in
the
Preanplitier
is provided
by
dc
feedback
from
the
junction
of Rl9
and
R20 tluough integrator
ICI
and the htput
Attenuator
nelwork
to
the
gate
of
Q3.
The purpose
of
tlris
leedback
is
to
mairtain
0
Vdc at
the
output of
the
Preamplifier.
4.15.
Overload
Detector
(A1/A2
08
rhrough
Ot0
Sche,
matic No. 1). The
Preamplilier
output
signal
at
the
junction
of
R22 and R39 is reiitificd
by
CR5,
filtered bi'
Cl4
and applied to
the
base
of
Q8. When the dc level
at
the
base
of
QQ.
becomes more
positive than
2.6
Vdc
(2.2
V
rns
input),
Q8 conducts.
QC)
cuts
off
and Q10
is
forward
biased
tluough
R26
arul R27.
Transistor
Ql0
drives the
corre-
sponding overload
indicator
(461/861) on
the
Panel
Meter.
4'16.
Log
Amplifier
(A3lA4 lC1
Schematic
No. 1).
The
Log
Arnplifier
(lCl)
is a
hybrid
circuit
designed
specifically
for
usc
in
the
Model
35754.
This
circuit
converts
the input
amplitude
to
a
logarithmic value,
furnishes
a
log
output
(lcl
pins
l,
5,
and
9) for
amplitude
measurements
and
produces
a
Iimited
output (lC1
pir
12)
that
is
used
for
phase measurements.
The major
adyantage
of
the
Log
Amplificr
is
that it
produces
usable
outputs
over
a
dynamic
input
range
of
80 dB.
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