Texas Instruments 990 Maintenance Manual page 25

~-------
~
945407-9701
TLIORES
-I
U10
15DO-
vcc
r----J
E4
~~ ~MMASKF.F.
r ~~
114DQ-
vcc
3K
E2
VCC
lR52
OUT 15
NOTE 1
vcc
4.7K
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_______..__~
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vcc
NOTE 1: E6-E12 FOR -0002
E11-E12 FOR --0003
~------ldb
TO INPUT 15 ON INPUT MULTIPLEXER Z3
EB ES
sv
IN15-
ov
2.5V
ov
E 1_3=CLR OF U 10
(
WIRED
l
~l SV
UNTIL RESET BV CPU COMMAND OV
{
E13=CLR
I /
OF U10
v
~~~ED
--0003
..--~~~~~~~~~~~~~~~~~~~~~
' - 1500-
2.5V
ov
5V
Ui'HiL RESET BY CPU COMMAND UV
(A)132028A
Figure 4-6. Edge Triggered Interrupt Generation Logic and Signals
VCC
3600HMS
IN15
3600HMS
When a voltage drop occurs at terminal E 13 (due to either a positive or negative transition of the
input interrupt, depending on the wired configuration), the voltage spike generated by the
differentiating network clears the interrupt flip-flop. If the CPU has enabled the associated
interrupt mask, the recorded interrupt is inverted three times and transferred to the CPU as a
low active (0.4 V) signal. The CPU will then execute a service routine in response to the
interrupt.
In addition to rece1vmg the hard-wired interrupt, the CPU can be programmed to locate the
source of the interrupt via the U3 multiplexer. Both the interrupt mask and the interrupt
flip-flop can be controlled by the
CPU
with the normal addressing mechanism discussed for the
data module output logic.
4-9/4-10
Digital Systems Division