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5-7 Mode latch circuit and up/down sensor
First, we
describe
the operation
of the D-type
flip-flop of 1C101 and 1C102 for latch.
Each
IC is CMOS
TC4013BP which is composed
of the
D-type
flip-flop
with
two
independent
circuits as shown
in Fig. 14. The level of the input
applied to the data (D) input is transmitted to the
Q and G outputs at the rise time of the clock
pulse (CP).
When
the clear (CL) input is made
''H'', the Q
output
becomes
''L"' irrespective of any other
input. When the preset (PR) input is made H'"
with the clear input at L'', the Q output becomes
"H'"
independent
of the clock
pulse
and
data
inputs.
When the clear and preset inputs are "H'', the clear
input is given priority, thus the Q output becomes
"L" and the Q output "'H''.
The
mode
latch circuit is as shown
in Fig. 15,
which operates as described in the timing chart of
Fig. 16.
Preset input
Data input
Clock pulse input
G output
Q output
Clear input
Fig. 14
-15-—
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