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ANALOG TO DIGITAL CONVERTER, ADC
The output from the phase sensitive rectifier is converted into digital data by a dual-slope analog to digi-
tal converter. The ADC comprises integrator 336, zero control 337, comparator
341, ADC control 338,
339 and a 19-bit counter. The latter is composed by the 11-bit counter 344, 345 and an 8-bit counter
within the microprocessor 309.
Oscilloscope drawings in Fig. 7 show one complete measurement cycle. Fig. 8 enlightens one conversion
period of the ADC within one of the single measurement cycles.
High signal of the microprocessor 309.31 prepares the conversion at t1. The time t2 - t1 may vary from
0 to 1 ms (1 pulse duration). The start pulse duration is 1.5 ms. The trailing edge of the 1 kHz signal
301.7 sets the output 338/1.5 high to start the integration at t2: the zero control is switched off and the
output of the phase sensitive rectifier is connected via FET switch 334/1 to the input of the integrator.
This is done during the zero period of the measurement
pulses..For this the 1 kHz signal shifted by
90° with reference to the switching phase of the phase sensitive rectifier is taken.
The integrator reference current, defined by resistors 702, 703, is equal! for integration (t2 to t4) and
de-integration (discharge slope, t4 to t5). The difference between input current, defined by measurement
voltage pulses and resistor 701, and the integrator reference
current effects the output voltage of the
integrator to go in negative direction during integration. At t2 flip-flop 340 and counter 339 are activa-
ted. The flip-flop' divides the 1 kHz frequency by 2 feeding the down counter 339 which was preset
to 10. At t3, counter state 7, high signal 339.6 resets the 11-bit counter to zero. Low signal 339.7 resets
flip-flop 303/2 of the comparator enabled again at t4. At t4 the counter state is zero. At the trailing
edge of the 1 kHz signal the output 339.13 generates a short low pulse resetting 338/2 and so termina-
ting the integration and starting the de-integration. The integration period T1 = 20 ms comprises 20
1 kHz pulses; so zero- and time-symmetrica!l 50 Hz noise and its odd harmonics have no influence on
the measurement result.
When 338/2 is reset at t4, all 3 enable inputs at NAND
gate 343 are high; so the 16 MHz count pulses
can pass to the 11- bit counter. The carry of the 11-bit counter toggles the 8-bit counter within the micro -~
processor, input 39.
At t5 the output voltage of the integrator crosses the zero level causing the comparator and the flip:
flop 303/2.9 to turn over to low. This signal 'end of integration' disables gate 343 to stop the 16 MHz
count pulses. The counter state at t5 is proportional to the integrator output voltage at t4 and conse.
quently to the measurement
value.
For reference measurement the integrator output is ca. 5 V at t4
resulting in T2 = ca. 15 ms, corresponding to 240.000 count pulses. The maximum
counter state is ca.
475.000 * T2 = 29.7 ms, the minimum is ca. 5000 @ T2 = 0.3 ms. So for the measurement range ca.
+235.000 count pulses are available.
As the tilt of the de-integration is independent of the measurement value, the delay time between zero
crossing and comparator turn-over and so the increase of the counter
state for every single measure
ment cycle is equal. So the difference of the counter states is not effected.
The output 303/2.9 of the comparator is sensed by the CPU at input 1. Low signal at t5, 'end of integr a-
tion', causes the CPU
to store the 19-bit counter
contents
into the data memory.
The CPU sends a
reset pulse at t6 preparing the circuitry for the next single measurement
cycle: the zero control
is
activated decreasing the integrator output voltage to zero. In the rest position the zero control has to
compensate the integrator reference curfent.
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