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@1C702 (AN8374S):
Servo processor
jm | tion | Paton
Division
Tracking gain adjustment
ea TE OUT
| oO | Tracking error signal output
Tracking error gain detecting filter
Pe [res [1 room aunadsnen
| 9 FE OUT
fo
| Focus error signal output
ae
FE aeiacrcersioceeed
Fe
ae
Fre foost [1 Jonas mn cpnaernaa
Pe [ro | 1 [reer ares sr
Cc
fre fer 1 [ricerca
a oe
CLK
Frequency pull-in clock signal
(88.2 kHz) input
Sliced and digitized RF signal
output
| 20 |pck
=|
o
| Clock output extracted from SRF
EFM signal output synchronous
with PCK
©1C703 (AN8377): BTL drive
T+ Jrvco | 1 _[oerporsiny waa
2 [vec [1 [Powrasy
(89 vie
External transistor base driving
output
RX-DT5
RX-DT5
vo
Division
[2 [veo [1 [Pome sip
a
SPCNT
eo
Track crossing speed contro! output
(Not used, open)
Selector output
(track crossing state)
Focus/tracking gain up output
(Not used, open)
Control input
(FOON: Focus servo ON signal)
Control input (TRON: Tracking
servo ON signal)
Control input [KICKF: Kick
direction (forward) command]
Control input [KICKR: Kick
direction (reverse) command}
Traverse forward command signal
Traverse backward command
signal
RF detection signal input
Dropout detection input
Power supply (+5 V input)
Traverse position detecting resistor/
capacitor inputs
Tracking drive control output
Tracking error signal input
re) z =
< 9
m
4
CNT2
NT3
TRVF
fe)
Non-inverting output of tracking
inverting output of focus driver
Non-inverting output of focus driver | _
Inverting output of traverse driver
Non-inverting output of traverse
driver
e1C704 (MN6625):
Digital signal processing
vo
Division
Serial data byte clock
fa oe
ca
(Not sige open)
zy LCLK
Crystal frame clock (Not use, open)
p+ fame | 0 | a
(de-emphasis ON at "H")
(Not used, open)
Fs [sox | 0 [somntcmecoua
Pe fino | 0 [inant
srioana
7
|WDCK
Serial data output word clock
LD
L channel deglitch signal
(Not used, open)
G
R channel deglitch signal
fms
|
o | (Not used
open)
Interpolation flag
IPFLAG
°
(Interpolation at "H")
XCK
Clock (16.9344 MHz) output
(Not used, open)
Test mode selection
ie TEST
hod (Not used, connected to +5 V)
T™
=a
Digital signal output
Mode selector ("L": normal,
"H": SLEEP mode)
CSEL
Test terminal ("L": normal)
x1
Clock input (16.9344 MHz)
Clock output (16.9344 MHz)
(Not used, open)
8S 2
m m
mel
UJ
< n 172)
GND terminal
Sub-code block (Q data)
ns
clock (75 Hz)
Sub-code frame (Q data)
clock (7.35 kHz)
(@)
LDCK
" Cc ie]
(9)
Sub-code (Q data) output
Reset signal input (reset at "L")
=|
Dv
ih
Command load signal input
vO
Division
Function
Command clock signal input
MDATA
Command data input
27
|DMUTE
Muting control
fe) im
A
Tracking servo ON signal
(tracking servo ON at "L")
TAT
Processing condition (CRC, CUE,
CLVS, TT STOP, FCLV)
Sub-code serial output data
30
(Not used, open)
UBC
+ DQ
oO
2
Clock for sub-code serial output
BCK
(Not used, open)
SMCK
Clock output (4.2336 MHz)
_|
Power supply (connected to +5 V)
Emphasis signal input
Spindle motor FG signal input
(Not used, open)
wo
Spindle motor ON signal
(ON at "L")
(Not used, open)
Drop-out signal (Drop-out at "H")
PLL extract clock input
(4.3218 MHz)
QO
mu)
un <
G) Oo
=)
37 | EC
ESY
40
3(2/8|
2
=/7
D QO za
7 v Q
PLL frequency comparison signal
44 |D7
5
16 K RAM data input/output
16 K RAM OE signal
16 K RAM WE signal
16 K RAM address signal
51
E | S~
=
(2) m
wv z
m
RAM/AO
(RAMAO: LSB, RAMA10:
MSB)
Bs)
z
Ba
oO
-62-~
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