JYTEK PXIe-3127e User Manual
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JYTEK PXIe-3127e User Manual

Pxi express embedded controller
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PXIe-3127e/3125e
PXI Express Embedded
Controller
User's Manual
Manual Rev.:
Revision Date:
1.0
Dec. 21, 2023

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Summary of Contents for JYTEK PXIe-3127e

  • Page 1 PXIe-3127e/3125e PXI Express Embedded Controller User’s Manual Manual Rev.: Dec. 21, 2023 Revision Date:...
  • Page 2 Revision History Revision Release Date Description of Change(s) 2023-12-21 Initial release...

  • Page 3: Preface

    Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for JYTEK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible.
  • Page 4 California Proposition 65 Warning WARNING: This product can expose you to chemicals including acrylamide, arsenic, benzene, cadmium, Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Dioxane, ane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and vinyl materials, which are known to the State of California to cause cancer, and acrylamide, benzene, cadmium, lead, mercury, phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and vinyl materials, which are known to the State of California to cause birth defects or...

  • Page 5: Table Of Contents

    2 Getting Started ..............17 Package Contents ............. 17 Operating System Installation ..........17 2.2.1 Installation Environment ........... 18 Installing the PXIe-3127e/3125e....... 20 2.2.2 2.2.3 Replacing the Hard Drive or Solid State Drive ..23 2.2.4 Replacing the Battery Backup ........25 2.2.5...
  • Page 6 3 Driver Installation.............. 27 A Appendix: PXI Trigger I/O Function Reference....29 Data Types................. 29 Function Library ..............30 A.2.1 TRIG_Init ..............30 A.2.2 TRIG_Close .............. 31 A.2.3 TRIG_SetSoftTrg ............31 A.2.4 TRIG_Trigger_Route ..........32 A.2.5 TRIG_Trigger_Clear ..........34 A.2.6 TRIG_GetSoftTrg............34 A.2.7 TRIG_Trigger_Route_Query ........
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  • Page 8: List Of Figures

    PXIe-3127e/3125e List of Figures Figure 1-1: Functional Block Diagram..........3 Figure 1-2: Front Panel ..............7 Figure 1-3: PXI Trigger SMB Jack ............. 8 Figure 1-4: DisplayPort Connector............. 9 Figure 1-5: GPIB Connector............. 10 Figure 1-6: LED Indicators ............... 11 Figure 1-7: COM Port...............
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  • Page 10: List Of Tables

    PXIe-3127e/3125e List of Tables Table 1-1: Front Panel Legend ............7 Table 1-2: DisplayPort Pin Assignment ..........9 Table 1-3: GPIB Pin Description ............. 10 Table 1-4: LED Indicator Legend ............ 11 Table 1-5: USB 2.0 Port Pin Assignment........12 Table 1-6: Ethernet Port Pin Assignments........
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  • Page 12: Introduction

    With a configurable PCIe switch, the PXIe-3127e/3125e can support four links at x4 or two links at x8 PXI Express link capability, with maximum system throughput of up to 16GB/s (PCI Express 3.0).

  • Page 13: Features

    1.1 Features -5 PXI Express Hardware Specification Rev.1.1  ® Core™ i7-11850HE/i5-11500HE processor for Intel  maximum computing power DDR4 SODIMM x2  Default: 16G , up to 64GB 3200MHz  Maximum System Throughput 16GB/s  PXI Express Link Capability ...

  • Page 14: Specifications

    Supports 3200MHz RAM up to 64 GB total  Supports non-ECC, unbuffered memory  The externally accessible SODIMM socket can accept replacement DDR5 DRAM DIMM modules. PXIe-3127e/3125e specifications and stability guarantees are NOTE: NOTE: only supported when JYTEK-provided DDR4 DRAM SODIMM modules are used. Introduction...
  • Page 15 Video DisplayPort supports up to 3840 x 2160 @ 60Hz resolution  DVI (with passive DisplayPort-to-DVI adapter) supports  resolution up to 1920 x 1200 @ 60 Hz DisplayPort adapters for other standards are available, with maximum available resolution dependent on the adapter chosen NOTE: NOTE:...
  • Page 16 Functional shock 30G, half-sine, 11ms pulse duration Random vibration: Operating 5 to 500Hz, 0.21Grms, 3 axes  Non-operating 5 to 500Hz, 2.46Grms, 3 axes  Environmental & Shock and Vibration values are only guaranteed with use of an JYTEK provided SSD. NOTE: NOTE: Introduction...
  • Page 17 Power Requirements Typical Consumption DC +3.3V DC +5V DC +12V Typical operation 1.722A 5.687A 1.953A (Measured while W10 is idle) Heavy operation (Measured while W10 is under heavy 1.728A 6.460A 6.000A CPU and storage utilization) Introduction...

  • Page 18: I/O And Indicators

    PXIe-3127e/3125e 1.3 I/O and Indicators 1.3.1 Front Panel Figure 1-2: Front Panel GPIB Connector Reset Button (Micro D-sub 25-pin) 2x DisplayPort 2x Gigabit Ethernet 2 USB 3.2 PXI Trigger 4x Type-A USB 2.0 LED indicators COM port (D-sub 9-pin serial)

  • Page 19: Figure 1-3: Pxi Trigger Smb Jack

    The PXI trigger connector is an SMB jack, used to route external trigger signals to or from the PXI backplane. Trigger signals are TTL-compatible and edge sensitive. The PXIe-3127e/3125e provides four trigger routing modes from/to the PXI trigger connector to synchronize PXI modules, including From a selected trigger bus line to PXI trigger connector ...

  • Page 20: Figure 1-4: Displayport Connector

    PXIe-3127e/3125e Figure 1-4: DisplayPort Connector Signal Signal CN_DDPx0+ CN_DDPx3- CN_DDPx0- CN_DDPx_AUX_SEL CN_DDPx1+ CN_DDPx_CONFIG2 CN_DDPx_AUX+ CN_DDPx1- CN_DDPx2+ CN_DDPx_AUX- CN_DDPx_HPD CN_DDPx2- CN_DDPx3+ +V3.3_DDPx_PWR Table 1-2: DisplayPort Pin Assignment Introduction...

  • Page 21: Gpib Connector

    1.3.2 GPIB Connector The GPIB connector on PXIe-3127e/3125e is a micro D-sub 25- pin connector, controlling external bench-top instruments. Connection to other instruments requires the optional ACL- IEEE488-MD1-A cable. The onboard GPIB controller provides: Full compatibility with IEEE 488 standard ...

  • Page 22: Reset Button

    Table 1-4: LED Indicator Legend 1.3.5 USB 2.0 Ports The PXIe-3127e/3125e provides four USB 2.0 ports via USB Type-A connectors on the faceplate, all compatible with hi- speed, full-speed and low-speed USB devices. Supported boot devices include USB flash drive, USB floppy, USB CD-ROM, and...

  • Page 23: Gigabit Ethernet Ports

    Power 5V USB Data- USB Data + Ground Table 1-5: USB 2.0 Port Pin Assignment 1.3.6 Gigabit Ethernet Ports Dual Gigabit Ethernet connection is provided on the PXIe-3127e/3125e front panel. 1000Base-T Signal 100/10Base-T Signal MDI0+ MDI0- MDI1+ MDI2+ Reserved MDI2-...

  • Page 24: Usb 3.0 Ports

    Orange 1000 Mbps 1.3.7 USB 3.2 Ports The PXIe-3127e/3125e provides two Type-A USB 3.2 ports on the front panel, supporting SuperSpeed, Hi-Speed, full-speed, and low-speed transmission for downstream. Multiple boot devices, including USB flash, USB external HD, and USB CD- ROM drives are supported, with boot priority configured in BIOS.

  • Page 25: Com Port

    1.3.8 COM Port A COM port on the front panel with a D-sub 9-pin connector supports RS-232/RS-422/RS-485 by BIOS selection. Figure 1-7: COM Port Signal Name RS-232 RS-422 RS-485 DCD# TXD422- 485DATA- TXD422+ 485DATA+ RXD422+ DTR# RXD422- DSR# RTS# CTS# Table 1-7: D-sub COM Port Signal Functions Introduction...

  • Page 26: Onboard Connections And Settings

    PXIe-3127e/3125e 1.3.9 Onboard Connections and Settings Figure 1-8: Onboard Configuration Clear CMOS switch SATA connector System battery Table 1-8: Onboard Configuration Legend Introduction...
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  • Page 28: Getting Started

    PXIe-3127e/3125e and making preparations for its operation, includ-ing hardware and software setup. Please note that the PXIe-3127e/3125e is shipped with RAM and HDD or SSD preinstalled. Please contact JYTEK or authorized dealer if there are any problems during the installation.

  • Page 29: Installation Environment

    Most operating systems require initial installation from a hard drive, floppy drive, or CD-ROM drive. The PXIe-3127e/3125e controller supports USB CD-ROM drive, USB flash disk, USB external hard drive, or a USB floppy drive as the first boot device. Please see Section B.5.1: Boot Configuration for information about setting the...
  • Page 30 Anti-static wrist strap  Anti-static mat  JYTEK PXIe-3127e/3125e system controllers are electrostatically sensitive and can be easily damaged by static electricity. The equipment must be handled on a grounded anti-static mat, and operators must wear an anti- static wristband, grounded at the same point as the anti-static mat.

  • Page 31: Installing The Pxie-3127E/3125E

    PXIe-3127e/3125e 2.2.2 Installing the 1. Remove all screw caps (x4). Getting Started...
  • Page 32 PXIe-3127e/3125e 2. Release the red locking lever. 3. Depress the latch. 4. Locate the system controller slot on the chassis (Slot 1). Getting Started...
  • Page 33 PXIe-3127e/3125e into the chassis, as shown 6. Elevate the latch until the PXIe-3127e/3125e is fully seated in the chassis backplane. The alignment pin on the rear of the latch can be threaded into the best fit alignment port in the chassis rail.

  • Page 34: Replacing The Hard Drive Or Solid State Drive

    PXIe-3127e/3125e 2.2.3 Replacing the Hard Drive or Solid State Drive The PXIe-3127e/3125e provides a SATA 3.0 port for optional SSD. Installing an SSD is accomplished as follows. 1. Locate the five screws attaching the hard drive housing to the PXIe-3127e/3125e controller, as shown.
  • Page 35 4. Locate the four screws (two on each side, as shown) fixing the hard drive, and remove. 5. To install an SSD, reverse the steps and reinstall the PXIe-3127e/3125e into the PXI system. Getting Started...

  • Page 36: Replacing The Battery Backup

    PXIe-3127e/3125e 2.2.4 Replacing the Battery Backup The PXIe-3127e/3125e is provided with a 3.0 V “coin cell” lithium battery, replacement of which is as follows. 1. Turn off the PXI chassis. 2. Remove the PXIe-3127e/3125e embedded controller from the chassis. Observe all anti-static precautions.

  • Page 37: Clearing Cmos

    2.2.5 Clearing CMOS In the event of a system malfunction causing the PXIe-3127e/3125e to halt or fail to boot, clear the CMOS and restore the controller BIOS to its default settings. To clear the CMOS: 1. Shut down the controller operating system and turn off the PXI Chassis.

  • Page 38: Driver Installation

    PXIe-3127e/3125e Driver Installation Windows 10 carries most device drivers for the PXIe-3127e/3125e, built-in. Others can be downloaded from the JYTEK PXIe-3127e/3125e Product Page. After downloading, execute the Setup file, and follow the instructions to complete installation for the following drivers.
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  • Page 40: A Appendix: Pxi Trigger I/O Function Reference

    Reference This appendix describes use of the PXI trigger I/O function library for the PXIe-3127e/3125e controller, to program routing of trigger signals between the trigger I/O SMB connector on the faceplate and the PXI trigger bus on the backplane. API files are located in the installation directory of the PXI Trigger I/O driver.

  • Page 41: Function Library

    Double 1.7976831348 floating-point 62315E309 A.2 Function Library This section provides detailed definitions of the functions available in the PXIe-3127e/3125e function library. Each function includes a description, list of supported cards, syntax, parameter list and Return Code information. A.2.1 TRIG_Init Description Initializes trigger I/O function of PXIe-3127e/3125e controller.

  • Page 42: Trig_Close

    PXIe-3127e/3125e A.2.2 TRIG_Close Description Closes trigger I/O function of PXIe-3127e/3125e controller, releasing resources allocated for the trigger I/O function. Users must invoke TRIG_Close before exiting the application. Syntax C/C++ I16 TRIG_Close() Visual Basic TRIG_Close() As Integer Parameter None Return Code...

  • Page 43: Trig_Trigger_Route

    0: Logic low 1: Logic high Return Code ERR_NoError ERR_BoardNoInit A.2.4 TRIG_Trigger_Route Description Routes the trigger signal between the trigger I/O SMB connector on the faceplate and the PXI trigger bus on the backplane. This function also allows routing of the software-generated trigger signal to SMB connector or trigger bus.
  • Page 44 PXIe-3127e/3125e Available value Description PXI_TRIG_VAL_TRIG6 PXI trigger bus #6 PXI_TRIG_VAL_TRIG7 PXI trigger bus #7 dest Destination of trigger routing. It can be one of the following values. Available value Description PXI_TRIG_VAL_SMB SMB connector on the faceplate PXI_TRIG_VAL_TRIG0 PXI trigger bus #0...

  • Page 45: Trig_Trigger_Clear

    Return Code ERR_NoError ERR_BoardNoInit ERR_Set_Path A.2.5 TRIG_Trigger_Clear Description Clears the trigger routing setting Syntax C/C++ I16 TRIG_Trigger_Clear() Visual Basic TRIG_Trigger_Clear() As Integer Parameters None Return Code ERR_NoError ERR_BoardNoInit ERR_Trigger_Clr A.2.6 TRIG_GetSoftTrg Description Acquires the current software trigger state, with default state after system boot of Logic Low Syntax C/C++...

  • Page 46: Trig_Trigger_Route_Query

    PXIe-3127e/3125e Returned value: 0: Logic low 1: Logic high Return Code ERR_NoError ERR_BoardNoInit ERR_Query_Status A.2.7 TRIG_Trigger_Route_Query Description Acquires the current trigger signal routing path Syntax C/C++ TRIG_Trigger_Route_Query (U32* source, U32* dest, U32* halfway) Visual Basic TRIG_Trigger_Route_Query (source As Long, dest As Long, halfway As...
  • Page 47 Available Definition Defined Value PXI_TRIG_VAL_TRIG6 PXI_TRIG_VAL_TRIG7 dest Returns to the current destination of trigger routing, with possible values including: Available Definition Defined Value PXI_TRIG_VAL_NONE PXI_TRIG_VAL_SMB PXI_TRIG_VAL_TRIG0 PXI_TRIG_VAL_TRIG1 PXI_TRIG_VAL_TRIG2 PXI_TRIG_VAL_TRIG3 PXI_TRIG_VAL_TRIG4 PXI_TRIG_VAL_TRIG5 PXI_TRIG_VAL_TRIG6 PXI_TRIG_VAL_TRIG7 halfway Returns to the current halfway point of trigger routing, with possible values including: Available Value Description...

  • Page 48: Trig_Getdriverrevision

    PXIe-3127e/3125e Return Code ERR_NoError ERR_BoardNoInit ERR_Query_Status A.2.8 TRIG_GetDriverRevision Description Acquires the PXI Trigger software driver version; format of the version number is major.minor1.minor2 Syntax C/C++ I16 TRIG_GetDriverRevision(unsigned short *major, unsigned short *minor1, unsigned short *minor2) Visual Basic TRIG_GetDriverRevision (major As Integer, minor1 As Integer, minor2...
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  • Page 50: B Appendix: Legacy Boot Mode Settings

    PXIe-3127e/3125e Appendix B Legacy Boot Mode Settings UEFI boot mode is default for the PXIe-3127e/3125e BIOS. To boot in legacy boot mode, change related settings in BIOS menu: 1. Power on and press DEL or ESC to enter BIOS menu 2.
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  • Page 52: Important Safety Instructions

    PXIe-3127e/3125e Important Safety Instructions For user safety, please read and follow all instructions, Warnings, Cautions, and Notes marked in this manual and on the associated device before handling/operating the device, to avoid injury or damage. S'il vous plaît prêter attention stricte à tous les avertissements et mises en garde figurant sur l'appareil , pour éviter des blessures...
  • Page 53 Never attempt to repair the device, which should only be  serviced by qualified technical personnel using suitable tools A Lithium-type battery may be provided for uninterrupted  backup or emergency power. Risk of explosion if battery is replaced with one of an incorrect type;...
  • Page 54 PXIe-3127e/3125e BURN HAZARD Touching this surface could result in bodily injury. To reduce risk, allow the surface to cool before touching. RISQUE DE BRÛLURES Ne touchez pas cette surface, cela pourrait entraîner des blessures. Pour éviter tout danger, laissez la surface refroidir...
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  • Page 56: Getting Service

    PXIe-3127e/3125e Getting Service Contact us should you require any service or assistance. Shanghai Jianyi Technology Co., Ltd. Web Site http://www.jytek.com Address: 上海市浦东新区张江高科技园区芳春路300号 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area, Shanghai,201203,China Tel: +86-21-5047-5899 Email: service@jytek.com...

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