HP 10314D User Manual page 45

Noticed
HP
103140
The preprocessor interface detects the start of an 80386DX bus cycle
when LADS goes true. The preprocessor interface latches address and
status on the following conditions:
• If the 80386DX cycle is a non-pipelined cycle, address and status
are latched during the time that ADS is low.
• If the 80386DX cycle is a pipelined cycle, address and status are
latched during the first CLK2 cycle after READY is detected low.
Data is latched at the end of the 80386DX cycle. The end of the bus
cycle is defined as the rising edge of CLK2 when CLK is high and
LREADY is low. The clock for the logic analyzer is generated
approximately 8 ns after the end of the cycle.
If J9 is in the OFF position, the logic analyzer clock is suppressed when
HLDA is asserted.
Figure 3-2 is the schematic for the HP 10314D. The pin numbers for
connector XWl on the schematic refer to the cable socket on the
preprocessor interface board. Table 2-1 lists the pin numbers for the
preprocessor interface board socket (XWl) and the corresponding pin
numbers (CPU Pin) on the target side of the preprocessor interface
cable.
The schematics on pages 3-6 through 3-10 are supplied only as an aid
to understanding circuit preprocessor interface characteristics. They
are not intended to
be
used as a service or troubleshooting aid. These
schematics are NOT subject to a revision or change program to keep
them current or accurate. ACCORDINGLY,
HEWLETT-PACKARD SHALL NOT BE LIABLE FOR ANY
DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
CONSEQUENTIAL DAMAGES, WHETHER BASED ON
CONTRACT, TORT, OR ANY OTHER LEGAL THEORY
ARISING FROM THE USE OF THESE SCHEMATICS.
80386DX Preprocessor Interface
General Information
3-5