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Timing Format
Specification
Note
9
When the preprocessor interface
is
used for timing analysis, the format
specification 'Will
be
set up as shown in figures 2-8 and 2-9.
( Sta la/Timing E) (
Femat
I
Pod E3
Pod E2
~
_ _ rn. _ _ _,)(
TTL.
j(jjfil)!
Pol
ADDR
+
.......•........
················
~ ~
1-.- .. -.- .. - . . -.. -.. -.. -..
-i ••••••••••••••••
~7
~
t-:;-
~
t-:;-
~
t-:;-
~ I -
................
................
................
................
~
7 . . . . . . -.. -.. -.- .. - . . - .. -.. -..
-!
................
................
§£) (
Run
)
{symbols
J
Ped El
)(
rn.
. .............. .
.
................ .
................
................
Figure 2-8. Timing Format Specification (Pods 1-3)
The timing
format
specification has ten additional
labels
which are
listed offscreen. To view these signals, select the Label field and rotate
the knob on the front panel clockwise.
Analyzing the Intel 80386DX
2-16
HP 103140
80386DX Preprocessor Interface
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