Akai LTA-26C903 Service Manual page 20

7 XTALI
6 VXDD
10,12,14,16 AI21~AI24
13 AI2D
19 AI1D
20 AI11
18 AI12
5,9,15,21,24,26,38 AGND
50,63,76,88,100 VSS
22 AOUT
27 CE
28 LLC
29 LLC2
30 RESON
31 SCL
32 SDA
34 RTS0
35 RTS1
36 RTCO
37 AMCLK
39 ASCLK
40 ALRCLK
41 AMXCLK
42 ITRDY
45 ICLK
46 IDQ
47 ITRI
48 IGP0
driven
by an external single-ended oscillator.
Input terminal for 24.576 (32.11) MHz crystal oscillator or connection
of external oscillator with TTL compatible square wave clock signal.
Crystal oscillator power supply
Analog signal input 21~24
differential input for ADC channel 2 (pins AI24, AI23, AI22, AI21)
differential input for ADC channel 1 (pins AI12, AI11)
analog input 11
analog input 12
ground
Analog test output (do not connect)
Chip Enable or RESET input (with internal pull up)
line-locked system clock output (27 MHz nominal), for backward
compatibility,
do not use for new applications
line locked clock/2 output (13.5 MHz nominal) for backward
compatibility, do
not use for new applications
RESet Output Not signal
IIC serial clock line (with inactive output path)
IIC serial data line
real time status or sync information, controlled by subaddr. "11h and
12h"
RTS1 35 O real time status or sync information, controlled by
subaddr. "11h and 12h"
Real time control output
Audio master clock output
Audio serial clock output
Audio lift/right clock output
Audio master external clock input
Target ready input, image port(with internal pull up)
clock output signal for image-port, LCLK of LPB image port mode, or
optional
asynchron. backend clock input
output data qualifier for image port (optional: gated clock output)
image-port output control signal, effects all I-port pins incl. ICLK,
enable and active polarity is under software control (bits IPE in
subaddr. "87") output path used for Testing: scan output
20