JVC TH-A75R Service Manual page 56

TH-A75R
Pin No. Symbol
103 SCEN
104 MVCKVss
105 ACLKVss
106 SCMD
107 ACLKVdd
108 Vdddac
109 Vssdac
110 Cr/R
111 IOM
112 C/Cb/B
113 Vaa3
114 Y/G
115 Vssa
116 VREF
117 Vaa
118 CVBS/C
119 RSET
120 COMP
121 Vss
122 VCLK
123 VSYNC
124 HSYNC
125 Vddio
126~131 VIO7 - VIO2
132 Vssio
133,134 VIO1,VIO0
135 Vdd
136~139 AD31 - AD28
140 Vddio
141~144 AD27 - AD24
145 PWE3-
146 AD23
147 Vssio
148~153 AD22 - AD17
154 Vddio
155 AD16
156 PWE2-
157,158 AD15,AD14
159 Vdd
160 SCLK
161 ACK
162 Vssio
163~168 AD13 - AD8
169 Vddio
1-56 (No.21189)
I/O
I Scan chain test enable
- Main and video clock PLL ground
- Audio clock PLL ground
I Scan chain test mode
- Audio clock PLL power supply (3.3V)
- DAC digital power supply (1.8V)
- DAC digital ground
O Video DAC3 output (A second composite video; Cr output for composite, Cr output for compo-
nent, Red output for SCART
O Cascaded DAC differential output used to dump current into external resistor for power
O Video DAC2 output (Chrominance output for NTSC/PAL S-Video; Cb output for component, Blue
output for SCART
- DAC analog power supply (3.3V)
O Video DAC1 output (Luminance for S-Video and component, G output for SCART)
- DAC analog ground
- Not connect. (Input voltage reference (1.2V typical) for output DACs)
- Connect to power supply (1.8V)
O Video DAC output (Composite video; Chrominance output for S-Video)
O Current setting resistor of output DACs
O Compensation capacitor connection
- Ground
- Not connect. (VCLK input/output for video I/O port function
- Not connect. (Bi-directional HSYNC signal for devices that do not use end active video/start ac-
tive video (EAV/SAV) codes; can be used as GPIO)
- Not connect. (Bi-directional VSYNC signal for devices that do not use end active video/start ac-
tive video (EAV/SAV) codes; can be used as GPIO)
- Power supply (3.3V)
- Not connect. (Bi-directional digital video port data bus; can be used as GPIO)
- Ground
- Not connect. (Bi-directional digital video port data bus; can be used as GPIO)
- Power supply (1.8V)
I/O uP multiplexed address/data bus
- Power supply (3.3V)
I/O uP multiplexed address/data bus
I/O Byte write enable for FLASH, EEPROM, SRAM or peripherals
I/O uP multiplexed address/data bus
- Ground
I/O uP multiplexed address/data bus
- Power supply (3.3V)
I/O uP multiplexed address/data bus
I/O Byte write enable for FLASH, EEPROM,SRAM or peripherals
I/O uP multiplexed address/data bus
- Power supply (1.8V)
O External bus clock used for programmable host bus peripherals
I/O Programmable WAIT-/ACK-/RDY- control
- Ground
I/O uP multiplexed address/data bus
- Power supply (3.3V)
Function