JVC TH-A75R Service Manual page 35

• Pin function
Pin No. Symbol
1 VDD
2 DQ0
3 VDDQ
4,5 DQ1,DQ2
6 VSSQ
7,8 DQ3,DQ4
9 VDDQ
10,11 DQ5,DQ6
12 VSSQ
13 DQ7
14 N.C
15 VDD
16 DQM0
17 WE
18 CAS
19 RAS
20 CS
21 N.C
22,23 BA0,BA1
24,25~27 A10,A0 - A2
28 DQM2
29 VDD
30 N.C
31 DQ16
32 VSSQ
33,34 DQ17,DQ18
35 VDDQ
36,37 DQ19,DQ20
38 VSSQ
39,40 DQ21,DQ22
41 VDDQ
42 DQ23
43 VDD
44 VSS
45 DQ24
46 VSSQ
47,48 DQ25,DQ26
49 VDDQ
50,51 DQ27,DQ28
52 VSSQ
Power for the input buffers and core logic.
Data input/output are multiplexed on the same pin.
Isolated power supply for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated ground for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated power supply for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated ground for the output buffers to provide improved noise immunity.
Data input/output are multiplexed on the same pin.
This pin is recommended to be left no connection on the device.
Power for the input buffers and core logic.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM.
This pin is recommended to be left no connection on the device.
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, Column address : CA0 ~ CA7
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Power for the input buffers and core logic.
This pin is recommended to be left no connection on the device.
Data input/output are multiplexed on the same pin.
Isolated ground for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated power supply for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated ground for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated power supply for the output buffers to provide improved noise immunity.
Data input/output are multiplexed on the same pin.
Power for the input buffers and core logic.
Ground for the input buffers and core logic.
Data input/output are multiplexed on the same pin.
Isolated ground for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated power supply for the output buffers to provide improved noise immunity.
Data inputs/outputs are multiplexed on the same pins.
Isolated ground for the output buffers to provide improved noise immunity.
Function
TH-A75R
(No.21189)1-35