JVC TH-A75R Service Manual page 32

TH-A75R
Pin No
59
60
61
62
63
64
65
66
67
68
69,70
71
72,73
74
75
76~79
80
81
82~85
86
87
88,89
90
91
92~94
95
96
97~99
100~102
103
104
105~110
111
112
113~118
119
120
121~125
126
127
128
129
130
131~133
134
135
136
137
138 SDO4_1/SDI1_1
139~142 TDO,TDI,TCK,TMS
143
144
1-32 (No.21189)
Symbol I/O
FSR_1 I/O Frame sync for receiver
SCKR_1 I/O Receiver serial clock_1
PINIT/NMI I
TA I
BR O
BB I/O Bus busy
VCCC -
GNDC -
WR O
RD O
AA1,AA0 O
BG I
A0,A1 O
VCCA -
GNDA -
A2~A5 O
VCCA -
GNDA -
A6~A9 O
VCCA -
GNDA -
A10,A11 O
GNDQ -
VCCQL -
A12~A14 O
VCCQH -
GNDA -
A15~A17 O
D0~D2 I/O Data bus
VCCD -
GNDD -
D3,D8 I/O Data bus
VCCD -
GNDD -
D9~D14 I/O Data bus
VCCD -
GNDD -
D15~D19 I/O Data bus
VCCQL -
GNDQL -
D20 I/O Data bus
VCCD -
GNDD -
D21~D23 I/O Data bus
MODD/IRQD I
MODC/IRQC I
MODB/IRQB I
MODA/IRQA I
I/O Serial data output 4_1 / Serial data input 1_1
O/I Test data output,Test data input,Test clock,Test mode select
MOSI/HA0 I/O SPI master-out-sleve-in / I2C slave address 0
MISO/SDA I/O SPI master-in-slave-out / I2C data and acknowkedge
PLL initial / Nonmaskable interrupt
Transfer acknowledge
Bus request
Bus control power
Bus control ground
Write enable
Read enable
Address attribute or row address strobe
Bus grant
Data bus
Address bus power
Address bus ground
Data bus
Address bus power
Address bus ground
Data bus
Address bus power
Address bus ground
Data bus
Quite ground
Quite core (Low) power
Data bus
Quite core (High) power
Address bus ground
Data bus
Data bus power
Data bus ground
Data bus power
Data bus ground
Data bus power
Data bus ground
Quite core (Low) power
Quite core (Low) ground
Data bus power
Data bus ground
Mode select D / External interrupt request D
Mode select C / External interrupt request C
Mode select B / External interrupt request B
Mode select A / External interrupt request A
Function