Table of Contents
Advertisement
DDR3 SO-DIMM_0
5
SO-DIMM A
2
M_A_A[15:0]
M_A_A0
M_A_A1
D
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
Layout Note:
M_A_A9
M_A_A10
signal/space/signal:
M_A_A11
M_A_A12
8 / 4 / 8
M_A_A13
M_A_A14
M_A_A15
2
M_A_BS0
2
M_A_BS1
2
M_A_BS2
2
M_A_CS#0
2
M_A_CS#1
2
M_A_CLK_DDR0
2
M_A_CLK_DDR#0
2
M_A_CLK_DDR1
2
M_A_CLK_DDR#1
2
M_A_CKE0
2
M_A_CKE1
2
M_A_CAS#
2
M_A_RAS#
C
2
M_A_W E#
SA0_DIM0
SA1_DIM0
11,33
SMB_CLK
11,33
SMB_DATA
2
M_A_ODT0
2
M_A_ODT1
2
M0_DM[7:0]
M0_DM0
M0_DM1
M0_DM2
M0_DM3
M0_DM4
M0_DM5
M0_DM6
M0_DM7
2
M_A_DQS[7:0]
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
2
M_A_DQS#[7:0]
M_A_DQS#0
RN1
M_A_DQS#1
B
M_A_DQS#2
10K_8P4R_04
SA0_DIM0
M_A_DQS#3
1
8
SA1_DIM0
M_A_DQS#4
2
7
3.3VS
3
6
M_A_DQS#5
SA1_DIM1
11
M_A_DQS#6
4
5
SA0_DIM1
11
M_A_DQS#7
D02 modify
VTT_MEM
C120
C139
C123
C971
10u_6.3V_X5R_06
10u_6.3V_X5R_06
1u_6.3V_X5R_04
1u_6.3V_X5R_04
1.35V
C121
C138
C137
C140
+
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
A
*330uF_2.5V_12m_6.6*6.6*4.2
1.35V
C129
C130
C131
C132
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
5
4
3
JDIMM1A
M_A_DQ[63:0]
2
M_A_DQ0
98
5
A0
DQ0
M_A_DQ1
97
7
A1
DQ1
M_A_DQ2
96
15
A2
DQ2
95
17
M_A_DQ3
A3
DQ3
M_A_DQ4
92
4
A4
DQ4
M_A_DQ5
91
6
A5
DQ5
M_A_DQ6
90
16
A6
DQ6
86
18
M_A_DQ7
A7
DQ7
M_A_DQ8
89
21
A8
DQ8
M_A_DQ9
85
23
A9
DQ9
M_A_DQ10
107
33
A10/AP
DQ10
84
35
M_A_DQ11
A11
DQ11
M_A_DQ12
83
22
A12/BC#
DQ12
M_A_DQ13
119
24
A13
DQ13
M_A_DQ14
80
34
A14
DQ14
M_A_DQ15
78
36
A15
DQ15
39
M_A_DQ16
DQ16
M_A_DQ17
109
41
BA0
DQ17
M_A_DQ18
108
51
BA1
DQ18
M_A_DQ19
79
53
BA2
DQ19
114
40
M_A_DQ20
S0#
DQ20
M_A_DQ21
121
42
S1#
DQ21
M_A_DQ22
101
50
CK0
DQ22
M_A_DQ23
103
52
CK0#
DQ23
102
57
M_A_DQ24
CK1
DQ24
M_A_DQ25
104
59
CK1#
DQ25
M_A_DQ26
73
67
CKE0
DQ26
M_A_DQ27
74
69
CKE1
DQ27
115
56
M_A_DQ28
CAS#
DQ28
M_A_DQ29
110
58
RAS#
DQ29
M_A_DQ30
113
68
WE#
DQ30
M_A_DQ31
197
70
SA0
DQ31
201
129
M_A_DQ32
SA1
DQ32
202
131
M_A_DQ33
SCL
DQ33
M_A_DQ34
200
141
SDA
DQ34
M_A_DQ35
143
DQ35
M_A_DQ36
116
130
ODT0
DQ36
120
132
M_A_DQ37
ODT1
DQ37
M_A_DQ38
140
DQ38
M_A_DQ39
11
142
DM0
DQ39
M_A_DQ40
28
147
DM1
DQ40
46
149
M_A_DQ41
DM2
DQ41
M_A_DQ42
63
157
DM3
DQ42
M_A_DQ43
136
159
CLOSE TO SO-DIMM_0
DM4
DQ43
M_A_DQ44
153
146
DM5
DQ44
170
148
M_A_DQ45
DM6
DQ45
M_A_DQ46
187
158
DM7
DQ46
M_A_DQ47
160
DQ47
M_A_DQ48
12
163
R121
DQS0
DQ48
1.35V
29
165
M_A_DQ49
DQS1
DQ49
M_A_DQ50
47
175
DQS2
DQ50
M_A_DQ51
64
177
DQS3
DQ51
M_A_DQ52
137
164
DQS4
DQ52
M_A_DQ53
154
166
DQS5
DQ53
171
174
M_A_DQ54
DQS6
DQ54
M_A_DQ55
188
176
DQS7
DQ55
M_A_DQ56
181
DQ56
M_A_DQ57
10
183
DQS0#
DQ57
27
191
M_A_DQ58
DQS1#
DQ58
M_A_DQ59
45
193
DQS2#
DQ59
M_A_DQ60
62
180
CLOSE TO SO-DIMM_0
DQS3#
DQ60
M_A_DQ61
135
182
DQS4#
DQ61
152
192
M_A_DQ62
DQS5#
DQ62
M_A_DQ63
169
194
DQS6#
DQ63
186
DQS7#
R119
1.35V
91-93469-179
C973
C126
6/26 modify
1u_6.3V_X5R_04
1u_6.3V_X5R_04
C141
C142
C143
C144
C145
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
10u_6.3V_X5R_06
C133
C134
C135
C136
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
0.1u_16V_Y5V_04
4
3
2
JDIMM1B
1.35V
75
VDD1
VSS16
76
VDD2
VSS17
81
VDD3
VSS18
82
VDD4
VSS19
87
VDD5
VSS20
88
VDD6
VSS21
93
VDD7
VSS22
94
VDD8
VSS23
3.3VS
99
VDD9
VSS24
100
20mils
VDD10
VSS25
105
VDD11
VSS26
106
VDD12
VSS27
C112
C113
111
VDD13
VSS28
112
VDD14
VSS29
1u_6.3V_X5R_04
*0.1u_16V_Y5V_04
117
VDD15
VSS30
118
VDD16
VSS31
123
VDD17
VSS32
124
VDD18
VSS33
VSS34
199
VDDSPD
VSS35
VSS36
3.3VS
77
NC1
VSS37
122
NC2
VSS38
R118
10K_04
125
NCTEST
VSS39
VSS40
198
11
TS#_DIMM0_1
EVENT#
VSS41
30
2
DRAM_A_RST#
RESET#
VSS42
VSS43
C114
1u_6.3V_X5R_04
VSS44
C115
*0.1u_16V_Y5V_04
MVREF_DQA
MVREF_DQA
1
VREF_DQ
VSS45
126
VREF_CA
VSS46
VSS47
MVREF_DIM0
C116
1u_6.3V_X5R_04
VSS48
C117
*0.1u_16V_Y5V_04
2
VSS1
VSS49
3
VSS2
VSS50
8
VSS3
VSS51
9
VSS4
VSS52
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
VTT1
31
VSS11
VTT2
MVREF_DQA
4.7K_1%_04
32
VSS12
37
VSS13
38
VSS14
R122
C119
43
VSS15
4.7K_1%_04
0.1u_10V_X5R_04
91-93469-179
MVREF_DIM0
4.7K_1%_04
R120
C118
4.7K_1%_04
0.1u_10V_X5R_04
3.3VS
8,11,12,13,15,16,17,19,20,21,23,24,27,30,33,34
1.35V
2,7,11,23,25
VTT_MEM
11,25
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
Title
Title
Title
[10] DDR3 SO-DIMM_0
[10] DDR3 SO-DIMM_0
[10] DDR3 SO-DIMM_0
Size
Size
Size
Document Number
Document Number
Document Number
6-71-W54T0-D01A
6-71-W54T0-D01A
6-71-W54T0-D01A
A3
A3
A3
W 54XTU
W 54XTU
W 54XTU
Date:
Date:
Date:
W ednesday, December 04, 2013
W ednesday, December 04, 2013
W ednesday, December 04, 2013
2
Schematic Diagrams
1
D
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
Sheet 10 of 34
144
145
150
151
DDR3 SO-DIMM_0
155
156
161
162
167
168
C
172
173
178
179
184
185
189
190
195
196
VTT_MEM
203
204
GND1
G1
GND2
G2
B
A
R e v
R e v
R e v
1.0A
1.0A
1.0A
Sheet
Sheet
Sheet
10
10
10
o f
o f
o f
35
35
35
1
DDR3 SO-DIMM_0 B - 11
Advertisement
Table of Contents
