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CPU & PCI Bus Control
By highlighting the "Press Enter" label next to the "CPU & PCI Bus Control"
and press the enter key, it will take you a submenu with the following options:
Figure 4.2: CPU & PCI Bus Control
PCI Master 0 WS Write
When enabled, writes to the PCI bus are executed with zero-wait states.
The Choices: Enabled (default), Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI
specification.
The Choices: Enabled (default), Disabled.
Vlink mode selection
This item allows you to select Vlink mode.
The Choices: By Auto (default), Mode 0 , Mode 1.
PT890 775
18
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