Lanner electronics AP-545L Manual page 44

AMI BIOS SETUP
External Cache : This option specifies the caching algorithm used for L2 secondary
(external) cache memory. The settings are:
Setting
Disabled
Neither L1 internal cache memory on the CPU or L2 secondary cache
memory is enabled.
WriteBack
Use the write-back caching algorithm.
(default)
WriteThru
Use the write-through caching algorithm.
System BIOS Shadow Cacheable : When this option is set to Enabled, the contents of
the F0000h system memory segment can be read from or written to L2 secondary
cache memory. The contents of the F0000h memory segment are always copied from
the BIOS ROM to system RAM for faster execution.
The settings are Enabled or Disabled. The Optimal default setting is Enabled. The
Fail-Safe default setting is Disabled.
C000,16K Shadow
C400,16K Shadow
C800,16K Shadow
CC00,16K Shadow
These options control the location of the contents of the 16KB of ROM beginning at the
specified memory location. If no adaptor ROM is using the named ROM area, this area
is made available to the local bus. The settings are:
Setting
Shadow
The contents of C0000h - C3FFFh are written to the same address in
system memory (RAM) for faster execution.
Cache
The contents of the named ROM area are written to the same address in
system memory (RAM) for faster execution, if an adaptor ROM will be
using the named ROM area. Also, the contents of the RAM area can be
read from and written to cache memory.
Disabled
The video ROM is not copied to RAM. The contents of the video ROM
cannot be read from or written to cache memory.
The default setting is Cache.
In the AMIBIOS for the Intel Triton chipset, the E000h page is used as ROM during
POST, but shadowing is disabled and the ROM CS# signal is disabled to make the
E000h page available on the local bus.
Description
D000,16K Shadow
D400,16K Shadow
D800,16K Shadow
C000,16K Shadow
Description
AP-545L / 38