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Quatech MPAC-100 User Manual

Rs-232 pci synchronous adapter
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SYNCHRONOUS ADAPTER
for PCI Card Standard compatible machines
User's Manual
QUATECH, INC.
662 Wolf Ledges Parkway
Akron, Ohio 44311
MPAC-100
RS-232 PCI
TEL: (330) 434-3154
FAX: (330) 434-1409
www.quatech.com

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Summary of Contents for Quatech MPAC-100

  • Page 1 MPAC-100 RS-232 PCI SYNCHRONOUS ADAPTER for PCI Card Standard compatible machines User's Manual QUATECH, INC. 662 Wolf Ledges Parkway Akron, Ohio 44311 TEL: (330) 434-3154 FAX: (330) 434-1409 www.quatech.com...
  • Page 2 Quatech Inc. warrants the MPAC-100 to be free of defects for one (1) year from the date of purchase. Quatech Inc. will repair or replace any board that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period.
  • Page 3 Quatech, Inc. Quatech, Inc. reserves the right to change this documentation or the product to which it refers at any time and without notice.

  • Page 4: Table Of Contents

    3 Windows 95/98 Installation 4 Other Operating Systems 5 Using the MPAC-100 with Syncdrive 6 Addressing ............
  • Page 5 15 Receive Pattern Character Register 16 Receive Pattern Count Register 17 Receive FIFO Timeout Register 18 External Connections 18.1 5V fuse (pin 9) 18.2 SYNCA (pin 10) 18.3 RING (pin 22) ..........18.4 Null-modem cables 19 DTE Interface Signals 20 PCI Resource Map...

  • Page 7: Introduction

    Because the PCI standard does not include a direct memory access (DMA) interface, the MPAC-100 supports only interrupt-driven communications. To compensate for the lack of DMA, the MPAC-100 is equipped with 1024-byte FIFOs for transmit and receive data. The FIFOs provide for high data throughput with very low interrupt overhead.

  • Page 8: Hardware Installation

    Hardware Installation Hardware installation for the MPAC-100 is a very simple process: 1. Turn off the power of the computer system in which the MPAC-100 is to be installed. 2. Remove the system cover according to the instructions provided by the computer manufacturer.

  • Page 9: Windows 95/98 Installation

    3.1 Using the "Add New Hardware" Wizard The following instructions provide step-by-step instructions on installing the MPAC-100 in Windows 98 using the "Add New Hardware" wizard. Windows 95 uses a similar process to load the INF file from a CD with slightly different dialog boxes.
  • Page 10 3. On the next dialog, select the "CD-ROM drive" checkbox. Insert the Quatech COM CD (shipped with the card) into the CD-ROM drive. Click the "Next" button. 4. Windows should locate the INF file on the CD and display a dialog that looks like this.
  • Page 11 5. Windows will copy the INF file from the CD and display a final dialog indicating that the process is complete. Click the "Finish" button. Quatech MPAC-100 User's Manual...

  • Page 12: Viewing Resources With Device Manager

    3. Double click the device group "Synchronous_Communication". The MPAC-100 model name should appear in the list of adapters. 4. Double click the MPAC-100 model name and a properties box should open for the hardware adapter. Quatech MPAC-100 User's Manual...
  • Page 13 5. Click the "Resources" tab located along the top of the properties box to view the resources Windows has allocated for the MPAC-100 match the hardware configuration. Click "Cancel" to exit without making changes. 6. If changes to the automatic configuration are necessary for compatibility with existing programs, uncheck the "Use Automatic Settings"...

  • Page 14: Dos And Other Operating Systems

    Many DOS applications support user configuration of the base address and IRQ of a serial port. Such applications can generally make use of the MPAC-100. Older applications, as well as some custom software, may use hard-coded standard legacy serial port addresses.
  • Page 15 This program should be run from real DOS, not in a Windows DOS box. Figure 13 shows the Basic Mode display for the MPAC-100 after the "Q" key has been pressed. In this example, the MPAC-100 uses I/O base address FF80 hex and IRQ 11.
  • Page 16 X - EXIT Figure 14 --- QTPCI.EXE Basic Mode display Figure 14 shows the Expert Mode display for the MPAC-100 after the "Q" key has been pressed. The information from the Basic Mode display is presented along with more details such as the Vendor and Device IDs, PCI Class Code, size of memory Quatech MPAC-100 User's Manual be used to make changes.
  • Page 17 I/O regions, etc. Pressing the "N" key will show similar information for all non-Quatech PCI devices in the system, including those devices integrated on the motherboard. In this example, the "Base addr 0" resource is reserved. For users interested in even more details, PCI BIOS information can be displayed by pressing the "B"...

  • Page 18: Using The Mpac-100 With Syncdrive

    Syncdrive, however, is not aware of the plug-and-play nature of PCI cards. A Syncdrive application will expect to see the MPAC-100 at a specific base address and a specific IRQ. When using Syncdrive with PCI cards, it is necessary to obtain the base address and IRQ assigned to the card by using the QTPCI.EXE software utility...

  • Page 19: Addressing

    The MPAC-100 occupies a continuous 16-byte block of I/O addresses. For example, if the base address is set to 300 hex, then the MPAC-100 will occupy address locations 300 hex to 30F hex. If the computer in which the MPAC-100 is installed is running PCI Card and Socket Services, the base address is set by the client driver.

  • Page 20: Interrupts

    Interrupts The MPAC-100 will operate using the interrupt level (IRQ) assigned by the PCI system. Interrupts can come from the SCC, the internal FIFOs or RS-232 test mode. The interrupt source is selected by bits 4 and 5 of the Configuration Register (see page 41).

  • Page 21: Scc General Information

    SCC General Information The Serial Communications Controller (SCC) is a dual channel, multi-protocol data communications peripheral. The MPAC-100 provides a single channel for communications, however, portions of the second channel can be utilized to support some special circumstances. The SCC can be configured to satisfy a wide variety of serial communications applications.

  • Page 22: Accessing The Registers

    SCC. Table 3 on page 26 describes the read registers and Table 4 on page 27 describes the write registers for each channel. The MPAC-100 has been designed to assure that all back to back access timing requirements of the SCC are met without the need for any software timing control. The standard of adding jmp $+2 between I/O port accesses is not required when accessing the MPAC-100.
  • Page 23 These clocks can be programmed in WR11 to come from the RTxC pin, the TRxC pin, the output of the BRG, or the transmit output of the DPLL. The MPAC-100 uses the TRxC pin for its clock-on-transmit and the RTxC pin Quatech MPAC-100 User's Manual ;...
  • Page 24 WR14 Miscellaneous control bits: baud rate generator, DPLL control, auto echo WR15 External/Status interrupt control Table 4 --- SCC write register description For complete information regarding the SCC registers please refer to Zilog's Z85230 technical manual. Quatech MPAC-100 User's Manual...

  • Page 25: Baud Rate Generator Programming

    WR13 (most significant byte). The equation relating the baud rate to the time constant is given below while Table 5 shows the time constants associated with a number of popular baud rates when using the standard MPAC-100 9.8304 MHz clock. Time_Const = Clock_Frequency/ 2* Baud_Rate*Clock_Mode Where: Clock_Frequency = 9.8304 x 10...

  • Page 26: Support For Scc Channel B

    Support for SCC Channel B The MPAC-100 is a single-channel device. Portions of SCC channel B are used to augment channel A. Channel B cannot be used for transmit, but may be used for receive, subject to certain limitations. 8.4.1 Receive data and clock signals The receive data signals RXDA and RXDB are tied together.

  • Page 27: Scc Incompatibility Warnings

    Register Pointer Bits In a Zilog 85230, the control port register pointer bits can be set in either channel. With the implementation on the MPAC-100, however, both parts of an SCC control port access must use the same I/O address.

  • Page 28: Fifo Operation

    These FIFOs are implemented as extensions of the SCC's small internal FIFOs. They have been designed to be as transparent as possible to the software operating the MPAC-100. By using these FIFOs, it is possible to achieve high data rates despite the MPAC-100 not supporting DMA.

  • Page 29: Receive Fifo

    The DMA operation described in this internal FIFOs, and is handled entirely by The MPAC-100 is a single-channel device. Accordingly, most applications will use SCC channel A for both transmit and receive operations. It is possible, however, to use a limited portion of SCC channel B for receive operations (see page 29). The channel used for receive will determine how the SCC must be configured.

  • Page 30: Using Channel A For Both Transmit And

    This is the mode in which most applications will run. Set RXSRC (bit 1) in the Configuration Register to logic 0. This will configure the MPAC-100 to use W/REQA for receive DMA and DTR/REQA for transmit DMA. In addition to any other desired...

  • Page 31: Using Channel B For Receive

    Set RXSRC (bit 1) in the Configuration Register to logic 1. This will configure the MPAC-100 to use W/REQA for transmit DMA and W/REQB for receive DMA. In addition to any other desired...

  • Page 32: Fifo Status And Control

    1 (see page 43). These bits are write-clear, meaning that software must write a 1 to a bit in order to clear it. FIFO-related interrupts will occur only when the MPAC-100 interrupt source is set to INTSCC. See Event Transmit FIFO drained...

  • Page 33: Resetting The Fifos

    The FIFOs are automatically disabled and reset at powerup or when the MPAC-100 is inserted into a PCI socket. The transmit and receive FIFOs can also be independently reset by setting and clearing the appropriate bits in the FIFO Control Register.

  • Page 34: Receive Pattern Detection

    For byte-synchronous operation with simple unique markers in the data stream, this feature may be quite useful. Even if it is not, however, the MPAC-100 can certainly be operated with per-character interrupts enabled and the internal FIFOs disabled. The tradeoff will be a heavier interrupt burden and possibly somewhat lower throughput.

  • Page 35: Receive Fifo Timeout

    With asynchronous operational modes, the same problem exists. Namely, how is one to determine when a reception is complete? While the receive pattern detection may be useful here, the MPAC-100 also offers a timeout feature on the internal receive FIFO.

  • Page 36: Communications Register

    DCE to the remote DTE interface and the return transmission path. The remote device must support remote loopback for this to work. When cleared (logic 0), no testing occurs. Quatech MPAC-100 User's Manual Bit 5 Bit 4 Bit 3...
  • Page 37 TCLK is always transmitted on pin 24 of the DB-25 connector. Bits 1-0: Reserved, always 0. Local Loopback and Remote Loopback cannot be enabled simultaneously. Bits 5 and 4 of the Communications Register should therefore not be set Quatech MPAC-100 User's Manual IMPORTANT (logic 1) simultaneously.

  • Page 38: Configuration Register

    (logic 1), the internal data FIFOs are enabled. If this bit is clear (logic 0), the internal data FIFOs are disabled. (See page 31 for full details on FIFO use.) Quatech MPAC-100 User's Manual Bit 5 Bit 4...
  • Page 39 0, or with SCC channel B by setting RXSRC to logic 1. (See page 29 for information on using channel B.) Receive Transmit Bit 0: Reserved, always 0. Quatech MPAC-100 User's Manual RXSRC = 0 W/REQA DTR/REQA This RXSRC = 1...

  • Page 40: Interrupt Status Register

    The Interrupt Status Register is used to determine the cause of an interrupt generated by the MPAC-100. The address of this register is Base+8. Table 11 details the bit definitions of the register. The interrupt source in the Configuration Register (see page 41) must be set to INTSCC for any of the statuses indicated by this register to occur.

  • Page 41: Fifo Status Register

    This bit is set (logic 1) while the internal transmit FIFO is at least half-full. Bit 0: TXE --- Transmit FIFO Empty: This bit is set (logic 1) when the internal transmit FIFO is completely empty. Quatech MPAC-100 User's Manual Bit 5 Bit 4 Bit 3 Bit 2...

  • Page 42: Fifo Control Register

    TX_RESET --- Reset Transmit FIFO: Set (logic 1), then clear (logic 0) this bit to reset the internal transmit FIFO. The FIFO can be reset only when it is disabled. Quatech MPAC-100 User's Manual Bit 5 Bit 4 Bit 3...

  • Page 43: Receive Pattern Character Register

    Table 14 --- Receive Pattern Character Register - Read/Write Bits 7-0: Receive Pattern Character: the numeric value of the character to be detected. See page 37 for details on the receive character pattern detection feature. Quatech MPAC-100 User's Manual Bit 5 Bit 4 Bit 3 character value (0-255)

  • Page 44: Receive Pattern Count Register

    Pattern Character Register (see page 46) must be consecutively detected for the receive character pattern detect interrupt to be generated. See page 37 for details on the receive character pattern detection feature. Quatech MPAC-100 User's Manual Bit 5 Bit 4...

  • Page 45: Receive Fifo Timeout Register

    FIFO will trigger a timeout condition. This interval assumes eight bits per character, so it will be an approximation for modes running at settings other than eight bits per character. Quatech MPAC-100 User's Manual Bit 5 Bit 4...

  • Page 46: External Connections

    18 External Connections The MPAC-100 is configured as a Data Terminal Equipment (DTE) device, meeting the RS-232-D standard using a DB-25 male connector. There is no DCE version available. The control signals the DTE can generate are Request To Send (RTS) and Data Terminal Ready (DTR).

  • Page 47: Fuse (Pin 9)

    RxCLK (DTE) SYNCA Figure 2 --- MPAC-100 Output Connector The testing signals the DTE can generate are Local Loopback (LL) and Remote Loopback (RL). These signals are asserted with certain bits in the Communications Register. When a Test Mode (TM) condition is received from the DCE, an interrupt can optionally be generated.
  • Page 48 The signal is inverted by the RS-232 receiver, so a positive voltage on pin 22 will assert STSCHG. Table 17 shows the pin configuration of the MPAC-100 DTE connector. The definitions of the interchange circuits according to the RS-232-D standard can be found starting on page 52.

  • Page 49: Null-Modem Cables

    18.4 Null-modem cables The MPAC-100 does not use a standard asynchronous PC serial port connector pinout. Typical off-the-shelf null-modem cables cannot be used with this card! Quatech MPAC-100 User's Manual...

  • Page 50: Dte Interface Signals

    DCE. CIRCUIT CB - CLEAR TO SEND CONNECTOR NOTATION: CTS DIRECTION: From DCE This signal indicates to the DTE whether the DCE is conditioned to transmit data on the communication channel. Quatech MPAC-100 User's Manual...
  • Page 51 CONNECTOR NOTATION: TXCLK (DTE) DIRECTION: To DCE This signal, generated by the DTE, provides the DCE with element timing information pertaining to the data transmitted by the DTE. The DCE can use this information for its received data. Quatech MPAC-100 User's Manual...
  • Page 52 DIRECTION: From DCE This signal indicates to the DTE that the DCE is in a test condition. The DCE generates this signal when it has received a local loopback or remote loopback signal from the DTE. Quatech MPAC-100 User's Manual...

  • Page 53: Pci Resource Map

    20 PCI Resource Map Listed below are the PCI resources used by the MPAC-100. Such information may be of use to customers writing their own device drivers or other custom software. (all numbers in hex) PCI Vendor ID: 0x135C PCI Device ID:...

  • Page 54: Specifications

    Transmit drivers: Receive buffers: I/O Address range: Interrupt levels: DMA channels: Power requirements: Quatech MPAC-100 User's Manual PCI, 32-bit bus, 5 volt only AMCC 5920 PCI Controller approx. 4.5” x 2.5” Zilog Z85230 20-MHz Serial Communications Controller (SCC) Male D-25 connector...
  • Page 55 MPAC-100 User's Manual Revision 1.01 June 2001 P/N 940-0090-220...

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