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Quatech MPAP-100 User Manual

Rs-232 pcmcia synchronous adapter for pcmcia card standard compatible machines
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SYNCHRONOUS ADAPTER
QUATECH, INC.
5675 Hudson Industrial Parkway
Hudson, Ohio 44236
Quatech MPAP-100 User's Manual
MPAP-100
RS-232 PCMCIA
for PCMCIA Card Standard compatible machines
User's Manual
TEL: (330) 655-9000
FAX: (330) 655-9010
www.quatech.com
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  • Page 1 SYNCHRONOUS ADAPTER for PCMCIA Card Standard compatible machines QUATECH, INC. 5675 Hudson Industrial Parkway Hudson, Ohio 44236 Quatech MPAP-100 User's Manual MPAP-100 RS-232 PCMCIA User's Manual TEL: (330) 655-9000 FAX: (330) 655-9010 www.quatech.com...
  • Page 2 Quatech Inc. warrants the MPAP-100 to be free of defects for one (1) year from the date of purchase. Quatech Inc. will repair or replace any board that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period.
  • Page 3 The authors have taken due care in the preparation of this document and every attempt has been made to ensure its accuracy and completeness. In no event will Quatech, Inc. be liable for damages of any kind, incidental or consequential, in regard to or arising out of the performance or form of the materials presented in this document or any software programs that might accompany this document.

  • Page 4: Table Of Contents

    ............1.1 System Requirements 2 Hardware Installation 3 DOS / Windows 3.x Software Installation 3.1 MPAP-100 Client Driver for DOS 3.1.1 DOS client driver installation 3.1.2 Auto Fallback configuration 3.1.3 Hot Swapping 3.2 DOS Client Driver examples...
  • Page 5 22.3.2 Insufficient Number Of Command Line Arguments 22.3.3 Bad Parameters Quatech MPAP-100 User's Manual Table of Contents ....... .

  • Page 6: Introduction

    Because the PCMCIA 2.1 standard does not include a direct memory access (DMA) interface, the MPAP-100 supports only interrupt-driven communications. To compensate for the lack of DMA, the MPAP-100 is equipped with 1024-byte FIFOs for transmit and receive data. The FIFOs provide for high data throughput with very low interrupt overhead.

  • Page 7: Hardware Installation

    3. Attach the narrow connector on the supplied cable to the socket on the end of the MPAP-100. The connector is keyed so that it can only be inserted in one orientation. The connector should attach firmly and smoothly. Do not force the connector into the socket! 4.

  • Page 8: Dos / Windows 3.X Software Installation

    Two DOS configuration software programs are provided with the MPAP-100: a client driver and a card enabler. These programs are executed from DOS (before entering Windows) and allow operation of the MPAP-100 in both the DOS and Windows 3.x environments. Table 1 highlights the differences between these programs.

  • Page 9: Mpap-100 Client Driver For Dos

    MPAP-100 Client Driver for DOS In order to use the MPAP-100 client driver, the system must be configured with Card and Socket Services software. Card and Socket Services software is not provided with the MPAP-100 but is available from Quatech.

  • Page 10: Auto Fallback Configuration

    The client driver supports "hot swapping." After installation, it is not necessary for the MPAP-100 to be inserted in the PCMCIA socket at boot time. When the card is inserted, it will be configured according to the command line options. When the card is removed, the resources it used will be made available for other devices.
  • Page 11 is helpful if the user allows Card Services to select resources instead of specifying them on the command line.

  • Page 12: Dos Client Driver Examples

    Example: Attempt to configure an MPAP-100 inserted into socket 0 with a base address of 300 hex and IRQ 5. Attempt to configure an MPAP-100 inserted into socket 1 with a base address of 340 hex and IRQ 10. This type of configuration may be desirable in systems where more than one MPAP-100 is to be installed.

  • Page 13: Mpap-100 Enabler For Dos

    "Hot Swapping". The enabler must be executed after insertion of an MPAP-100 card. If more than one MPAP-100 is installed in a system, the enabler must be executed separately for each card. A card that is removed and reinserted must be reconfigured by executing the enabler again.
  • Page 14 (no spaces). In the descriptions below, replace the '#' symbols with the appropriate numeric values. The PCMCIA socket into which the MPAP-100 will be inserted. This value is a decimal number ranging from 0 to 15. This parameter is always required when configuring a card.

  • Page 15: Releasing A Card's Configuration

    Use the 'R' parameter to do this. The PCMCIA socket into which the MPAP-100 will be inserted. This value is a decimal number ranging from 0 to 15. This parameter is always required when releasing a card's configuration.

  • Page 16: Dos Enabler Examples

    Example: Configure the MPAP-100 in socket 0 with a base address of 300H and IRQ 5. Software control of SYNCA will be enabled MPAP1EN.EXE (s0,b300,i5,c) Example: Configure the MPAP-100 in socket 1 with a base address of 300H and IRQ 3 using a configuration memory window at segment D800. MPAP1EN.EXE (s1,b300,i3,wd8) Example: Release the configuration used by the MPAP-100 in socket 0.

  • Page 17: Windows 95/98 Installation

    Windows 98 using the "Add New Hardware" wizard. Windows 95 uses a similar process to load the INF file from a floppy disk with slightly different dialog boxes. 1. After inserting an MPAP-100 for the first time, the "Add New Hardware" wizard will start. Click the "Next" button.
  • Page 18 2. Click the "Next" button. Select the radio button for "Search for the best driver for your device." Click the "Next" button to continue. 3. On the next dialog, select the "CD-ROM drive" checkbox. Insert the Quatech COM CD (shipped with the card) into the CD-ROM drive. Click the "Next" button.
  • Page 19 5. Windows will copy the INF file from the CD and display a final dialog indicating that the process is complete. Click the "Finish" button.

  • Page 20: Viewing Resources With Device Manager

    3. Double click the device group "Synchronous_Communication". The MPAP-100 model name should appear in the list of adapters. 4. Double click the MPAP-100 model name and a properties box should open for the hardware adapter. 5. Click the "Resources" tab located along the top of the properties box to view the resources Windows has allocated for the MPAP-100 match the hardware configuration.

  • Page 21: Configuration Options

    6. If changes to the automatic configuration are necessary for compatibility with existing programs, uncheck the "Use Automatic Settings" box and doubleclick on the Resource Type that needs to be changed. Caution should be used to avoid creating device conflicts with other hardware in the system.

  • Page 22: Os/2 Software Installation

    OS/2 Software Installation An OS/2 client driver is provided with the MPAP-100. This client driver works with OS/2's Card and Socket Services to allow operation of the MPAP-100 under OS/2. System Requirements  OS/2 2.1 or later.  OS/2 PCMCIA Card and Socket Services support must be installed. See "Installing OS/2 PCMCIA support"...

  • Page 23: Tying A Configuration To A Particular Socket

    The client driver supports "hot swapping." After installation, it is not necessary for the MPAP-100 to be inserted in the PCMCIA socket at boot time. When the card is inserted, it will be configured according to the command line options. When the card is removed, the resources...

  • Page 24: Os/2 Client Driver Configuration Examples

    IRQ 5. If any of these resources are not available, the card will not be configured. If an MPAP-100 is inserted into socket 2, configure it at base address 110 hex and IRQ 15. If any of these resources are not available, the card will not be configured. Up to two MPAP-100s can be used.
  • Page 25 If PCMCIA support was not selected when OS/2 was installed, add it by using the Selective Install facility in the System Setup folder. Full PCMCIA support is built into OS/2 Warp 3.0 and later. On OS/2 2.1 and 2.11, PCMCIA Card Services is built in, but you must add Socket Services separately.

  • Page 26: Using The Mpap-100 With Syncdrive

    Syncdrive, however, is not aware of the plug-and-play nature of PCMCIA cards. A Syncdrive application will expect to see the MPAP-100 at a specific base address and a specific IRQ. When using Syncdrive with PCMCIA cards, it is necessary to obtain the base address and IRQ assigned to the card by the PCMCIA Card Services and provide those values in the channel configuration array.

  • Page 27: Addressing

    The MPAP-100 occupies a continuous 16-byte block of I/O addresses. For example, if the base address is set to 300 hex, then the MPAP-100 will occupy address locations 300 hex to 30F hex. If the computer in which the MPAP-100 is installed is running PCMCIA Card and Socket Services, the base address is set by the client driver.

  • Page 28: Interrupts

    Interrupts The MPAP-100 will operate using the interrupt level (IRQ) assigned by the PCMCIA system. Interrupts can come from the SCC, the external FIFOs or RS-232 test mode. The interrupt source is selected by bits 4 and 5 of the Configuration Register (see page 41).

  • Page 29: Scc General Information

    SCC General Information The Serial Communications Controller (SCC) is a dual channel, multi-protocol data communications peripheral. The MPAP-100 provides a single channel for communications, however, portions of the second channel can be utilized to support some special circumstances. The SCC can be configured to satisfy a wide variety of serial communications applications.

  • Page 30: Accessing The Registers

    9 read registers. These registers only occupy four address locations, which start at the MPAP-100's physical base address that is configured via the on board switches. This and all other addresses are referenced from this base address in the form Base+Offset. An example of this is Base+1 for the SCC Control Port, Channel A.
  • Page 31 These clocks can be programmed in WR11 to come from the RTxC pin, the TRxC pin, the output of the BRG, or the transmit output of the DPLL. The MPAP-100 uses the TRxC pin for its clock-on-transmit and the RTxC pin for its clock-on-receive. Programming of the clocks should be done before enabling the receiver, transmitter, BRG, or DPLL.
  • Page 32 Interrupt control, Wait/DMA request control Interrupt vector Receiver initialization and control Transmit/Receive miscellaneous parameters and codes, clock rate, stop bits, parity Transmitter initialization and control Sync character (1st byte) or SDLC address field Sync character (2nd byte) or SDLC Flag WR7' Special HDLC Enhancement Register Transmit buffer...

  • Page 33: Baud Rate Generator Programming

    The equation relating the baud rate to the time constant is given below while Table 5 shows the time constants associated with a number of popular baud rates when using the standard MPAP-100 9.8304 MHz clock. Time_Const = Where: Clock_Frequency = 9.8304 x 10...

  • Page 34: Receive Data And Clock Signals

    9.4.3 Extra handshaking for channel A The SCC does not provide a DSR input for either channel. The MPAP-100 routes the DSR signal from the connector to the DCDB input of the SCC. Software can therefore use DCDB as a surrogate for DSR on channel A.

  • Page 35: Scc Incompatibility Warnings

    Register Pointer Bits In a Zilog 85230, the control port register pointer bits can be set in either channel. With the implementation on the MPAP-100, however, both parts of an SCC control port access must use the same I/O address.

  • Page 36: Fifo Operation

    These FIFOs are implemented as extensions of the SCC's small internal FIFOs. They have been designed to be as transparent as possible to the software operating the MPAP-100. By using these FIFOs, it is possible to achieve high data rates despite the MPAP-100 not supporting DMA.

  • Page 37: Receive Fifo

    DMA is not supported between the MPAP-100 and the host computer due to the lack of DMA facilities The MPAP-100 is a single-channel device. Accordingly, most applications will use SCC channel A for both transmit and receive operations. It is possible, however, to use a limited portion of SCC channel B for receive operations (see page 29).

  • Page 38: Using Channel A For Both Transmit And Receive

    This is the mode in which most applications will run. Set RXSRC (bit 1) in the Configuration Register to logic 0. This will configure the MPAP-100 to use W/REQA for receive DMA and DTR/REQA for transmit DMA. In addition to any other desired SCC...

  • Page 39: Using Channel B For Receive

    Set RXSRC (bit 1) in the Configuration Register to logic 1. This will configure the MPAP-100 to use W/REQA for transmit DMA and W/REQB for receive DMA. In addition to any other desired SCC configuration, ensure that the following bits...

  • Page 40: Fifo Status And Control

    43). These bits are write-clear, meaning that software must write a 1 to a bit in order to clear it. FIFO-related interrupts will occur only when the MPAP-100 interrupt source is set to INTSCC. See Table Event Transmit FIFO drained...

  • Page 41: Resetting The Fifos

    10.4.2 Resetting the FIFOs The FIFOs are automatically disabled and reset at powerup or when the MPAP-100 is inserted into a PCMCIA socket. The transmit and receive FIFOs can also be independently reset by setting and clearing the appropriate bits in the FIFO Control Register. Resetting a FIFO sets the appropriate FIFO empty status bit and resets the FIFO's internal read and write pointers.
  • Page 42 SCC into the receive FIFO. When this occurs, the RX_PAT bit in the Interrupt Status Register (see page 43) is set. For instance, the MPAP-100 can watch for the end-of-text character to be received, or for three consecutive pad characters to be received.

  • Page 43: Receive Fifo Timeout

    While the receive pattern detection may be useful here, the MPAP-100 also offers a timeout feature on the external receive FIFO. If the external FIFO is not empty and a time interval equal to a specified number of character-times has elapsed without any further data being received, a receive FIFO interrupt is generated and RX_FIFO bit in the Interrupt Status Register (see page 43) is set.

  • Page 44: Communications Register

    11 Communications Register The Communications Register is used to set options pertaining to the clocks. The source and type of clock to be transmitted or received can be specified. External synchronization and RS-232 DTE test modes and can also be controlled with this register. The address of the Communications Register is Base+4.
  • Page 45 receive unformatted serial data, as it allows the SCC receiver to be manually placed into sync under program control. This bit is ignored if bit 6 is set (logic 1). Bit 3: RCKEN --- Receive Clock Source: set (logic 1), this bit allows the receive clock (RCLK) signal to be generated by the TRxC pin on channel B of the SCC.

  • Page 46: Configuration Register

    FIFOs are present. Other MPA-series products that are not equipped with external data FIFOs, including MPAP-100 Revision A cards, will return 0 in this bit location. Bit 6: Reserved, always 0.
  • Page 47 Bit 1: RXSRC --- Receive FIFO DMA Source: bit determines which SCC pins are used to control transmit and receive DMA transactions between the SCC and the external FIFOs (when enabled). The transmit data FIFO is always used with SCC channel A. The receive data FIFO may be used with SCC channel A by setting RXSRC to logic 0, or with SCC channel B by setting RXSRC to logic 1.

  • Page 48: Interrupt Status Register

    The Interrupt Status Register is used to determine the cause of an interrupt generated by the MPAP-100. The address of this register is Base+8. Table 11 details the bit definitions of the register. The interrupt source in the Configuration Register (see page 41) must be set to INTSCC for any of the statuses indicated by this register to occur.

  • Page 49: Fifo Status Register

    14 FIFO Status Register The FIFO Status Register is used to return current status information about the external FIFOs. The address of this read-only register is Base+9. Table 12 details the bit definitions of the register. This register can be ignored if the external FIFOs are not being used. Bit 7 Bit 6 Table 12 --- FIFO Status Register - Read Only...

  • Page 50: Fifo Control Register

    15 FIFO Control Register The FIFO Control Register is used to control the external data FIFOs. The address of this register is Base+A (hex). Table 13 details the bit definitions of the register. This register can be ignored if the external FIFOs are not being used. Bit 7 Bit 6 EN_PAT...

  • Page 51: Receive Pattern Character Register

    16 Receive Pattern Character Register The Receive Pattern Character Register is used to set the character value to be used in receive pattern detection. The address of this register is Base+B (hex). This register can be ignored if the external FIFOs are not being used. Bit 7 Bit 6 Table 14 --- Receive Pattern Character Register - Read/Write...

  • Page 52: Receive Pattern Count Register

    17 Receive Pattern Count Register The Receive Pattern Count Register is used to set the counter value to be used in receive pattern detection. The address of this register is Base+C (hex). This register can be ignored if the external FIFOs are not being used. Bit 7 Bit 6 Table 15 --- Receive Pattern Count Register - Read/Write...

  • Page 53: Receive Fifo Timeout Register

    18 Receive FIFO Timeout Register The Receive FIFO Timeout Register is used to control the operation of the external receive FIFO timeout feature. The address of this register is Base+D (hex). This register can be ignored if the external FIFOs are not being used. See page 38 for details on the receive FIFO timeout feature.

  • Page 54: External Connections

    19 External Connections The MPAP-100 is configured as a Data Terminal Equipment (DTE) device, meeting the RS-232-D standard using a DB-25 male connector. There is no DCE version available. The control signals the DTE can generate are Request To Send (RTS) and Data Terminal Ready (DTR).

  • Page 55: Synca (Pin 10)

    RS-232 receiver, so a positive voltage on pin 22 will assert STSCHG. Table 17 shows the pin configuration of the MPAP-100 DTE connector. The definitions of the interchange circuits according to the RS-232-D standard can be found starting on page 52.

  • Page 56: Null-Modem Cables

    TXCLK (DTE) TEST MODE * Not included in the official RS-232-D specification 19.3 Null-modem cables The MPAP-100 does not use a standard asynchronous PC serial port connector pinout. Typical off-the-shelf null-modem cables cannot be used with this card! CGND DGND...

  • Page 57: Dte Interface Signals

    20 DTE Interface Signals CIRCUIT AB - SIGNAL GROUND  CONNECTOR NOTATION: DGND  DIRECTION: Not applicable This conductor directly connects the DTE circuit ground to the DCE circuit ground. CIRCUIT BA - TRANSMITTED DATA  CONNECTOR NOTATION: TXD  DIRECTION: To DCE This signal transfers the data generated by the DTE through the communication channel to one or more remote DCE data stations.
  • Page 58 CIRCUIT CC - DCE READY (DATA SET READY)  CONNECTOR NOTATION: DSR  DIRECTION: From DCE This signal indicates the status of the local DCE by reporting to the DTE device that a communication channel has been established. CIRCUIT CD - DTE READY (DATA TERMINAL READY)  CONNECTOR NOTATION: DTR  DIRECTION: To DCE This signal controls the switching of the DCE to the communication channel.
  • Page 59 CIRCUIT DB - TRANSMIT SIGNAL ELEMENT TIMING (DCE SOURCE)  CONNECTOR NOTATION:TXCLK (DCE)  DIRECTION: From DCE This signal, generated by the DCE, provides the DTE with element timing information pertaining to the data transmitted to the DCE. The DCE can use this information for its received data.

  • Page 60: Specifications

    21 Specifications Bus interface: Physical Dimensions: Type II (5 mm) PCMCIA card Controller: DTE Interface: Transmit drivers: Receive buffers: I/O Address range: Interrupt levels: DMA channels: Power requirements: 115 mA at +5 volts, typical PCMCIA PC Card Standard 2.1 85230-compatible 16-MHz Serial Communications Controller (SCC) Male D-25 connector RS-232 compatible,...

  • Page 61: Software Troubleshooting

    I/O devices such as serial ports or modems. If one of these generic client drivers is installed, it may try to configure the MPAP-100 causing the MPAP-100 client driver to fail installation. In these cases, the user should do one of the following: 1.

  • Page 62: Dos Enabler

    The enabler should NOT be used if any Card and Socket Services are present on the system. If Card and Socket Services is installed, the enabler may interfere with its operation and with the device(s) it controls. The client driver should be used to configure the MPAP-100 if Card and Socket Services are installed.
  • Page 63 The base address or IRQ value may be out of range. Make sure that the base address is a hexadecimal number between 100 hex and 3F0 hex ending in 0. Make sure that the IRQ is a decimal number between 2 and 15.
  • Page 64 MPAP-100 User's Manual Revision 2.22 March 2004 P/N 940-0090-222 Quatech MPAP-100 User's Manual...

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