Appendix C: Pll Filter; Figure 28. Pll Block Diagram - Cirrus Logic CS42518-CQ Instructions Manual

CS42518

12 APPENDIX C: PLL FILTER

The PLL has been designed to only use the preambles of the S/PDIF stream to provide lock update infor-
mation to the PLL. This results in the PLL being immune to data dependent jitter effects because the
S/PDIF preambles do not vary with the data.
The PLL has the ability to lock onto a wide range of input sample rates with no external component chang-
es. The nominal center sample rate is the sample rate that the PLL first locks onto upon application of an
S/PDIF data stream.
INPUT
Phase
RM CK
Comparator
VCO
and Charge Pump
RFILT
CRIP
CFILT
÷
N

Figure 28. PLL Block Diagram

77