Cirrus Logic CS42518-CQ Instructions Manual page 4

12 APPENDIX C: PLL FILTER ................................................................................................... 77
12.1. External Filter Components .......................................................................................... 78
12.1.1 General ............................................................................................................. 78
12.1.2 Jitter Attenuation ............................................................................................... 78
12.1.3 Capacitor Selection ........................................................................................... 79
12.1.4 Circuit Board Layout .......................................................................................... 79
13 APPENDIX D: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS ............... 80
13.1. AES3 Receiver External Components .......................................................................... 80
14 APPENDIX E: ADC FILTER PLOTS ..................................................................................... 81
15 APPENDIX F: DAC FILTER PLOTS ..................................................................................... 83
LIST OF FIGURES
Figure 1. Serial Audio Port Master Mode Timing .......................................................................... 11
Figure 2. Serial Audio Port Slave Mode Timing ............................................................................ 11
Figure 3. Control Port Timing - I2C Format ................................................................................... 12
Figure 4. Control Port Timing - SPI Format................................................................................... 13
Figure 5. Typical Connection Diagram .......................................................................................... 18
Figure 6. Typical Connection Diagram with PLL ........................................................................... 19
Figure 7. Full-Scale Analog Input .................................................................................................. 20
Figure 8. Full-Scale Output ........................................................................................................... 21
Figure 9. ATAPI Block Diagram (x = channel pair 1, 2, 3, 4)......................................................... 22
Figure 10. CS42518 Clock Generation ......................................................................................... 24
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Figure 11. I S Serial Audio Formats.............................................................................................. 28
Figure 12. Left Justified Serial Audio Formats .............................................................................. 29
Figure 13. Right Justified Serial Audio Formats ............................................................................ 29
Figure 14. One Line Mode #1 Serial Audio Format....................................................................... 30
Figure 15. One Line Mode #2 Serial Audio Format....................................................................... 30
Figure 16. ADCIN1/ADCIN2 Serial Audio Format ......................................................................... 31
Figure 17. OLM Configuration #1 .................................................................................................. 32
Figure 18. OLM Configuration #2 .................................................................................................. 33
Figure 19. OLM Configuration #3 .................................................................................................. 34
Figure 20. OLM Configuration #4 .................................................................................................. 35
Figure 21. OLM Configuration #5 .................................................................................................. 36
Figure 22. Control Port Timing in SPI Mode.................................................................................. 37
Figure 23. Control Port Timing, I2C Write ..................................................................................... 38
Figure 24. Control Port Timing, I2C Read ..................................................................................... 38
Figure 25. Recommended Analog Input Buffer ............................................................................. 73
Figure 26. Recommended Analog Output Buffer .......................................................................... 73
Figure 27. Channel Status Data Buffer Structure.......................................................................... 75
Figure 28. PLL Block Diagram ...................................................................................................... 77
Figure 29. Jitter Attenuation Characteristics of PLL ...................................................................... 78
Figure 30. Recommended Layout Example .................................................................................. 79
Figure 31. Consumer Input Circuit ................................................................................................ 80
Figure 32. S/PDIF MUX Input Circuit ............................................................................................ 80
Figure 33. TTL/CMOS Input Circuit............................................................................................... 80
Figure 34. Single Speed Mode Stopband Rejection ..................................................................... 81
Figure 35. Single Speed Mode Transition Band............................................................................ 81
Figure 36. Single Speed Mode Transition Band (Detail) ............................................................... 81
Figure 37. Single Speed Mode Passband Ripple.......................................................................... 81
Figure 38. Double Speed Mode Stopband Rejection .................................................................... 81
Figure 39. Double Speed Mode Transition Band .......................................................................... 81
Figure 40. Double Speed Mode Transition Band (Detail).............................................................. 82
Figure 41. Double Speed Mode Passband Ripple ........................................................................ 82
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CS42518