S/Pdif Receiver; 8:2 S/Pdif Input Multiplexer; Error Reporting And Hold Function; Channel Status Data Handling - Cirrus Logic CS42518-CQ Instructions Manual

4.4.

S/PDIF Receiver

The CS42518 includes an S/PDIF digital audio receiver. The S/PDIF receiver accepts and decodes digital
audio data according to the IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. The receiver con-
sists of an 8:2 multiplexer input stage driven through pins RXP0 and RXP1/GPO1 - RXP7/GPO7, a PLL
based clock recovery circuit, and a decoder which separates the audio data from the channel status and
user data. A comprehensive buffering scheme provides read access to the channel status and user data.
External components are used to terminate and isolate the incoming data cables from the CS42518.
These components and required circuitry are detailed in the CDB42518.
4.4.1

8:2 S/PDIF Input Multiplexer

The CS42518 contains an 8:2 S/PDIF Input Multiplexer to accommodate up to eight channels of input dig-
ital audio data. Digital audio data is single-ended and input through the RXP0 and
RXP1/GPO1-RXP7/GPO7 pins. Any one of these inputs can be multiplexed to the input of the S/PDIF
receiver and to the S/PDIF output pin TXP.
When any portion of the multiplexer is implemented, unused RXP0 and RXPx/GPOx pins should be tied
to a 0.01uF capacitor to ground. The receiver multiplexer select line control is accessed through bits
RMUX2:0 in the Receiver Mode Control 2 register on p 61. The TXP multiplexer select line control is ac-
cessed through bits TMUX2:0 in the same register. The multiplexer defaults to RXP0 for both functions.
4.4.2

Error Reporting and Hold Function

While decoding the incoming S/PDIF data stream, the CS42518 can identify several kinds of error, indi-
cated in the register "Receiver Errors (address 26h) (Read Only)" on page 65. See "Error Reporting and
Hold Function" on page 74 for more information.
4.4.3

Channel Status Data Handling

The first 2 bytes of the Channel Status block (C data) are decoded into the Receiver Channel Status reg-
ister (See "Receiver Channel Status (address 25h) (Read Only)" on page 64). See "Channel Status Data
Handling" on page 74 for more information.
4.4.4

User Data Handling

The incoming User (U) data is buffered in a user accessible buffer. If the U data bits have been encoded
as Q-channel subcode, the data is decoded and presented in 10 consecutive register locations, address
30h to 39h. The user can configure the Interrupt Mask Register to cause interrupts to indicate the decod-
ing of a new Q-channel block, which may be read through the control port. See "User (U) Data E Buffer
Access" on page 76 for more information.
4.4.5

Non-Audio Auto-Detection

An S/PDIF data stream may be used to convey non-audio data, thus it is important to know whether the
incoming data stream is digital PCM audio samples or not. This information is typically conveyed in chan-
nel status bit 1 (AUDIO), which is extracted automatically by the CS42518. Certain non-audio sources,
however, such as AC-3
properly set. See "Non-Audio Auto-Detection" on page 76 for more information including details for inter-
face format detection.
®
or MPEG encoders, may not adhere to this convention, and the bit may not be
CS42518
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