SWITCHING CHARACTERISTICS - CONTROL PORT - I
= -10 to +70° C; For DQ, T
Logic 0 = DGND, Logic 1 = VLC, C
SCL Clock Frequency
RST Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
Notes: 16. Data must be held for sufficient time to bridge the transition time, t
17. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
15
18.
-------------------- -
for Single-Speed Mode,
×
256
Fs
R S T
t
irs
Stop
Start
S D A
t
buf
S C L
12
= -40 to +85° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs:
A
= 30 pF)
L
Parameter
t
t
high
hdst
t
t
lo w
hdd
Figure 3. Control Port Timing - I
Symbol
f
scl
t
irs
t
buf
t
hdst
t
low
t
high
t
sust
(Note 16)
t
hdd
t
sud
t
rc
t
fc
t
susp
(Note 17)
t
ack
15
-------------------- -
for Double-Speed Mode,
×
128 Fs
t sud
t ack
2
C Format
2
C FORMAT
Min
Max
-
100
500
-
4.7
-
4.0
-
4.7
-
4.0
-
4.7
-
0
-
250
-
-
1
-
300
4.7
-
-
(Note 18)
, of SCL.
fc
15
----------------- -
for Quad-Speed Mode
×
64 Fs
R e p e a te d
Sta rt
t rd
t
t fc
hdst
t sust
t rc
CS42518
(For CQ, T
A
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
Stop
t fd
t susp
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