Kenwood TK-3402(U) Service Manual page 11

From
T/R SW
(D15)
+B
PC
4. Frequency Synthesizer Unit
4-1. Frequency synthesizer
The frequency synthesizer consists of the TCXO (X1),
VCO, PLL-IC (IC2), and buffer amplifi ers.
The TCXO generates 16.8MHz. The frequency stability is
1.5ppm within the temperature range of –30°C to +60°C. The
frequency tuning and modulation of the TCXO are done to
apply voltage to pin 1 of the TCXO. The output of the TCXO
is applied to pin 1 of PLL-IC.
The VCO consists of 2 VCOs and covers a dual range
of 399.15~469.15MHz and 450~520MHz. The VCO gener-
ates 399.15~469.15MHz for providing the fi rst local signal
for reception. The operating frequency is generated by Q6 in
transmitting mode and Q5 in receiving mode. The oscillation
frequency is controlled by applying the VCO control voltage,
obtained from the phase comparator (IC2) to the variable
capacitance diodes (D5, D9, D11,and D13 in transmitting
mode and D4,D7 and D12 in receiving mode)
The TX/RX pin of IC702 goes "high" in transmitting mode,
causing Q8 to turn off, and Q7 turn on. The TX/RX pin goes
"low" in receiving mode.
The output from Q5 and Q6 are amplifi ed by a buffer am-
plifi er (Q9) and Q2, and then sent to the PLL-IC. The PLL-IC
consists of a prescaler, reference divider, phase comparator,
and charge pump. The input signal from pin 1 and 8 of the
PLL-IC is divided down and compared at the phase compar-
ator. The pulsed output signal of the phase comparator is ap-
plied to the charge pump and transformed into a DC signal
in the loop fi lter (LPF). The DC signal is applied to the CV of
the VCO and locked to keep the VCO frequency constant.
5. Control Circuit
The control consists of the MCU (IC702) and its peripher-
al circuits. It controls the TX-RX unit. IC702 mainly performs
the following;
1) Switching between transmission and reception by PTT
signal input.
2) Reading channel information, frequency, and program
data from the memory circuit.
CIRCUIT DESCRIPTION
Q201 Q206
Pre-DRIVE DRIVE
AMP AMP
R230
VDD
R231
R233
IC200
(1/2)
Fig. 5 Drive and fi nal amplifi er and APC circuit
TK-3402(U)/3402/3407
ANT
Q208 D203,204
RF FINAL ANT
AMP SW
VG
IC200
(2/2)
PLL data is output from PLL_LE (pin 72), PLL_DATA (pin
73) PLL_CLK (pin 74), and PLL_PS (pin 70) of the MCU
(IC702). The data is input to the PLL-IC when the channel is
changed or transmission is changed to reception and vice
versa. The PLL lock condition is always monitored by pin 71
(PLL_LD) of the MCU. When the PLL is unlocked, PLL_LD
goes low.
Q9
TX/RX VCO BUFF
(TX: High)
CV
LPF
IC2
5
PLL
14
PLL_LD
MCU
PLL_LE,PLL_DATA,PLL_CLK,PLL_PS
IC702
Fig. 6 PLL block diagram
3) Sending frequency program data to the PLL.
4) Controlling squelch on/off via the DC voltage from the
squelch circuit.
5) Controlling the audio mute circuit via the decode data in-
put.
6) Transmitting tone and encode data.
Q10 D15
RF
SW To
AMP
RF AMP
Q2 D14
BUFF SW
To mixer
8
VC
TCXO Baseband
1
X1 IC705
11