Epson S1D10605 Series Manual page 38

S1D10605 Series
The Reset Circuit
When the RES input comes to the LOW level, these LSIs return to the default state. Their default states are as follows:
1. Display OFF
2. Normal display
3. ADC select: Normal (ADC command D0 = LOW)
4. Power control register: (D2, D1, D0) = (0, 0, 0)
5. Serial interface internal register data clear
6. LCD power supply bias rate:
S1D10605 *****
S1D10606 *****
10609 *****
S1D10607 *****
7. All-indicator lamps-on OFF (All-indicator lamps ON/OFF command D0 = LOW)
8. Power saving clear
9. V voltage regulator internal resistors Ra and Rb separation
5
(Internal resistors are connected while RES is LOW.)
10. Output conditions of SEG and COM terminals
SEG : V /V , COM : V
2 3
(Both the SEG terminal and the COM terminal output the VDA level while RES is LOW.)
11. Read modify write OFF
12. Static indicator OFF
Static indicator register : (D1, D2) = (0, 0)
13. Display start line set to first line
14. Column address set to Address 0
15. Page address set to Page 0
16. Common output status normal
17. V voltage regulator internal resistor ratio set mode clear
5
18. Electronic volume register set mode clear
Electronic volume register : (D5, D4, D3, D2, D1, D0) = (1, 0. 0, 0, 0, 0)
19. Test mode clear
On the other hand, when the reset command is used, the above default settings from 11 to 19 are only executed.
When the power is turned on, the IC internal state becomes unstable, and it is necessary to initialize it using the RES
terminal. After the initialization, each input terminal should be controlled normally.
Moreover, when the control signal from the MPU is in the high impedance, an overcurrent may flow to the IC. After
applying a current, it is necessary to take proper measures to prevent the input terminal from getting into the high
impedance state.
If the internal liquid crystal power supply circuit is not used, it is necessary that RES is HIGH when the external liquid
crystal power supply is turned on. This IC has the function to discharge V
supply short-circuits to V
While RES is LOW, the oscillator and the display timing generator stop, and the CL, FR, FRS and DOF terminals are
fixed to HIGH. The terminals D0 to D7 are not affected. The V
terminals. This means that an internal resistor is connected between V
36
.......................... 1/9 bias
, 10608 ***** ,
................................. 1/8 bias
.......................... 1/6 bias
/V
1 4
when RES is LOW.
DD
when RES is LOW, and the external power
5
level is output from the SEG and COM output
DD
and V
DD
EPSON
.
5
Rev.2.1