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EN 148
9.
BJ3.1A LA
9.10.4 Diagram B3x, PNX3000HL (IC 7C00)
Block Diagram
SIFIN
VIFIN
DTVIFIN
DTVIFAGC
TUNERAGC
DTVIFPLL
VIFPLL
CVBS0
CVBS1
CVBS2
CVBS/Y3
CVBS/Y4
YCOMB
CCOMB
CVBS_DTV
R1/PR1/V1
G1/Y1/Y1
B1/PB1/U1
R2/PR2/V2
G2/Y2/Y2
B2/PB2/U2
MIC1
MIC2
Pin Configuration
Circuit Descriptions, Abbreviation List, and IC Data Sheets
1 ×
SIFAGC
CVBSOUTIF
QSS
2
SIF
MIXER
AMP
&
AM SND
DEMOD
Fpc
2
IF
2
VIF
VIF
2
SWITCH
AMP
PLL
&
SNDTRAP
DTVIF
MIXER
GROUP
DELAY
CVBS_IF
C3
C4
CLP_PRIM
AM sound
CLP_SEC
CLP_YUV
ICLP
RGB/YUV
MATRIX
&
L1/AMint
SWITCH
R1/AMext
L2/MIC1/PipMono
2
MIC
AMPS
R2/MIC2/AM
2
6.75 MHz
MIC1
MIC2
AM
int
AUDIO SWITCH
(DIGITAL OUT)
R1
R2
R3
R4
R5
L1
L2
L3
L4
L5
AM
EXT
Figure 9-11 Internal block diagram and pin configuration
CVBSOUTA
CVBSOUTB
2NDSIFEXT
(FMRAD)
2nd SIF internal
DTV 1st IF
SWITCH
DTV 2nd IF
&
CVBS/Y_PRIM
A
CVBS
PRIM.
C
SWITCH
VIDEO
IDENT
ICLP
2ndSIF
AGC
DET
CVBS
OUT
VCA
SWITCH
A
&
CVBS
CVBS_SEC
SEC.
SWITCH
ICLP
ICLP
A
Yyuv
D
U
CLK
A
L
A
V
D
D
A
CLK
primary digital audio
R
2
D
secondary digital audio
297 MHz
A
L
2
DATALINK
D
A
R
27 MHz
D
13.5 MHz
ADC
CLOCK
AUDIO SWITCH
(ANALOG OUT)
AUDIO
AMPS
VOLTAGE
CURRENT
DSNDL1
LINEL
SCART2R
DSNDR1
LINER
SCART2L
DSNDL2
SCART1L
DSNDR2
SCART1R
EWVIN
2
DTVOUT
PNX3000
10
D
DATA
4
DLINK1
LINK 1
CLK
297 MHz
2NDSIFAGC
10
DATA
4
DLINK3
LINK 3
D
CLK
297 MHz
DATA
4
DLINK2
10
LINK 2
297 MHz
BGDEC
10
VDEFLO
VDEFLS
VDEFL
BAND
VAUDO
GAP
REF
VAUDS
VAUD
PLL
RREF
VD2V5
54 MHz
XREF
DIVIDER
13.5 or 27 MHz
PLL
CLP_PRIM
HV_PRIM
TIMING
CLP_YUV
CIRCUIT
HV_SEC
CLP_SEC
2
I
C-BUS
TO
IRQ
INTERFACE
MCE430
REW
ADR SCL SDA
EWIOUT
F_15400_131.eps
240505
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