ZiLOG Z08617 Manual page 22

INSTRUCTION SUMMARY (Continued)
Address
Instruction Mode
and Operation dst src
ADC dst, src †
dst ← dst + src + C
ADD dst, src †
dst ← dst + src
AND dst, src †
dst ← dst AND src
CALL dst DA
SP ← SP – 2
IRR
@SP ← PC,
PC ← dst
CCF
C ← NOT C
CLR dst R
dst ← 0
IR
COM dst R
dst ← NOT dst
IR
CP dst, src †
dst – src
DA dst R
dst ← DA dst
IR
DEC dst R
dst ← dst – 1
IR
DECW dst RR
dst ← dst – 1
IR
DI
IMR(7) ← 0
DJNZr, dst RA
r ← r – 1
if r ≠ 0
PC ← PC + dst
Range: +127,–128
EI
←
IMR(7) 1
22
Flags
Opcode Affected
Byte (Hex) C Z S V D H
1[ ] 0
0[ ] 0
5[ ] 0 – –
D6 – – – – – –
D4
EF – – – – –
B0 – – – – – –
B1
6 0 – 0 – –
6 1
A[ ] – –
4 0 X – –
4 1
0 0 – – –
0 1
8 0 – – –
8 1
8 F – – – – – –
r A – – – – – –
r = 0 – F
9 F – – – – – –
Address
Instruction Mode
and Operation dst src
INC dst r
dst ← dst + 1
R
IR
INCW dst RR
dst ← dst + 1
IR
IRET
FLAGS ← @SP;
SP ← SP + 1
PC ← @SP;
SP ← SP + 2;
IMR(7) ← 1
JP cc, dst DA
if cc is true
PC ← dst
IRR
JR cc, dst RA
if cc is true,
PC ← PC + dst
Range: +127,–128
LD dst, src r Im
dst ← src
r R
R r
r X
X r
r Ir
Ir r
R R
R IR
R IM
IR IM
IR R
LDC dst, src r Irr
LDCI dst, src Ir Irr
dst ← src
r ← r + 1;
rr ← rr + 1
®
Z08617 NMOS Z8 8-B MCU
IT
K C
EYBOARD ONTROLLER
Flags
Opcode Affected
Byte (Hex) C Z S V D H
rE – – –
r = 0 – F
2 0
2 1
A 0 – – –
A 1
BF
CD – – – – – –
C = 0 – F
3 0
CB – – – – – –
C = 0 – F
rC – – – – – –
r 8
r 9
r = 0 – F
C7
D7
E3
F 3
E4
E5
E6
E7
F 5
C2 – – – – – –
C3 – – – – – –