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Xycom XVME-240 User Manual page 6

Digital i/o module
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XVME-240 Manual
October, 1984
1.1
INTRODUCTION
The XVME-240
Digital Input/Output Module (hereafter referred to as the DIO module)
VMEbus
provides
arranged to provide 8 (byte-wide) bidirectional I/O ports, 8 interrupt input lines, and
and 8 flag output lines. Each bidirectional port can be programmed to either input or
output data. The 8 interrupt input lines can be used in conjunction with the module
interrupt masking and handling capabilities to generate of VMEbus interrupt on any
level.
Typical applications for the DIO module include:
TTL-level peripheral control of printers and other parallel port devices.
-
Interfacing with OPT0 22 compatible devices to control switch inputs,
-
indicator outputs, and AC/DC applications.
1.2 MANUAL STRUCTURE
The purpose of this first chapter is
and functional capabilities of the DIO module. Successive chapters will develop the
various aspects of module installation and operation in the following progression:
Chapter One - A general description of the DIO module, including complete
functional and environmental specifications, VMEbus
and a block diagram.
Chapter Two - Module installation information covering the location of pertinant
module components, switch and jumper options, external connector pin locations,
and standard board installation information.
Chapter Three - General information needed to use the DIO module including:
module base addressing, module identification data, the Status and Control
register, data port addressing, data direction programming (i.e., Input or Output),
and the interrupt scheme.
The Appendices are designed to introduce and reinforce a variety of module-related
topics including: XYCOM's Standard
tions, a block diagram and schematics, and a quick reference section.
1.3 MODULE OPERATIONAL DESCRIPTION
Figure l- 1 shows an operational block diagram of the DIO module.
MODULE DESCRIPTION
80 TTL-level I/O
systems with
Chapter 1
channels. The I/O channels are
to
introduce the user to the general specifications
I/O
Architecture, backplane
l - l
compliance
information,
signal/pin
descrip-

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