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Inrevium TB-7VX-690T-PCIEXP Hardware User Manual

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TB-7VX-690T/980T/1140T-PCIEXP Hardware User's Manual
TB-7VX-690T/980T/1140T-PCIEXP
Hardware User's Manual
Rev.1.04
Rev.1.04
1

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Summary of Contents for Inrevium TB-7VX-690T-PCIEXP

  • Page 1 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Rev.1.04 Rev.1.04...
  • Page 2 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Revision History Version Date Description Publisher Rev.1.0 2013/5/28 Preliminary Yanagisawa Rev.1.01 2013/12/9 Release Version Yoshioka Rev.1.02 2014/0318 Modified worng informations Yoshioka Rev.1.03 2014/10/7 Additional specification based on FMC4 limitation Yoshioka Rev.1.04 2014/10/27 Added Section 9 Initial Switch Settings Yoshioka Rev.1.04...

  • Page 3: Table Of Contents

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Table of Contents Related Documents and Board Accessories ..................8 Overview ............................8 Feature ............................... 8 Block Diagram ............................ 9 External View of the Board ....................... 10 Board Specification........................... 10 Description of Each Component ...................... 12 7.1.
  • Page 4 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual List of Figures Figure 4-1 Block Diagram ........................9 Figure 5-1 Component Side of the Board ..................10 Figure 6-1 Board Dimension Diagram ....................11 Figure 7-1 Power Supply Structure ....................12 Figure 7-2 Clock Structure ....................... 13 Figure 7-3 Programable Clock Connection ..................
  • Page 5 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Introduction Thank you for purchasing the TB-7VX-690T/980T/1140T-PCIEXP board. Before using the product, be sure to carefully read this user manual and fully understand how to correctly use the product. First read through this manual, then always keep it handy. SAFETY PRECAUTIONS Be sure to observe these precautions Observe the precautions listed below to prevent injuries to you or other personnel or damage to property.
  • Page 6 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Warning In the event of a failure, disconnect the power supply. If the product is used as is, a fire or electric shock may occur. Disconnect the power supply immediately and contact our sales personnel for repair. If an unpleasant smell or smoking occurs, disconnect the power supply.
  • Page 7 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Caution Do not use or place the product in the following locations.  Humid and dusty locations  Airless locations such as closet or bookshelf  Locations which receive oily smoke or steam  Locations exposed to direct sunlight ...

  • Page 8: Related Documents And Board Accessories

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 1. Related Documents and Board Accessories Related documents: All documents relating to this board can be downloaded from our website. Please refer to attached paper of the products. Board Fixer: Fan/heat sink set (Fan: 1, Heat sink: 1, M3 X 20 screw: 2, Washer: 2) XH connector (JST: B3B-XH-A): 1 DDR3-SO-DIMM: 4G byte x2 Board Accessories:...

  • Page 9: Block Diagram

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 4. Block Diagram The following figure shows the block diagram of this board. CLK,ADDR,CMD Xtal 40MHz OSC 25MHz DDR3 SO-DIMM#1(4GB) [TXC] [TXC] [JAE] 7M-40.000MAHE-T 7C-25.000MBA-T DATA[63:0],DQS,DM MM80-204B1-1 OSC 233MHz CLK buffer Programmable CLK OSC 200MHz [IDT] [IDT] [IDT] CL284BB-200.000MHz 4MA233333Z4AACUGI ICS854104AGLF ICS849N202I CLK,ADDR,CMD MMCX connector DDR3 SO-DIMM#2(4GB) [Samtec]...

  • Page 10: External View Of The Board

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 5. External View of the Board The following figures show the external views of the board. Figure 5-1 Component Side of the Board 6. Board Specification External Dimensions: W:312mm x H:130mm (non-compliance with PCI-Express specification) Number of Layers: 16 Layers Board Thickness: 1.7 mm...

  • Page 11: Figure 6-1 Board Dimension Diagram

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Figure 6-1 Board Dimension Diagram Rev.1.04...

  • Page 12: Description Of Each Component

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7. Description of Each Component 7.1. Power Supply Structure The following figure provides the internal power supply structure. The power is provided through a 12V ATX power connector. Power  FPGA: Vccint LTC3855 Connector 1.0V/37.5A FPGA: Vccauxio LTC3600 2.0V/1.28A FMC-Option Board LTM4627 FPGA: Vcco...

  • Page 13: Oscillator

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.2. Oscillator This board provides the following clock sources. FPGA 25Mhz AR26:Bank_11(MC) D35:Bank_17(IO) 200Mhz AT26:Bank_11(MC) C35:Bank_17(IO) AT20:Bank_31(MC) 40Mhz AU20:Bank_31(MC) 200Mhz CN24 (FMC1_MMCX_CLK_P) AU18:Bank_31(SC) AU17:Bank_31(SC) 200Mhz CN25 (FMC1_MMCX_CLK_N) AD8:MGTREFCLK0P_114 AD7:MGTREFCLK0N_114 AF8:MGTREFCLK1P_114 AF7:MGTREFCLK1N_114 G16:Bank_34(MC) G15:Bank_34(MC) K19:Bank_35(MC) J19:Bank_35(MC) AP8:MGTREFCLK0P_112 CN26 AP7:MGTREFCLK0N_112 (FMC2_MMCX_CLK_P)

  • Page 14: Table 7-1 Details Of Onboard Oscillator

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Table 7-1 Details of Onboard Oscillator Signal FPGA Source Signal Name Note Format Pin# DDR3_IF_1_CLK_200MHz_P /N LVDS AR26/AT26 DDR3_IF_1 system clock CLK_200M_P/N LVDS AT20/AU20 User clock DDR3_IF_2_CLK_200MHz_P/N LVDS AU18/AU17 DDR3_IF_2 system clock PCIE_100M_REFCLK_P/N AP8/AP7 Express Edge CN23 PCIE_125M_REFCLK_P/N LVDS...

  • Page 15: Programmable Clock Generator

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.2.1. Programmable clock generator This board has a programmable clock generater “ICS849N202I(U53)” for reference clock of Virtex-7 FPGA GTH Transceiver. The initial setting is below.  ICS849N202I: 156.25MHz  SW5: all OFF. Please used by default settings. If using ICS849N202I for other frequency, please feel free to contact our support web Figure 7-3 Programable Clock Connection Output clock is distributed by Clock buffer(U34) then clocks are provide to each GTH group.

  • Page 16: Clock Switch

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.2.2. Clock Switch Reference clock of GTH is selectable by “SN65LVDS250(U64,U65,U66,U67)” Clock Switch has 4 clock sources and select 2 clocks for GTH reference clock. Figure 7-4 Connection of clock switch Clock Sources ・FMCxx_CLK_P/N: From ICS849N202I programmable clock. ・FMCxx_MMCX_CLK_P/N: From MMCX(CN24,25/CN26,27/CN28,29/CN30.31).

  • Page 17: Fmc Connector Interface

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.3. FMC Connector Interface This board has 4 Samtec FMC connectors. High-Pin Count: 4 (CN14,CN15,CN16,CN17) The following provides the pinout table. Note that all pins are not connected to the FPGA. Figure 7-5 High-Pin Count Pin Layout Rev.1.04...

  • Page 18: Fmc1 Hpc Connector (High-Pin Count)

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.3.1. FMC1 HPC Connector (High-Pin Count) The board uses the High-Pin Count connector. Due to limitation of the number of FPGA pins (Banks), all FMC connector pins are not connected. The connector is interfaced as shown below. HighSpead: TX 10ch, RX 10ch LowSpead: LA 36Pair (include 2 pair clocks) Table 7-3 FMC1 Connector Pinout...
  • Page 19 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Pin No. Bank No. PG_C2M MGTHTXP0_113 DP0_C2M_P MGTHTXN0_113 DP0_C2M_N *1 GBTCLK0_M2C_P Clock Switch *1 GBTCLK0_M2C_N Clock Switch MGTHRXP0_113 DP0_M2C_P MGTHRXN0_113 DP0_M2C_N LA01_P_CC LA01_N_CC LA06_P LA06_N LA05_P LA05_N LA10_P LA09_P LA10_N LA09_N LA13_P LA14_P LA13_N LA14_N...
  • Page 20 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Pin No. Bank No. PG_M2C HA01_P_CC HA01_N_CC HA00_P_CC HA00_N_CC HA05_P HA05_N HA04_P HA04_N HA09_P HA09_N HA08_P HA08_N HA13_P HA13_N HA12_P HA12_N HA16_P HA16_N HA15_P HA15_N HA20_P HA20_N HA19_P HA19_N HB03_P HB03_N HB02_P HB02_N HB05_P HB05_N...
  • Page 21 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Pin No. Bank No. VREF_A_M2C CLK1_M2C_P PRSNT_M2C_L CLK1_M2C_N CLK0_M2C_P CLK0_M2C_N LA00_P_CC LA00_N_CC LA02_P LA02_N LA03_P LA03_N LA04_P LA04_N LA08_P LA08_N LA07_P LA07_N LA12_P LA12_N LA11_P LA11_N LA16_P LA16_N LA15_P LA15_N LA20_P LA20_N LA19_P LA19_N LA22_P...
  • Page 22 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Pin No. Bank No. VREF_B_M2C CLK3_M2C_P CLK3_M2C_N CLK2_M2C_P CLK2_M2C_N HA03_P HA03_N HA02_P HA02_N HA07_P HA07_N HA06_P HA06_N HA11_P HA11_N HA10_P HA10_N HA14_P HA14_N HA17_P_CC HA17_N_CC HA18_P HA18_N HA21_P HA21_N HA22_P HA22_N HA23_P HA23_N HB01_P HB01_N...
  • Page 23 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual *1 GBTCLK0_M2C_P/N, GBTCLK1_M2C_P/N0 It will be MGT reference clock in case it is selected by U64 (clock selector) from FMC option card. *2 FMC1 - JTAG (TDI, TDO) TDI and TDO have a loopback structure for JTAG communication from the FMC mezzanine card. *3 VIO_B_M2C VIO_B_M2C is connected to FMC_VADJ power supply to increase power capacity.

  • Page 24: Fmc2 Hpc Connector (High-Pin Count)

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.3.2. FMC2 HPC Connector (High-Pin Count) The board uses the High-Pin Count connector. Due to limitation of the number of FPGA pins (Banks), all FMC connector pins are not connected. The connector is interfaced as shown below. HighSpead: TX 10ch, RX 10ch LowSpead: LA 36Pair (include 2 pair clocks) Table 7-4 FMC2 Connector Pinout...
  • Page 25 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Pin No. Bank No. PG_C2M MGTHTXP0_116 DP0_C2M_P MGTHTXN0_116 DP0_C2M_N *1 GBTCLK0_M2C_P Clock Switch *1 GBTCLK0_M2C_N Clock Switch MGTHRXP0_116 DP0_M2C_P MGTHRXN0_116 DP0_M2C_N LA01_P_CC LA01_N_CC LA06_P LA06_N LA05_P LA05_N LA10_P LA09_P LA10_N LA09_N LA13_P LA14_P LA13_N LA14_N...
  • Page 26 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. PinNo. Pin No. Bank No. PG_M2C HA01_P_CC HA01_N_CC HA00_P_CC HA00_N_CC HA05_P HA05_N HA04_P HA04_N HA09_P HA09_N HA08_P HA08_N HA13_P HA13_N HA12_P HA12_N HA16_P HA16_N HA15_P HA15_N HA20_P HA20_N HA19_P HA19_N HB03_P HB03_N HB02_P HB02_N HB05_P HB05_N HB04_P...
  • Page 27 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Pin No. Bank No. VREF_A_M2C CLK1_M2C_P PRSNT_M2C_L CLK1_M2C_N CLK0_M2C_P CLK0_M2C_N LA00_P_CC LA00_N_CC LA02_P LA02_N LA03_P LA03_N LA04_P LA04_N LA08_P LA08_N LA07_P LA07_N LA12_P LA12_N LA11_P LA11_N LA16_P LA16_N LA15_P LA15_N LA20_P LA20_N LA19_P LA19_N LA22_P...
  • Page 28 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. PinNo. Bank No. VREF_B_M2C CLK3_M2C_P CLK3_M2C_N CLK2_M2C_P CLK2_M2C_N HA03_P HA03_N HA02_P HA02_N HA07_P HA07_N HA06_P HA06_N HA11_P HA11_N HA10_P HA10_N HA14_P HA14_N HA17_P_CC HA17_N_CC HA18_P HA18_N HA21_P HA21_N HA22_P HA22_N HA23_P HA23_N HB01_P HB01_N HB00_P_CC...
  • Page 29 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual *1 GBTCLK0_M2C_P/N, GBTCLK1_M2C_P/N0 It will be MGT reference clock in case it is selected by U65 (clock selector) from FMC option card. *2 FMC1 -JTAG (TDI, TDO) TDI and TDO have a loopback structure for JTAG communication from the FMC mezzanine card. *3 VIO_B_M2C VIO_B_M2C is connected to FMC_VADJ power supply to increase power capacity.

  • Page 30: Fmc3 Hpc Connector (High-Pin Count)

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.3.3. FMC3 HPC Connector (High-Pin Count) The board uses the High-Pin Count connector. Due to limitation of the number of FPGA pins (Banks), all FMC connector pins are not connected. The connector is interfaced as shown below. HighSpead: TX 10ch, RX 10ch LowSpead: LA 36Pair (include 2 pair clocks) Table 7-5 FMC3 Connector Pinout...
  • Page 31 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Pin No. Bank No. PG_C2M MGTHTXP0_216 DP0_C2M_P MGTHTXN0_216 DP0_C2M_N *1 GBTCLK0_M2C_P Clock Switch *1 GBTCLK0_M2C_N Clock Switch MGTHRXP0_216 DP0_M2C_P MGTHRXN0_216 DP0_M2C_N LA01_P_CC LA01_N_CC LA06_P LA06_N LA05_P LA05_N LA10_P LA09_P LA10_N LA09_N LA13_P LA14_P LA13_N LA14_N...
  • Page 32 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Pin No. Bank No. PG_M2C HA01_P_CC HA01_N_CC HA00_P_CC HA00_N_CC HA05_P HA05_N HA04_P HA04_N HA09_P HA09_N HA08_P HA08_N HA13_P HA13_N HA12_P HA12_N HA16_P HA16_N HA15_P HA15_N HA20_P HA20_N HA19_P HA19_N HB03_P HB03_N HB02_P HB02_N HB05_P HB05_N...
  • Page 33 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Pin No. Bank No. VREF_A_M2C CLK1_M2C_P PRSNT_M2C_L CLK1_M2C_N CLK0_M2C_P CLK0_M2C_N LA00_P_CC LA00_N_CC LA02_P LA02_N LA03_P LA03_N LA04_P LA04_N LA08_P LA08_N LA07_P LA07_N LA12_P LA12_N LA11_P LA11_N LA16_P LA16_N LA15_P LA15_N LA20_P LA20_N LA19_P LA19_N LA22_P...
  • Page 34 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Pin No. Bank No. VREF_B_M2C CLK3_M2C_P CLK3_M2C_N CLK2_M2C_P CLK2_M2C_N HA03_P HA03_N HA02_P HA02_N HA07_P HA07_N HA06_P HA06_N HA11_P HA11_N HA10_P HA10_N HA14_P HA14_N HA17_P_CC HA17_N_CC HA18_P HA18_N HA21_P HA21_N HA22_P HA22_N HA23_P HA23_N HB01_P HB01_N...
  • Page 35 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual *1 GBTCLK0_M2C_P/N, GBTCLK1_M2C_P/N0 It will be MGT reference clock in case it is selected by U66 (clock selector) from FMC option card. *2 FMC1 - JTAG (TDI, TDO) TDI and TDO have a loopback structure for JTAG communication from the FMC mezzanine card. *3 VIO_B_M2C VIO_B_M2C is connected to FMC_VADJ power supply to increase power capacity.

  • Page 36: Fmc4 Hpc Connector (High-Pin Count)

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.3.4. FMC4 HPC Connector (High-Pin Count) The board uses the High-Pin Count connector. Due to limitation of the number of FPGA pins (Banks), all FMC connector pins are not connected. The connector is interfaced as shown below. HighSpead: TX 10ch, RX 10ch LowSpead: LA 36Pair (include 2 pair clocks) Table 7-6 FMC4 Connector Pinout...
  • Page 37 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Pin No. Bank No. PG_C2M MGTHTXP0_213 AN43 DP0_C2M_P MGTHTXN0_213 AN44 DP0_C2M_N *1 GBTCLK0_M2C_P Clock Switch *1 GBTCLK0_M2C_N Clock Switch MGTHRXP0_213 AM41 DP0_M2C_P MGTHRXN0_213 AM42 DP0_M2C_N LA01_P_CC LA01_N_CC LA06_P LA06_N LA05_P LA05_N LA10_P LA09_P LA10_N LA09_N...
  • Page 38 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Pin No. Bank No. PG_M2C HA01_P_CC HA01_N_CC HA00_P_CC HA00_N_CC HA05_P HA05_N HA04_P HA04_N HA09_P HA09_N HA08_P HA08_N HA13_P HA13_N HA12_P HA12_N HA16_P HA16_N HA15_P HA15_N HA20_P HA20_N HA19_P HA19_N HB03_P HB03_N HB02_P HB02_N HB05_P HB05_N...
  • Page 39 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Pin No. Bank No. VREF_A_M2C CLK1_M2C_P PRSNT_M2C_L CLK1_M2C_N CLK0_M2C_P CLK0_M2C_N LA00_P_CC LA00_N_CC LA02_P LA02_N LA03_P LA03_N LA04_P LA04_N LA08_P LA08_N LA07_P LA07_N LA12_P LA12_N LA11_P LA11_N LA16_P LA16_N LA15_P LA15_N LA20_P LA20_N LA19_P LA19_N LA22_P...
  • Page 40 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Pin No. Bank No. VREF_B_M2C CLK3_M2C_P CLK3_M2C_N CLK2_M2C_P CLK2_M2C_N HA03_P HA03_N HA02_P HA02_N HA07_P HA07_N HA06_P HA06_N HA11_P HA11_N HA10_P HA10_N HA14_P HA14_N HA17_P_CC HA17_N_CC HA18_P HA18_N HA21_P HA21_N HA22_P HA22_N HA23_P HA23_N HB01_P HB01_N...
  • Page 41 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual *1 GBTCLK0_M2C_P/N, GBTCLK1_M2C_P/N0 It will be MGT reference clock in case it is selected by U67 (clock selector) from FMC option card. *2 FMC1 -JTAG (TDI,TDO) TDI and TDO have a loopback structure for JTAG communication from the FMC mezzanine card. *3 VIO_B_M2C VIO_B_M2C is connected to FMC_VADJ power supply to increase power capacity.

  • Page 42: Ddr3 So-Dimm Interface

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.4. DDR3 SO-DIMM Interface The board provides 2 Micron DDR3 SO-DIMM(4GByte). On the PCB, bottom side is DIMM1 and top side is DIMM2. Figure 7-6 DIMM1 and DIMM2 Rev.1.04...

  • Page 43: Table 7-7 Ddr3 So-Dimm-1 Pinout

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Table 7-7 DDR3 SO-DIMM-1 Pinout Bank No. Pin No. Signal Name Pin No. Signal Name Pin No. Bank No. VREFDQ AK22 AJ24 AL23 AK21 DQS0# AK23 AJ25 DQS0 AK24 AL21 AM23 AJ22 AM22 AP24 DQ12 AN22 AP22 DQ13 AT24...
  • Page 44 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Signal Name Pin No. Signal Name Pin No. Bank No. AH27 AN25 AH28 AJ27 AK27 AK29 AK26 AL29 AL26 AM27 AM28 AM25 AM26 AN27 AN28 AH29 101 102 AU27 AJ29 CK0# 103 104 CK1# AV27 105 106...
  • Page 45 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Signal Name Pin No. Signal Name Pin No. Bank No. AU30 DQ48 163 164 DQ52 AT30 AV30 DQ49 165 166 DQ53 AT31 167 168 AR31 DQS6# 169 170 AR29 AP31 DQS6 171 172 173 174 DQ54 AU31...

  • Page 46: Table 7-8 Ddr3 So-Dimm-2 Pinout Table

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Table 7-8 DDR3 SO-DIMM-2 Pinout Table Bank No. Pin No. Signal Name Pin No. Signal Name Pin No. Bank No. VREFDQ AJ10 AL11 AM12 AH12 DQS0# AM10 AK11 DQS0 AL10 AJ12 AM11 AJ11 AK13 AP10 DQ12 AP12 AM13 DQ13...
  • Page 47 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Signal Name Pin No. Signal Name Pin No. Bank No. AK18 AM17 AK17 AH17 AJ20 AL20 AK19 AM20 AL19 AN19 AN18 AP17 AR17 AP20 AP19 AL18 101 102 AW19 AM18 CK0# 103 104 CK1# AY19 105 106...
  • Page 48 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Signal Name Pin No. Signal Name Pin No. Bank No. AU13 DQ48 163 164 DQ52 AT15 AV13 DQ49 165 166 DQ53 AT14 167 168 AR14 DQS6# 169 170 AR16 AP14 DQS6 171 172 173 174 DQ54 AT13...

  • Page 49: Pci Express Edge Interface

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.5. PCI Express Edge Interface The board allows a PCI Express x8 (8-Lane) Gen3 connection. Table 7-9 PCI Express Edge Pinout Table Bank No. Pin No. Pin No. Bank No. PRSNT1_B +V12 +V12 +V12 +V12 +V12 JTAG_TCK SMCLK JTAG_TDI...

  • Page 50: Table 7-10 Pci Express Lane Width Configuration

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual Bank No. Pin No. Pin No. Bank No. PETP6 MGTHRXP1_111 PETN6 MGTHRXN1_111 MGTHTXP1_111 PERP6 MGTHTXN1_111 PERN6 PETP7 MGTHRXP0_111 PETN7 MGTHRXN0_111 MGTHTXP0_111 PERP7 MGTHTXN0_111 PERN7 PRSNT2#   The PCI Express lane width depends on the type of a resistor to be installed. Table 7-10 shows PCI Express lane width configuration.

  • Page 51: Pmod Interface

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.6. PMOD Interface The board provides a general PMOD interface. The board has TI : TXS0108EPWR(U47) for signal level exchange purpose. The PMOD connector (CN45) uses SAMTEC : SSW-106-01-F-D. Table 7-11 PMOD Pinout Table FPGA TXS0108EPWR Connector Pin No.

  • Page 52: Qspi-Flash

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.7. QSPI-FLASH The board has 1 x Micron : N25Q512A11G1240F(U54). This QSFP Flash memory is using for user apploication. It is not connected to configuration pins. Figure 7-7 QSPI Layout Table 7-12 QSPI Pinout Table Device FPGA Name Signal Name...

  • Page 53: Usb3.0

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.8. USB3.0 This board has a CYUSB3014(U29) and USB3.0 TYPE-B connector(CN4). Virtex-7 is connecting CYUSB3014 via Spartan3AN but Initial Spartan3AN design is supported USB3.0 bypass function. Table 7-13 USB3.0 Pin Assign Schematic FPGA Signal Name Pin No. Bank Level Comment...

  • Page 54: Led 11

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.9. This board has 12 LEDs. All these LEDs will be turned on when “High” is output from FPGA. Figure 7-8 LED Layout Table 7-14 LED Pinout Table Device FPGA Name Signal Name Pin No. Bank Level LED0 LED0...

  • Page 55: Gpio Interface

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.10. GPIO Interface The board has two 10 pin headers (CN34, CN35) and each connector has 8 signals that are connected to FPGA.(Total 16 signals) The interface has FMC_VADJ (Default: 1.8V) voltage level. Figure 7-9 GPIO Pin Layout Table 7-15 GPIO Pinout Table FPGA CN34...

  • Page 56: Dipsw

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.11. DIPSW The board has three 4 poles DIPSW (SW10, SW11, SW12). When the DIPSW is set to the ON side, it generates “Low” on the associated FPGA pin. Figure 7-10 DIPSW Structure Table 7-16 DIPSW Pinout Table Device FPGA Name...

  • Page 57: Pushsw

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.12. PUSHSW When the PUSHSW is held down, it generates “Low” on the The board has four PUSHSWs. associated FPGA pin. FMC_VADJ R596 4.7K PSW0 SKQYAAE010 PSW0 R597 20_1% C546 0.1uF FMC_VADJ DGND R598 4.7K PSW1 SKQYAAE010 PSW1 R599...

  • Page 58: Power Connector For Fan

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.13. Power Connector for FAN This is a power supply connector for FAN. Figure 7-12 Power Connector for FAN Table 7-18 External Power Supply Connector Pinout Table Type 1pin 2pin 3pin Power Connector for FAN CN38 DGND Sensor 7.14.

  • Page 59: Xadc Pinheader

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 7.15. XADC Pinheader The board has a XADC pinheader connector (CN48). Figure 7-14 XADC Structure Table 7-20 XADC Pinout Table CN48 FPGA Name Signal Name Pin No. Bank Level VP_0 AB23 VN_0 AC22 DXP_0 AD23 DXN_0 AD22 1.8V V7_VCCADC_1P8V...

  • Page 60: Configuration

    TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual 8. Configuration The board allows configuration using microSDCard and NandFlash. Please see “uSD_CONF_UserManual_V7PCIEX_1_**e.pdf” for more detail of microSDCard configuration. 9. Initial Settings This section describes initial settings for all Switch and CN(Jumper). Figure 9-1 location of SW and CN(Juspmer) Table 9-1 Initial Settings Silk No.
  • Page 61 TB-7VX-690T/980T/1140T-PCIEXP Hardware User’s Manual PLD Solution Dept. PLD Division URL: http://solutions.inrevium.com/ E-mail: psd-support@teldevice.co.jp HEAD Quarter: Yokohama East Square, 1-4 Kinko-cho, Kanagawa-ku, Yokohama City, Kanagawa, Japan 221-0056 TEL: +81-45-443-4016 FAX: +81-45-443-4058 Rev.1.04...

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