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Inrevium TB-7V-2000T-LSI Hardware User Manual

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TB-7V-2000T-LSI Hardware User Manual
TB-7V-2000T-LSI
Hardware User Manual
Rev.1.03
1
Rev.1.03

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Summary of Contents for Inrevium TB-7V-2000T-LSI

  • Page 1 TB-7V-2000T-LSI Hardware User Manual TB-7V-2000T-LSI Hardware User Manual Rev.1.03 Rev.1.03...
  • Page 2 TB-7V-2000T-LSI Hardware User Manual Revision History Version Date Description Publisher Rev.1.00 2013/04/25 Release version Amano Rev.1.01 2013/06/21 Modify Table 8-28,Table 8-29,Figure 8-33 Amano Rev.1.02 2013/08/02 Modify Table 8-7,Table 8-15,Table 8-23,Table 9-7,Table 9-17, Amano Table 9-19 Rev.1.03 2013/08/12 Modify Table 9-19 Amano Rev.1.03...

  • Page 3: Table Of Contents

    Table of Contents Related Documents and Accessories ..................14 Overview ............................ 14 Feature ............................15 Block Diagram ........................... 16 4.1. Block diagram of TB-7V-2000T-LSI ..................16 4.2. FPGA Bank Assgin ........................17 4.2.1. Bank assign of XC7V2000T ..................... 17 4.2.2.
  • Page 4 TB-7V-2000T-LSI Hardware User Manual 8.6. RS-232C ........................... 78 8.7. PinHeader ..........................80 8.8. DipSW ............................82 8.9. PushSW............................ 84 8.10. Rotary SW ..........................85 8.11. LED ............................86 8.12. Single Digit LED ........................88 8.13. XADC Pin Header ......................... 90 8.14.
  • Page 5 TB-7V-2000T-LSI Hardware User Manual List of Figures Figure 4-1 Block Diagram ........................ 16 Figure 4-2 Bank Assignments of XC7V2000T.................. 17 Figure 4-3 Bank Assignments of XC7K325T ..................18 Figure 5-1 Component Side ......................19 Figure 5-2 Solder Side ........................19 Figure 7-1 Power Supply Structure ....................
  • Page 6 TB-7V-2000T-LSI Hardware User Manual Figure 8-30 Onboard PinHeaders ....................80 Figure 8-31 Virtex-7 DIPSW Structure ..................... 82 Figure 8-32 Onboard DIPSWs ......................82 Figure 8-33 Virtex-7 PushSW Sructure .................... 84 Figure 8-34 Onboard PushSWs ....................... 84 Figure 8-35 Rotary SW Structure ..................... 85 Figure 8-36 Onboard Rotary SW .....................
  • Page 7 TB-7V-2000T-LSI Hardware User Manual Figure 11-8 iMPACT Window - 2 ....................139 Figure 11-9 iMPACT Window - 3 ....................140 Figure 11-10 iMPACT Window - 4 ....................140 Figure 11-11 iMPACT Window - 5 ....................141 Figure 11-12 iMPACT Window - 6 ....................141 Figure 11-13 iMPACT Window - 7 ....................
  • Page 8 TB-7V-2000T-LSI Hardware User Manual List of Tables Table 7-1 Power Status LEDs (Virtex-7/Spartan-3AN) ..............23 Table 7-2 Power Status LED (Kintex-7).................... 24 Table 7-3 Kintex-7 Bank – Peripheral Device Voltage Selection............26 Table 7-4 VCCADC/VREFP Voltage Selection on Virtex-7 .............. 27 Table 7-5 VCCADC/VREFP Selection on Kintex-7 ................
  • Page 9 TB-7V-2000T-LSI Hardware User Manual Table 8-39 PMODE Jumper Settings ....................69 Table 8-40 CLK Jumper [JP54] Settings ..................70 Table 8-41 OTG ID Jumper [JP55] Settings ..................70 Table 8-42 DVI Rx Pin Assignments ....................73 Table 8-43 DVI Tx Pin Assignments ....................75 Table 8-44 DVI_Rx- DVI_Tx Connections ..................
  • Page 10 TB-7V-2000T-LSI Hardware User Manual Table 9-27 Kintex-7 Dedicted DIPSW Pin Assignments ..............120 Table 9-28 Kintex-7 Dedicated PushSW Pin Assignments ............121 Table 9-29 Kintex-7 Dedicated LED Pin Assignments ..............122 Table 9-30 Kintex-7 XADC Dedicated PinHeader Pin Assignments ..........124 Table 9-31 QSPI Flash Memory for Configuration .................
  • Page 11 TB-7V-2000T-LSI Hardware User Manual Introduction Thank you for purchasing the TB-7V-2000T-LSI board. Before using the product, be sure to carefully read this user manual and fully understand how to correctly use the product. First read through this manual, then always keep it handy.
  • Page 12 TB-7V-2000T-LSI Hardware User Manual Warning In the event of a failure, disconnect the power supply. If the product is used as is, a fire or electric shock may occur. Disconnect the power supply immediately and contact our sales personnel for repair.
  • Page 13 TB-7V-2000T-LSI Hardware User Manual Caution Do not use or place the product in the following locations.  Humid and dusty locations  Airless locations such as closet or bookshelf  Locations which receive oily smoke or steam  Locations exposed to direct sunlight ...

  • Page 14: Related Documents And Accessories

    Switching power supply (Cosel: PLA600F-12 with a power supply cable: 1 2. Overview The TB-7V-2000T-LSI board is an LSI development platform equipped with Xilinx FPGA Virtex-7 Series “2000T” and Kintex-7 Series “325T”. The TB-7V-2000T-LSI board is also equipped with speed grade "-2" FPGA (XC7V2000T-2FLG1925) and speed grade "-2"...

  • Page 15: Feature

    TB-7V-2000T-LSI Hardware User Manual 3. Feature Virtex-7 FPGA “XC7V2000T-2FLG1925” FPGA : Kintex-7 FPGA “XC7K325T-2FFG900” Spartan-3AN FPGA “XC3S700AN-4FGG484C” for configuration only. Connectors : Samtec QTH connectors (120pin) x5 FMC HPC x1 (TED TB-FMCH-VBY1 only)(*1) Memory : 1600Mbps DDR3 SDRAM 2Gbit x8...

  • Page 16: Block Diagram

    TB-7V-2000T-LSI Hardware User Manual 4. Block Diagram 4.1. Block diagram of TB-7V-2000T-LSI Figure 4-1 Block Diagram Rev.1.03...

  • Page 17: Fpga Bank Assgin

    TB-7V-2000T-LSI Hardware User Manual 4.2. FPGA Bank Assgin The following subsections describes the FPGA bank assignments. 4.2.1. Bank assign of XC7V2000T DDR3_C(32bit) DDR3_A(32bit) KINTEX_7 KINTEX_7 DDR3_B(32bit) DDR3_D(32bit) DVI RX PinHeader DVI TX QTH2(CN21) PinHeader Config PSW/LED/ PinHeader USB3.0 QTH1(CN20) QTH3(CN22)

  • Page 18: Bank Assignments Of Xc7K325T

    TB-7V-2000T-LSI Hardware User Manual 4.2.2. Bank assignments of XC7K325T QTH5(CN32) PSW/LED DIPSW Config Virtex_7 (QSPI) QTH4(CN31) Virtex_7 Figure 4-3 Bank Assignments of XC7K325T Rev.1.03...

  • Page 19: External View Of The Board

    TB-7V-2000T-LSI Hardware User Manual 5. External View of the Board Figures 5-1 and 5-2 show the external view of the TB-7V-2000T-LSI board. PCI Express V7 MMCX Single Digit V7 XADC Power V7 Option Connector Connector LVDS 1/2 PinHeader OSC 1/2...

  • Page 20: Board Specifications

    The following shows the board specifications. External dimensions: W:400.00mm x H:300.00mm Number of layers: 20 Board Thickness: 2.4mm Material: FR-5 or equivalent Weight: About 1.2kg (excluding FAN/heat sink and power supply) *For board dimensions, refer to Appendix “ TB-7V-2000T-LSI Board Dimensions.pdf“. Rev.1.03...

  • Page 21: Power Supply/Clock (Virtex-7/Kintex-7)

    TB-7V-2000T-LSI Hardware User Manual 7. Power Supply/Clock (Virtex-7/Kintex-7) 7.1. Power Supply Structure Figure 7-1 shows the internal power supply structure. DC JACK x 2 12V/40A FPGA(Virtex-7) 5.0V/15A [TI] [TI] 1.0V/60A [Molex] TPS56121DQPT PTH0404WAZ (CORE) 39-30-0060 FPGA(Virtex-7) [TI] 1.8V/15A TPS56121DQPT (IO)

  • Page 22: Power Input

    TB-7V-2000T-LSI Hardware User Manual FPGA（Spartan-3AN） [TI] 3.3V/2A TPS54327DDAR (IO/VCCAUX) FPGA（Spartan-3AN） [TI] 1.2V/500mA TPS73512DRBT (CORE) FPGA（Spartan-3AN） [TI] 1.8V/200mA TLV70018DSET (IO) Option [TI] 2.5V/2A TPS54327DDAR (FMC/QTH) Option [TI] 3.3V/15A TPS56121DQPT (FMC/QTH) Option [TI] 5.0V/25A TPS56221DQPT (DVI/QTH) Option 12V/40A (QTH) Figure 7-1 Power Supply Structure 7.1.1.

  • Page 23: Power Supply Status Checking

    TB-7V-2000T-LSI Hardware User Manual 7.1.2. Power Supply Status Checking The current status of power supplies can be verified on the following power status LEDs (if the power status LED is blinking and continuously red, the power supply is functional). In the following table, V7 refers to Virtex-7, K7 to Kintex-7 and S3 to Spartan-3AN.

  • Page 24: Figure 7-4 Power Sutatus Leds (Kintex-7)

    TB-7V-2000T-LSI Hardware User Manual Table 7-2 Power Status LED (Kintex-7) Power Status Voltage Color K7_ VCCINT+1.0V LED49 K7 VCCINT +1.0V K7_ VCC+2.5V LED50 K7 VCCIO +2.5V K7_ MGTAVTT+1.2V LED51 K7 MGTAVTT +1.2V K7_ VCC_CF LED52 QSPI Flash Memory K7_ VCC+3.3V...

  • Page 25: Kintex-7 Fpga Bank Voltage Selection

    TB-7V-2000T-LSI Hardware User Manual 7.1.3. Kintex-7 FPGA Bank Voltage Selection The following peripheral devices shown in Figure 7-5 are connected to the Kintex-7. The QTH and FMC connectors allow the developers to select an appropriate KIntex-7 bank voltage (VCCIO) by setting onboard jumpers (JP94/95/102) to meet the voltage requirements (1.8V, 2.5V or 3.3V) of the connected interfaces.

  • Page 26: Figure 7-6 Bank Voltage Setting Location On Fpga (Kintex-7)

    TB-7V-2000T-LSI Hardware User Manual Table 7-3 Kintex-7 Bank – Peripheral Device Voltage Selection Voltage Selection Bank Connected Device Voltage JP No. 1.8V 2.5V 3.3V FMC_HPC(CN34) JP94 5-6uit Variable HR13/14/15 QTH4(CN31) (1.8V/2.5V/3.3V) JP102 QSPI,DSW, UART FMC_HPC(CN34) Variable HR16/17/18 QTH5(CN32) JP95 (1.8V/2.5V/3.3V) LED,PSW Be sure to set JP94 and JP102 to the same pin settings.

  • Page 27: Xadc Power Supply On Virtex-7

    TB-7V-2000T-LSI Hardware User Manual 7.1.3.1. XADC Power Supply on Virtex-7 VCCADC (XADC analog circuit power supply) can be supplied either at V7_VCC+1.8V or V7_VCCADC+1.8V. This supply voltage selection is made using JP39. VREFP (differencial reference voltage to the A/D conversion process) can be supplied either at V7_XADC_AGND or V7_VREFP+1.25V.

  • Page 28: Xadc Power Supply On Kintex-7

    TB-7V-2000T-LSI Hardware User Manual 7.1.3.2. XADC Power Supply on Kintex-7 VCCADC (XADC analog circuit power supply) can be supplied either from a K7_VCC+1.8V or CN28 9pin. This supply voltage selection is made using JP92. VREFP (differential reference voltage to the A/D conversion process) can be supplied either from a V7_XADC_AGND or CN28 11pin.

  • Page 29: Pm Bus Interface (Cn5)

    PM Bus Interface is used to configure the TI UCD9090 (power supply sequence and management) chip. For information about PM Bus, refer to the UCD9090 data sheet. The TB-7V-2000T-LSI board has the already configured default PM Bus Interface to meet the FPGA specification requirements (no need to change the configuration).

  • Page 30: Clock Source

    TB-7V-2000T-LSI Hardware User Manual 7.2. Clock Source The TB-7V-2000T-LSI board provides the clock sources as shown in Figure 7-11. IC26 Virtex-7 IC40 CN20 LVDS LVDS LVDS Bank33:AT19 200MHz K41:Bank21 Bank33:AU19 K42:Bank21 LVDS Bank33:AV19 LVDS F28:Bank18 Bank33:AV18 LVDS E28:Bank18 Bank31:AP11 LVDS...

  • Page 31: Figure 7-11 Clock Structure

    TB-7V-2000T-LSI Hardware User Manual IC72 CN31 LVDS Kintex-7 C25:Bank16 Bank13:AD27 B25:Bank16 Bank13:AD28 LVDS CN36 LVDS Bank13:AB27 K7_MMCX1_P R28:Bank14 Bank13:AC27 K7_MMCX1_N T28:Bank14 LVDS CN38 Bank13:AG29 CN37 Bank13:AH29 LVDS LVDS K7_MMCX2_P D26:Bank16 Bank14:U27 K7_MMCX2_N C26:Bank16 Bank14:U28 CN39 QTH4 LVDS Bank14:T25 Connector IC81...
  • Page 32 TB-7V-2000T-LSI Hardware User Manual Connection Signal Name Pin No. Remarks Virtex-7 CN10/12 V7_MMCX1_P/N LVDS AE40/AF40 MMCX external clock Virtex-7 CN11/13 V7_MMCX2_P/N LVDS AA38/AA39 MMCX external clock Via 1to2 buffer X10(250MHz) V7_CLK250M1_P/N LVDS BA8/BA7 MGT reference clock Via 1to2 buffer X10(250MHz)
  • Page 33 TB-7V-2000T-LSI Hardware User Manual Connection Signal Name Pin No. Remarks CN22 S3_LVDS47_CLK_P/N AL37/AL38 LVDS QTH3 IF clock (QTH3 Connector) S3_LVDS_CLK1_P/N AK36/AK37 1to2 via differential buffer X2(74.25MHz) K7_CLK74M_P/N LVDS C25/B25 Kintex-7 clock Kintex-7 CN36/38 K7_MMCX1_P/N LVDS R28/T28 MMCX external clock Kintex-7...

  • Page 34: Kintex-7 Mgt Reference Clock Selector

    TI’s SN65LVDS250DBT is a 4-input 4-output differential clock selector. Each output can select any of the input clock sources in accordance with the SW26 setting. The TB-7V-2000T-LSI board does not use Channel 4 (4A, 4B, 4Y, 4Z, S40 and S41). Thus, SW26-7 and -8 are reserved.

  • Page 35: Virtex-7 Interface

    8. Virtex-7 Interface 8.1. DDR3 SDRAM The TB-7V-2000T-LSI board is equipped with eight (8) ELPIDA’s DDR3 SDRAMs (EDJ2116DEBG-xx-x). All addresses, commands and clocks are connected using the fly-by termination scheme that is used for SO-DIMM. In addition, A14 is connected for expansion purposes.

  • Page 36: Figure 8-2 Ddr3 Sdram Connections

    TB-7V-2000T-LSI Hardware User Manual The DDR3 Memory is segmented into four (4) groups as shown in Figure 8-2. FPGA A[14:0],BA[2:0],CK,/CK,/CS,/RAS, Bank21 /CAS,CKE,/WE,ODT /RESET GroupA DDR３ SDRAM(2Gbit) DQU[7:0],DQL[7:0],DQSU,/DQSU, (IC32) DQSL,/DQSL,DMU,DML Bank22 DDR３ SDRAM(2Gbit) DQU[7:0],DQL[7:0],DQSU,/DQSU, (IC33) DQSL,/DQSL,DMU,DML A[14:0],BA[2:0],CK,/CK,/CS,/RAS, Bank18 /CAS,CKE,/WE,ODT /RESET GroupB DDR３...

  • Page 37: Table 8-1 Ddr3 Sdram And Virtex-7 Pin Assignment Table

    TB-7V-2000T-LSI Hardware User Manual Table 8-1 DDR3 SDRAM and Virtex-7 Pin Assignment Table DDR3 IC32 IC33 IC34 IC35 Pin Name Pin No. Bank Pin No. Bank Pin No. Bank Pin No. Bank /RAS /CAS /RESET DQU7 DQU6 DQU5 DQU4 DQU3...
  • Page 38 TB-7V-2000T-LSI Hardware User Manual IC36 IC37 IC38 IC39 DDR3 Pin Name Pin No. Bank Pin No. Bank Pin No. Bank Pin No. Bank /RAS /CAS /RESET DQU7 DQU6 DQU5 DQU4 DQU3 DQU2 DQU1 DQU0 AA10 DQL7 DQL6 DQL5 DQL4 DQL3...

  • Page 39: Qth Connector

    8.2. QTH Connector The TB-7V-2000T-LSI board is equipped with five SAMTEC’s 120pin QTH connectors that allow high speed data connection to external devices. Each connector provides up to 56 pairs of LVDS signal connections, including 8 pairs of clock signals (or 119 single-pin connections).

  • Page 40: Table 8-3 Qth1 B55 Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual B55 Pin Either 5V or FPGA (Virtex-7) is selectable by setting the jumper as shown in Table 8-3. Currently the FPGA (Virtex-7) connection is not available due to non-implementation of R1036). Table 8-3 QTH1 B55 Pin Assignments...

  • Page 41: Table 8-7 Qth1 B59 Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual B59 Pin Either QTH1_VCC or FPGA (Virtex-7) is selectable by setting the jumper as shown in Table 8-7. QTH1_VCC is selectable by the jumper JP62. Currently the FPGA (Virtex-7) connection is not available due to non-implementation of R1040).

  • Page 42: Table 8-9 Qth1 Connector (Cn20) Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual Table 8-9 QTH1 Connector (CN20) Pin Assignments FPGA (Virtex-7) QTH1 (CN20) FPGA (Virtex-7) Signal Name Signal Name Bank Pin# Pin Name Pair Pin# Pin# Pair Pin Name Pin# Bank AT12 IO_L12N_T1_MRCC_31 S1_LVDS_CLK0_N S1_LVDS0_N IO_L2N_T0_31 AJ10 AR12 IO_L12P_T1_MRCC_31...
  • Page 43 TB-7V-2000T-LSI Hardware User Manual FPGA (Virtex-7) QTH1 (CN20) FPGA (Virtex-7) Signal Name Signal Name Bank Pin# Pin Name Pair Pin# Pin# Pair Pin Name Pin# Bank AP14 IO_L20N_T3_32 S1_LVDS23_N S1_LVDS24_N/VREF IO_L6N_T0_VREF_32 BA13 AN14 IO_L20P_T3_32 S1_LVDS23_P S1_LVDS24_P IO_L6P_T0_32 BA14 BD14 IO_L2N_T0_32...
  • Page 44 TB-7V-2000T-LSI Hardware User Manual FPGA (Virtex-7) QTH1 (CN20) FPGA (Virtex-7) Signal Name Signal Name Bank Pin# Pin Name Pair Pin# Pin# Pair Pin Name Pin# Bank AU19 IO_L11N_T1_SRCC_33 S1_LVDS47_N/CLK_N N S1_LVDS48_N IO_L1N_T0_33 BC21 AT19 IO_L11P_T1_SRCC_33 S1_LVDS47_P/CLK_P P S1_LVDS48_P IO_L1P_T0_33 BB21...

  • Page 45: Qth2 Power Supply Pinout

    TB-7V-2000T-LSI Hardware User Manual 8.2.2. QTH2 Power Supply Pinout H1 Pin OP+3.3V power supply (currently not available due to non-implementation of R635). H2 Pin OP+3.3V power supply (currently not available due to non-implementation of R636). B54 Pin Any 5V, 12V or FPGA (Virtex-7) is selectable by setting the jumper as shown in Table 8-10.

  • Page 46: Table 8-13 Qth2 B57 Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual B57 Pin Either 5V or FPGA (Virtex-7) is selectable by setting the jumper as shown in Table 8-13. Currently the FPGA (Virtex-7) connection is not available due to non-implementation of R1042). Table 8-13 QTH2 B57 Pin Assignments...

  • Page 47: Table 8-17 Qth2 Connector (Cn21) Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual Table 8-17 QTH2 Connector (CN21) Pin Assignments FPGA (Virtex-7) QTH2(CN21) FPGA (Virtex-7) Signal Name Signal Name Bank Pin# Pin Name Pair Pin# Pin# Pair Pin Name Pin# Bank AU27 IO_L12N_T1_MRCC_35 S2_LVDS_CLK0_N S2_LVDS0_N IO_L1N_T0_AD4N_35 BD26 AU26 IO_L12P_T1_MRCC_35...
  • Page 48 TB-7V-2000T-LSI Hardware User Manual FPGA (Virtex-7) QTH2(CN21) FPGA (Virtex-7) Signal Name Signal Name Bank Pin# Pin Name Pair Pin# Pin# Pair Pin Name Pin# Bank BD31 IO_L4N_T0_36 S2_LVDS23_N S2_LVDS24_N/VREF IO_L6N_T0_VREF_36 BB30 BD30 IO_L4P_T0_36 S2_LVDS23_P S2_LVDS24_P IO_L6P_T0_36 BA30 BA33 IO_L5N_T0_36 S2_LVDS25_N...
  • Page 49 TB-7V-2000T-LSI Hardware User Manual FPGA (Virtex-7) QTH2(CN21) FPGA (Virtex-7) Signal Name Signal Name Bank Pin# Pin Name Pair Pin# Pin# Pair Pin Name Pin# Bank AR23 IO_L14N_T2_SRCC_34 S2_LVDS47_N/CLK_N N S2_LVDS48_N IO_L24N_T3_34 AJ24 AP23 IO_L14P_T2_SRCC_34 S2_LVDS47_P/CLK_P P S2_LVDS48_P IO_L24P_T3_34 AJ23 AM22...

  • Page 50: Qth3 Power Supply Pinout

    TB-7V-2000T-LSI Hardware User Manual 8.2.3. QTH3 Power Supply Pinout H1 Pin OP+3.3V power supply (currently not available due to non-implementation of R645). H2 Pin OP+3.3V power supply (currently not available due to non-implementation of R646). B54 Pin Any 5V, 12V or FPGA (Virtex-7) is selectable by setting the jumper as shown in Table 8-18.

  • Page 51: Table 8-22 Qth3 B58 Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual B58 Pin Either TRAD or FPGA (Virtex-7) is selectable by setting the jumper as shown in Table 8-22. Currently the FPGA (Virtex-7) connection is not available due to non-implementation of R1051). Table 8-22 QTH3 B58 Pin Assignments...

  • Page 52: Table 8-25 Qth3 Connector (Cn22) Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual Table 8-25 QTH3 Connector (CN22) Pin Assignments FPGA (Virtex-7) QTH3(CN22) FPGA (Virtex-7) Signal Name Signal Name Bank Pin# Pin Name Pair Pin# Pin# Pair Pin Name Pin# Bank BA40 IO_L12N_T1_MRCC_11 S3_LVDS_CLK0_N S3_LVDS0_N IO_L1N_T0_11 AW41 AY40 IO_L12P_T1_MRCC_11 S3_LVDS_CLK0_P...
  • Page 53 TB-7V-2000T-LSI Hardware User Manual FPGA (Virtex-7) QTH3(CN22) FPGA (Virtex-7) Signal Name Signal Name Bank Pin# Pin Name Pair Pin# Pin# Pair Pin Name Pin# Bank AV37 IO_L24N_T3_12 S3_LVDS23_N S3_LVDS24_N/VREF IO_L6N_T0_VREF_12 AP36 AV36 IO_L24P_T3_12 S3_LVDS23_P S3_LVDS24_P IO_L6P_T0_12 AN36 AV34 IO_L22N_T3_12 S3_LVDS25_N...
  • Page 54 TB-7V-2000T-LSI Hardware User Manual FPGA (Virtex-7) QTH3(CN22) FPGA (Virtex-7) Signal Name Signal Name Bank Pin# Pin Name Pair Pin# Pin# Pair Pin Name Pin# Bank AL37 IO_L11P_T1_SRCC_13 S3_LVDS47_N/CLK_N S3_LVDS48_N IO_L1N_T0_13 AK41 AL38 IO_L11N_T1_SRCC_13 S3_LVDS47_P/CLK_P S3_LVDS48_P IO_L1P_T0_13 AJ41 AH44 IO_L2N_T0_13 S3_LVDS49_N...

  • Page 55: Pci Express / Gtx Connector

    8.3. PCI Express / GTX Connector The TB-7V-2000T-LSI board is equipped with two SAMTEC’s ”x8”(8Lane) connectors. The CN23 can be used as a PCI Express connector and the CN24 as a GTX connector. (the CN24 cannot be used a PCI Express connector).

  • Page 56: Table 8-26 Virtex-7 - Pci Express Connector [Cn23] Signal Connections

    TB-7V-2000T-LSI Hardware User Manual The following table lists the signal connections between the FPGA (Virtex-7) and the PCI Express Connector [CN23]. Table 8-26 Virtex-7 - PCI Express Connector [CN23] Signal Connections PCI Express Connector1(CN23) FPGA (Virtex-7) Signal Name Pin No.

  • Page 57: Table 8-27 Pci Express Connector [Cn23] Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual Table 8-27 shows the PCI Express Connector pin assignments. Table 8-27 PCI Express Connector [CN23] Pin Assignments CN23 CN23 Pin Name Signal Pin Name Signal B Side A Side +12 V PRSNT1# (PCIe1 PRSNT SEL) +12 V...
  • Page 58 TB-7V-2000T-LSI Hardware User Manual CN23 CN23 Pin Name Signal Pin Name Signal B Side A Side PETn6 PCIE1_RX6_N PERp6 PCIE1_TX6_P PERn6 PCIE1_TX6_N PETp7 PCIE1_RX7_P PETn7 PCIE1_RX7_N PERp7 PCIE1_TX7_P PRSNT2# (PCIe1 PRSNT SEL) PERn7 PCIE1_TX7_N Rev.1.03...

  • Page 59: Table 8-28 Signal Connections Between Virtex-7 And Gtx Connector [Cn24]

    TB-7V-2000T-LSI Hardware User Manual Table 8-28 shows the signal connections between FPGA (Virtex-7) and GTX connector [CN24]. Table 8-28 Signal Connections between Virtex-7 and GTX Connector [CN24] GTX Connector(CN24) FPGA (Virtex-7) Signal Name Pin Name MGT_BANK Pin No. Pin No.

  • Page 60: Table 8-29 Gtx Connector [Cn24] Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual Table 8-29 shows the GTX connector pin assignments. Table 8-29 GTX Connector [CN24] Pin Assignments CN24 CN24 Pin Name Signal Pin Name Signal B Side A Side +12 V PRSNT1# +12 V +12 V +12 V...
  • Page 61 TB-7V-2000T-LSI Hardware User Manual CN24 CN24 Pin Name Signal Pin Name Signal B Side A Side PETn6 GTX_TX6_N PERp6 GTX_RX6_P PERn6 GTX_RX6_N PETp7 GTX_TX7_P PETn7 GTX_TX7_N PERp7 GTX_RX7_P PRSNT2# PERn7 GTX_RX7_N Rev.1.03...

  • Page 62: Usb3.0

    8.4. USB3.0 The TB-7V-2000T-LSI board is equipped with a Cypress USB Super Speed Peripherals equivalent CYUSB3014 and a SAMTEC USB3.0 TYPE-B connector. In addition, it is also equipped with I2S interface, I2C interface, RS232C interface, RS232C pin header and SPI Flash for firmware storage.

  • Page 63: Table 8-30 Usb3.0 Controller Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual Table 8-30 shows the signal connections between FPGA (Virtex-7) and USB3.0Controller. Table 8-30 USB3.0 Controller Pin Assignments FPGA(Virtex-7) (IC55) Signal Name Pin Name Pin No. Bank RESET# USB_RESET_N AU24 INT# USB_INT_N AU25 USB_I2C_CHARGER_DETECT AJ21 GPIO29 USB_CTL12...

  • Page 64: Usb3.0 Type-B Connector

    The TB-7V-2000T-LSI board is equipped with one SAMTEC USB3.0 TYPE-B connector. Figure 8-6 USB3.0 TYPE-B Connector 8.4.2. I2S Connector The TB-7V-2000T-LSI board is equipped with one I2S interface that is connected to the CYUSB3014. Figure 8-7 I2S Connector Table 8-31 I2S Connector Pin Assignments...

  • Page 65: Spi Connector And Spi Flash Memory

    TB-7V-2000T-LSI Hardware User Manual 8.4.3. SPI Connector and SPI Flash Memory The TB-7V-2000T-LSI board is equipped with one SPI connector that is connected to the CYUSB3014. It is also equipped with one SPI Flash Memory for firmware storage. *Either SPI or RS232C can be used. For more information, refer to the section “IFSELJumper”.

  • Page 66: I2C Interface

    TB-7V-2000T-LSI Hardware User Manual 8.4.4. I2C Interface The TB-7V-2000T-LSI board is equipped with one I2C interface that is connected to the CYUSB3014 and the FPGA (Virtex-7). I2C device addresses E0 through E2 can be defined using SW15. *I2C device is not implemented (only socket is provided).

  • Page 67: Rs232C Connector

    CN_USB_UART_RXD CN17 CN_USB_UART_RTS CN_USB_UART_CTS 8.4.6. IFSEL Jumpers The TB-7V-2000T-LSI board is equipped with four IFSEL jumpers that are used to select either SPI or RS232C interface on the CYUSB3014. Figure 8-13 Onboard IFSEL Jumpers Table 8-36 IFSEL Jumper Settings JP46,JP47,JP48,JP49...

  • Page 68: Usb Jtag Connector

    TB-7V-2000T-LSI Hardware User Manual 8.4.7. USB JTAG Connector The TB-7V-2000T-LSI board is equipped with a CYUSB3014 dedicated JTAG connector. Figure 8-14 Onboard USB JTAG Connector Table 8-37 USB JTAG Connector Pin Assignments CN18 IC55 (CYUSB3014) VCC / GND / N.C.

  • Page 69: Pmode Jumpers

    TB-7V-2000T-LSI Hardware User Manual 8.4.8. PMODE Jumpers The TB-7V-2000T-LSI board is equipped with three PMODE jumpers that are used to select type of PMODE of CYUSB3014. Figure 8-15 Onboard PMODE Jumpers Table 8-39 PMODE Jumper Settings JP53 JP52 JP51 PMODE...

  • Page 70: Clk Jumper

    CLK SEL CLKIN XTAL 8.4.10. OTG_ID The TB-7V-2000T-LSI board is equipped with an OTG ID jumper [JP55] that is used to set CYUSB3014 [IC55] OTG_ID input. Figure 8-17 Onboard OTG ID Jumper [JP55] Table 8-41 OTG ID Jumper [JP55] Settings...

  • Page 71: Reset

    TB-7V-2000T-LSI Hardware User Manual 8.4.11. Reset The TB-7V-2000T-LSI board will allow the user to control the CYUSB3014 [IC55] reset either by Push SW, Jumper or Virtex-7 [IC26]. SW7: Pressing and holding the switch (causing the output to go LOW) will assert the CYUSB3014 [IC55] reset.

  • Page 72: Dvi

    TB-7V-2000T-LSI Hardware User Manual 8.5. The TB-7V-2000T-LSI board is equipped with single mode DVI Tx and DVI Rx. IC47 OCK_INV /STAG JP44 JP43 JP42 JP41 CN14 V7_VCC+3.3V XR2A-0811-N IC43 IC46 DVI_R_DFO DDC_CLK DVI_R_ST DDC_DATA DVI Rx DVI_R_STAG IC26 Connector DVI_R_OCK_INV...

  • Page 73: Dvi_Rx

    TB-7V-2000T-LSI Hardware User Manual 8.5.1. DVI_Rx The TB-7V-2000T-LSI board is equipped with an external input dedicated DVI interface. *For information on how to configure the DVI Receiver and JP41, JP42, JP43 and JP44, refer to the TI’s TFP401PZP Data Sheet. Information on SW5 and SW6 will be described later in this section.

  • Page 74: Dvi_Tx

    V7_DVI_R_QE23 IC45 1.8V V7_DVI_R_CLK V7_DVI_R_CTL1 V7_DVI_R_CTL2 V7_DVI_R_CTL3 V7_DVI_R_DE V7_DVI_R_VS V7_DVI_R_HS V7_DVI_R_SCDT 8.5.2. DVI_Tx The TB-7V-2000T-LSI board is equipped with an external output dedicated DVI interface. DVI Rx I/F DVI Rx I/F IC48 IC49 CN15 DVI_T_DATA[23:0] HPLG DVI_T_DKEN DDC_DATA DDC_CLK DVI_T_BSEL...

  • Page 75: Table 8-43 Dvi Tx Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual Table 8-43 shows the signal connections between TFP410PAP and FPGA (Virtex-7). Table 8-43 DVI Tx Pin Assignments Device FPGA (Virtex-7) Name Signal Name Pin No. Bank Level DVI_T_DATA0 AA37 DVI_T_DATA1 AB39 DVI_T_DATA2 AB35 DVI_T_DATA3 AB42 DVI_T_DATA4...

  • Page 76: Dvi_Rx- Dvi_Tx Connections

    TB-7V-2000T-LSI Hardware User Manual 8.5.3. DVI_Rx- DVI_Tx Connections SW5 and SW6 allow the user to switch the DVI_Rx- DVI_Tx connections. Figure 8-24 shows the SW5/SW6 structure. SW5: DDC switchover SW6: Hot-Plug switchover IC47 CN14 XR2A-0811-N IC46 DDC_CLK DDC_DATA DVI Rx...

  • Page 77: Table 8-44 Dvi_Rx- Dvi_Tx Connections

    TB-7V-2000T-LSI Hardware User Manual Table 8-44 DVI_Rx- DVI_Tx Connections Connecter Device Connect Pin Description Name Destination Name Pin No. EEPROM DDC_CLK (DVI_Tx CN) Pin No.6 CN14 EEPROM DDC_DATA (DVI_Rx CN) (DVI_Tx CN) Pin No.7 OP+5V (DVI_Tx CN) Pin No.16 Rev.1.03...

  • Page 78: Rs232C

    TB-7V-2000T-LSI Hardware User Manual 8.6. RS-232C The TB-7V-2000T-LSI board is equipped with a RS-232C interface for external communication purposes. FPGA connections can be switched using jumpers. IC80 CN35 IC26 IC78 V7_UART_DIN DOUT FPGA D-sub LEVEL V7_UART_ROUT ROUT RS232C Connector TRANSLATOR...

  • Page 79: Figure 8-28 Onboard Fpga Switching Jumpers

    TB-7V-2000T-LSI Hardware User Manual Figure 8-28 Onboard FPGA Switching Jumpers Table 8-46 FPGA(Virtex-7) Switching Jumper Settings JP112 FPGA SEL V7 UART ON V7 UART OFF Table 8-47 FPGA(Kintex-7) Switching Jumper Setting JP114 FPGA SEL K7 UART ON K7 UART OFF *Do not attempt to turn on Virtex-7 UART and Kintex-7 UART simultaneously.

  • Page 80: Pinheader

    TB-7V-2000T-LSI Hardware User Manual 8.7. PinHeader The TB-7V-2000T-LSI board is equipped with two 16-pin pinheaders (of them, 12 pins are used for FPGA signal connections). Figure 8-29 PinHeader Structure Figure 8-30 Onboard PinHeaders Rev.1.03...

  • Page 81: Table 8-48 Pinheader (Cn25) Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual Table 8-48 PinHeader (CN25) Pin Assignments FPGA(Virtex-7) PinHeader CN25 FPGA(Virtex-7) Bank Pin No. Signal Name Pin No. Signal Name Pin No. Bank V7_VCC+1.8V V7_VCC+1.8V AH29 V7_PH1 V7_PH2 AF29 AF30 V7_PH3 V7_PH4 AJ29 AJ30 V7_PH5 V7_PH6 AG31...

  • Page 82: Dipsw

    TB-7V-2000T-LSI Hardware User Manual 8.8. DipSW The TB-7V-2000T-LSI board is equipped with three 8-position DIPSWs for Virtex-7. When the DIPSW is switched on, then there is “low” level on FPGA input. Figure 8-31 Virtex-7 DIPSW Structure Figure 8-32 Onboard DIPSWs...

  • Page 83: Table 8-50 Virtex-7 Dipsw Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual Table 8-50 Virtex-7 DIPSW Pin Assignments Device FPGA(Virtex-7) Name Pin No. Signal Name Pin No. Bank Level V7_DIPSW1 AH32 V7_DIPSW2 AH33 V7_DIPSW3 AJ33 V7_DIPSW4 AL33 1.8V V7_DIPSW5 AM34 V7_DIPSW6 AL34 V7_DIPSW7 AM35 V7_DIPSW8 AL35 9-16 V7_DIPSW9...

  • Page 84: Pushsw

    TB-7V-2000T-LSI Hardware User Manual 8.9. PushSW The TB-7V-2000T-LSI board is equipped with four PushSws for Virtex-7. When the PushSW is pressed down, then there is “low” level on FPGA input. Figure 8-33 Virtex-7 PushSW Sructure Figure 8-34 Onboard PushSWs Table 8-51 Virtex-7 PushSW Pin Assignments...

  • Page 85: Rotary Sw

    TB-7V-2000T-LSI Hardware User Manual 8.10. Rotary SW The TB-7V-2000T-LSI board is equipped with one Rotary SW. Figure 8-35 Rotary SW Structure Figure 8-36 Onboard Rotary SW Table 8-52 Rotary SW Pin Assignments Device (SW4) FPGA (Virtex-7) Pin No. Signal Name Pin No.

  • Page 86: Led

    TB-7V-2000T-LSI Hardware User Manual 8.11. LED The TB-7V-2000T-LSI board is equipped with ten LEDs for Virtex-7. Each LED will light up when the corresponding FPGA output pin is driven “High”. Figure 8-37 Virtex-7 LED Structure Figure 8-38 Onboard LEDs Rev.1.03...

  • Page 87: Table 8-54 Virtex-7 Led Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual Table 8-54 Virtex-7 LED Pin Assignments Device FPGA (Virtex-7) Name Signal Name Pin No. Bank Level LED1 V7_LED1 AH42 LED2 V7_LED2 AH28 LED3 V7_LED3 AG29 LED4 V7_LED4 AG30 LED5 V7_LED5 AG44 1.8V LED6 V7_LED6 AE30 LED7...

  • Page 88: Single Digit Led

    TB-7V-2000T-LSI Hardware User Manual 8.12. Single Digit LED The TB-7V-2000T-LSI board is equipped with two Single digit LEDs. Each Single digit LED will light up when the corresponding FPGA output pin is driven “High”. Figure 8-39 shows the LED64 structure. Similar figure applies to the LED65 structure.

  • Page 89: Table 8-55 Single Digit Led(Led64) Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual Table 8-55 Single Digit LED(LED64) Pin Assignments Device FPGA(Virtex-7) Name Pin No. Signal Name Pin No. Bank Level V7_PEL_LED1_A V7_PEL_LED1_F V7_PEL_LED1_G V7_PEL_LED1_E V7_PEL_LED1_D LED64 1.5V V7_PEL_LED1_DP OP+3.3V V7_PEL_LED1_C OP+3.3V V7_PEL_LED1_B Table 8-56 Single Digit LED(LED65) Pin Assignments...

  • Page 90: Xadc Pin Header

    TB-7V-2000T-LSI Hardware User Manual 8.13. XADC Pin Header The TB-7V-2000T-LSI board is equipped with a 14-pin PinHeader for Virtex7 XADC. If a dedicated differential analog input (VP_0,VN_0) is used, do not implement R283 and R284. If a thermal diode (DXP_0, DXN_0) is used, do not implement R286 and R287.

  • Page 91: Battery Control

    TB-7V-2000T-LSI Hardware User Manual 8.14. Battery Control The TB-7V-2000T-LSI board is equipped with a battery control circuit on the solder side. By default, the battery socket is not implemented. The battery is connected to the Virtex-7 VCCVBATT(AB1) pin. Use a “CR1220” size of button battery.

  • Page 92: Virtex-7 Config Micro Sd/Nand Flash

    TB-7V-2000T-LSI Hardware User Manual 8.15. Virtex-7 Config Micro SD/NAND Flash The TB-7V-2000T-LSI board is equipped with one NAND Flash for Virtex-7 configuration file storage and one Micro SD socket that allow configuration from Micro SD Card and NAND Flash. It is also equipped with Spartan-3AN for configuration control.

  • Page 93: Kintex-7 Interfae

    9.1. QTH Connector The TB-7V-2000T-LSI board is equipped with five SAMTEC 120-pin QTH connectors that allow high speed data connection to external devices. Each connector provides up to 56 pairs of LVDS signal connections, including 8 pairs of clock signals (or 119 single-pin connections).

  • Page 94: Figure 9-2 Bank Voltage Setting Location On Fpga (Kintex-7)

    TB-7V-2000T-LSI Hardware User Manual Table 9-1 Voltage Selection for Kintex-7 Banks and Peripheral Devices Voltage Selection Bank Connected Device Voltage JP No. 1.8V 2.5V 3.3V FMC_HPC(CN34) JP94 Variable HR13/14/15 QTH4(CN31) (1.8V/2.5V/3.3V) JP102 QSPI,DSW, UART FMC_HPC(CN34) Variable HR16/17/18 QTH5(CN32) JP95 (1.8V/2.5V/3.3V) LED,PSW Be sure to set JP94 and JP102 to the same pin settings.

  • Page 95: Qth4 Power Supply Pins

    TB-7V-2000T-LSI Hardware User Manual 9.1.1. QTH4 Power Supply Pins H1 Pin OP+3.3V power supply (currently not available due to non-implementation of R848). H2 Pin OP+3.3V power supply (currently not available due to non-implementation of R849). B54 Pin Any 5V, 12V or FPGA (Kintex-7) is selectable by setting the jumper as shown in Table 9-2.

  • Page 96: Table 9-6 Qth4 B58 Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual B58 Pin Either TRAD or FPGA (Kintex-7) is selectable by setting the jumper as shown in Table 9-6. Currently the FPGA (Kintex-7) connection is not available due to non-implementation of R1057). Table 9-6 QTH4 B58 Pin Assignments...

  • Page 97: Table 9-9 Qth4 Connector (Cn31) Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual Table 9-9 QTH4 Connector (CN31) Pin Assignments FPGA (Kintex-7) QTH4 (CN31) FPGA (Kintex-7) Signal Name Signal Name Bank Pin# Pin Name Pair Pin# Pin# Pair Pin Name Pin# Bank AC27 IO_L12N_T1_MRCC_13 S4_LVDS_CLK0_N S4_LVDS0_N IO_L1N_T0_13 AA26 AB27 IO_L12P_T1_MRCC_13 S4_LVDS_CLK0_P...
  • Page 98 TB-7V-2000T-LSI Hardware User Manual FPGA (Kintex-7) QTH4 (CN31) FPGA (Kintex-7) Signal Name Signal Name Bank Pin# Pin Name Pair Pin# Pin# Pair Pin Name Pin# Bank IO_L1N_T0_AD0N_15 S4_LVDS23_N B25 A25 N S4_LVDS24_N/VREF IO_L6N_T0_VREF_15 IO_L1P_T0_AD0P_15 S4_LVDS23_P B26 A26 P S4_LVDS24_P IO_L6P_T0_15...
  • Page 99 TB-7V-2000T-LSI Hardware User Manual FPGA (Kintex-7) QTH4 (CN31) FPGA (Kintex-7) Signal Name Signal Name Bank Pin# Pin Name Pair Pin# Pin# Pair Pin Name Pin# Bank IO_L22N_T3_A16_15 S4_LVDS43_N B45 A45 N S4_LVDS44_N IO_L23N_T3_FWE_B_15 IO_L22P_T3_A17_15 S4_LVDS43_P B46 A46 P S4_LVDS44_P IO_L23P_T3_FOE_B_15...

  • Page 100: Switchover Of Desctination (Kintex-7/Cn33) To Which The Qth4 Connector Is Connected

    TB-7V-2000T-LSI Hardware User Manual 9.1.2. Switchover of desctination (Kintex-7/CN33) to which the QTH4 connector is connected The IIC signal destination of the QTH connector can be switched using SW20 and SW21. Figure 9-3 Structure of switchover of destination (Kintex-7/IIC) to which the QTH4 connector...

  • Page 101: Table 9-11 Iic Pullup On/Off Switchover

    TB-7V-2000T-LSI Hardware User Manual The IIC Pullup ON/OFF switchover can be controlled using SW24 and SW25. The 1.8V/2.5V/3.3V Pullup selection is also allowed. Table 9-11 IIC Pullup On/OFF Switchover Connecter Name Device Name Action Pullup OFF SW24 CN33 SW25 3.3V Pullup ON In addition, the above 3.3V Pullup mode can be switched to 1.8V or 2.5V Pullup mode.

  • Page 102: Qth5 Power Supply Pinout

    TB-7V-2000T-LSI Hardware User Manual 9.1.3. QTH5 Power Supply Pinout H1 Pin OP+3.3V power supply (currently not available due to non-implementation of R858). H2 Pin OP+3.3V power supply (currently not available due to non-implementation of R859). B54 Pin Any 5V, 12V or FPGA (Kintex-7) is selectable by setting the jumper as shown in Table 9-12.

  • Page 103: Table 9-16 Qth5 B5 Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual B58 Pin Either TRAD or FPGA (Kintex-7) is selectable by setting the jumper as shown in Table 9-16. Currently the FPGA (Kintex-7) connection is not available due to non-implementation of R1063). Table 9-16 QTH5 B5 Pin Assignments...

  • Page 104: Table 9-19 Qth5 Connector (Cn32) Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual Table 9-19 QTH5 Connector (CN32) Pin Assignments FPGA (Kintex-7) QTH5 (CN32) FPGA (Kintex-7) Signal Name Signal Name Bank Pin# Pin Name Pair Pin# Pin# Pair Pin Name Pin# Bank IO_L12N_T1_MRCC_17 S5_LVDS_CLK0_N S5_LVDS0_N IO_L1N_T0_17 IO_L12P_T1_MRCC_17 S5_LVDS_CLK0_P S5_LVDS0_P...
  • Page 105 TB-7V-2000T-LSI Hardware User Manual FPGA (Kintex-7) QTH5 (CN32) FPGA (Kintex-7) Signal Name Signal Name Bank Pin# Pin Name Pair Pin# Pin# Pair Pin Name Pin# Bank IO_L1N_T0_18 S5_LVDS23_N S5_LVDS24_N/VREF IO_L6N_T0_VREF_18 IO_L1P_T0_18 S5_LVDS23_P S5_LVDS24_P IO_L6P_T0_18 IO_L2N_T0_18 S5_LVDS25_N S5_LVDS26_N/C_M_SDA IO_L3N_T0_DQS_18 IO_L2P_T0_18 S5_LVDS25_P...
  • Page 106 TB-7V-2000T-LSI Hardware User Manual FPGA (Kintex-7) QTH5 (CN32) FPGA (Kintex-7) Signal Name Signal Name Bank Pin# Pin Name Pair Pin# Pin# Pair Pin Name Pin# Bank D28 IO_L14N_T2_SRCC_16 S5_LVDS47_N/CLK_N N S5_LVDS48_N IO_L15N_T2_DQS_16 IO_L14P_T2_SRCC_16 S5_LVDS47_P/CLK_P P S5_LVDS48_P IO_L15P_T2_DQS_16 C30 IO_L16N_T2_16 S5_LVDS49_N...

  • Page 107: Switchover Of Desctination (Kintex-7/Iic) To Which The Qth5 Connector Is Connected

    TB-7V-2000T-LSI Hardware User Manual 9.1.4. Switchover of desctination (Kintex-7/IIC) to which the QTH5 connector is connected The connection destination of the QTH5 connector can be switched using SW22 and SW23. Figure 9-4 Structure of switchover of destination (Kintex-7/IIC) to which the QTH5 connector...

  • Page 108: Table 9-21 Iic Pullup On/Off Switchover

    TB-7V-2000T-LSI Hardware User Manual The IIC Pullup ON/OFF switchover can be controlled using SW24 and SW25. The 1.8V/2.5V/3.3V Pullup selection is also allowed. Table 9-21 IIC Pullup On/Off Switchover Connecter Name Device Name Action Pullup OFF SW24 CN33 SW25 3.3V Pullup ON In addition, the above 3.3V Pullup mode can be switched to 1.8V or 2.5V Pullup mode.

  • Page 109: Fmc Connector

    TB-7V-2000T-LSI Hardware User Manual 9.2. FMC Connector The TB-7V-2000T-LSI board is equipped with one SAMTEC’s FMC Connector that is connected to the Kintex-7. Figure 9-5 shows the High-Pin Count Pin Assignments. High-Pin Count: One (CN34) Note that all HPC and LPC pins are not connected to the FPGA.

  • Page 110: Hpc Connector (High-Pin Count)

    TB-7V-2000T-LSI Hardware User Manual 9.2.1. HPC Connector (High-Pin Count) The following shows the HPC interface requirements. High Speed: TX 10ch + RX 10ch + 2 Clock Sources (4 pins) Low Speed: LA: 5-Pair (10 pins) + 1 Clock Source (2 pins) The subsequent pages list the HPC connector pin assignments with FPGA.

  • Page 111: Table 9-22 Hpc Connector (Cn34) Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual Table 9-22 HPC Connector (CN34) Pin Assignments Bank Pin# Pin# Bank RES1 MGTXRXP1_115 DP1_M2C_P MGTXRXN1_115 DP1_M2C_N DP9_M2C_P MGTXRXP1_117 DP9_M2C_N MGTXRXN1_117 MGTXRXP2_115 DP2_M2C_P MGTXRXN2_115 DP2_M2C_N DP8_M2C_P MGTXRXP0_117 DP8_M2C_N MGTXRXN0_117 MGTXRXP3_115 DP3_M2C_P MGTXRXN3_115 DP3_M2C_N DP7_M2C_P MGTXRXP3_116 DP7_M2C_N MGTXRXN3_116...
  • Page 112 TB-7V-2000T-LSI Hardware User Manual Bank Pin# Pin# Bank *5 PG_C2M MGTXTXP0_115 DP0_C2M_P MGTXTXN0_115 DP0_C2M_N *1GBTCLK1_M2C_P MGTXRXP0_115 DP0_M2C_P ***1GBTCLK1_M2C_N MGTXRXN0_115 DP0_M2C_N LA01_P_CC LA01_N_CC LA06_P LA06_N LA05_P LA05_N LA10_P LA09_P LA10_N LA09_N LA13_P LA14_P LA13_N LA14_N LA17_P_CC LA17_N_CC LA18_P_CC LA18_N_CC LA23_P LA23_N...
  • Page 113 TB-7V-2000T-LSI Hardware User Manual Bank Pin# Pin# Bank *5 PG M2C HA01_P_CC HA01_N_CC HA00_P_CC HA00_N_CC HA05_P HA05_N HA04_P HA04_N HA09_P HA09_N HA08_P HA08_N HA13_P HA13_N HA12_P HA12_N HA16_P HA16_N HA15_P HA15_N HA20_P HA20_N HA19_P HA19_N HB03_P HB03_N HB02_P HB02_N HB05_P...
  • Page 114 TB-7V-2000T-LSI Hardware User Manual Bank Pin# Pin# Bank *7 VREF_A_M2C CLK1_M2C_P *5 PRSNT_M2C_L CLK1_M2C_N CLK0_M2C_P CLK0_M2C_N LA00_P_CC LA00_N_CC LA02_P LA02_N LA03_P LA03_N LA04_P LA04_N LA08_P LA08_N LA07_P LA07_N LA12_P LA12_N LA11_P LA11_N LA16_P LA16_N LA15_P LA15_N LA20_P LA20_N LA19_P LA19_N...
  • Page 115 TB-7V-2000T-LSI Hardware User Manual Bank Pin# Pin# Bank *7 VREF_B_M2C CLK3_M2C_P CLK3_M2C_N CLK2_M2C_P CLK2_M2C_N HA03_P HA03_N HA02_P HA02_N HA07_P HA07_N HA06_P HA06_N HA11_P HA11_N HA10_P HA10_N HA14_P HA14_N HA17_P_CC HA17_N_CC HA18_P HA18_N HA21_P HA21_N HA22_P HA22_N HA23_P HA23_N HB01_P HB01_N...

  • Page 116: Figure 9-7 Sda,Scl,Ga1/0 Tdi/Tdo Circuit Structure

    TB-7V-2000T-LSI Hardware User Manual *2 SCL,SDA The TB-7V-2000T-LSI board is equipped with test points and a pullup function to realize I2C communications with FMC mezzanine Card. By default, the pullup resistor is not implemented. Figure 9-7 SDA,SCL,GA1/0 TDI/TDO Circuit Structure *3 GA[1:0] This circuit is provided for notification of ID data to the FMC mezzanine card.
  • Page 117 The TB-7V-2000T-LSI board is equipped with a TPAD73 test pad to monitor the “VREF_A_M2C” on H1-pin and a TRAD74 test pad to monitor “VREF_B_M2C” on K1-pin. *8 VIO_B_M2C The TB-7V-2000T-LSI board is equipped with a TP51 test pad to monitor “VIO_B_M2C” on J39 and K40 pins. Rev.1.03...

  • Page 118: Rs232C

    TB-7V-2000T-LSI Hardware User Manual 9.3. RS-232C The TB-7V-2000T-LSI board is equipped with a RS-232C interface that allows the connection to an external device. The FPGA connection is enabled through the use of onboard jumpers. IC80 CN35 IC26 IC78 V7_UART_DIN DOUT...

  • Page 119: Figure 9-11 Onboard Fpga Connectivity Jumpers

    TB-7V-2000T-LSI Hardware User Manual Figure 9-11 Onboard FPGA Connectivity Jumpers Table 9-25 FPGA (Virtex-7) Connectdivity Jumper Settings JP112 FPGA SEL V7 UART ON V7 UART OFF Table 9-26 FPGA (Kintex-7) Connectivity Jumper Settings JP114 FPGA SEL K7 UART ON K7 UART OFF *Do not turn on the UART on Virtex-7 and the UART on Kintex-7 simultaneously.

  • Page 120: Dipsw

    TB-7V-2000T-LSI Hardware User Manual 9.4. DipSW The TB-7V-2000T-LSI board is equipped with one 8-position DIPSW for Kintex-7. When the DIPSW is switched on, then there is “low” level on FPGA input. Figure 9-12 Onboad Kintex-7 dedicated DIPSW Table 9-27 Kintex-7 Dedicted DIPSW Pin Assignments...

  • Page 121: Pushsw

    TB-7V-2000T-LSI Hardware User Manual 9.5. PushSW The boad is equipped with four Kintex-7 dedicated PushSW. When the PushSW is pressed down, then there is “low” level on FPGA input. Figure 9-13 Kintex-7 Dedicated PushSW Structure Figure 9-14 Onboard PushSWs Table 9-28 Kintex-7 Dedicated PushSW Pin Assignments...

  • Page 122: Led

    TB-7V-2000T-LSI Hardware User Manual 9.6. The TB-7V-2000T-LSI board is equipped with six Kintex-7 dedicated LEDs. Each LED will light up when the corresponding FPGA output pin is driven “High”. Figure 9-15 Kintex-7 Dedicated LED Structure Figure 9-16 Onboard Kintex-7 Dedicated LEDs...

  • Page 123: Xadc Dedicated Pin Header

    9.7. XADC Dedicated Pin Header The TB-7V-2000T-LSI board is equipped with a Kintex-7 XADC dedicated 14-pin PinHeader. In the case of using a dedicated differential analog input (VP_0,VN_0), do not implement R819 and R820. While, in the case of using a thermal diode (DXP_0, DXN_0), do not implement R821 and R822.

  • Page 124: Table 9-30 Kintex-7 Xadc Dedicated Pinheader Pin Assignments

    TB-7V-2000T-LSI Hardware User Manual Table 9-30 Kintex-7 XADC Dedicated PinHeader Pin Assignments FPGA PinHeader(CN28) Bank No. Pin No. Signal Name Pin No. Signal Name K7_XADC_AGND K7_XADC_AGND K7_XADC_AGND K7_XADC_AGND VCCADC K7_XADC_AGND Power supply VREFP K7_XADC_AGND Power supply K7_XADC_AGND Rev.1.03...

  • Page 125: Battery Control

    TB-7V-2000T-LSI Hardware User Manual 9.8. Battery Control The TB-7V-2000T-LSI board is equipped with a battery control circuit on the solder side. By default, the battery socket is not implemented. The battery is connected to the Kintex-7 VCCVBATT (C10) pin. Use a “CR1220” size of button battery.

  • Page 126: Quad Spi Flash

    TB-7V-2000T-LSI Hardware User Manual 9.9. Quad SPI Flash The TB-7V-2000T-LSI board is equipped with a 128-Mbyte QSPI flash memory for Kintex-7 configuration that is connected to the FPGA via a level shiftor. For information about configurationmethod, refer to Section 11.

  • Page 127: Virtex-7 And Kintex-7 Interconnection

    TB-7V-2000T-LSI Hardware User Manual Virtex-7 and Kintex-7 Interconnection Virtex-7 [IC26] and Kintex-7 [IC72] are interconnected on the board using 4 Banks. The interface is 1.8V. Note that Bank12 (HR) on Kintex-7 [IC72] does not support differential signals. So, only 3 Banks are used for the differential signal interface.

  • Page 128: Table 10-1 Pin Assignments For Fpga Interconnection ([Ic26] Bank19 - [Ic72] Bank12)

    TB-7V-2000T-LSI Hardware User Manual Table 10-1 shows the pin assignments for Virtex-7 [IC26] and Kintex-7 [IC72] interconnection. Table 10-1 Pin Assignments for FPGA Interconnection ([IC26] Bank19 - [IC72] Bank12) Virtex-7 [IC26] Kintex-7 [IC72] Signal Name Bank Pin No. Pin No.
  • Page 129 TB-7V-2000T-LSI Hardware User Manual Virtex-7 [IC26] Kintex-7 [IC72] Signal Name Bank Pin No. Pin No. Bank FPGA_SRCC0_P AG24 FPGA_SRCC0_N AH24 FPGA_SRCC1_P AE23 FPGA_SRCC1_N AF23 FPGA_MRCC0_P AF22 FPGA_MRCC0_N AG23 FPGA_MRCC1_P AD23 FPGA_MRCC1_N AE24 FPGA_D0_S FPGA_D1_S AE20 Rev.1.03...

  • Page 130: Table 10-2 Pin Assignments For Fpga Interconnection ([Ic26] Bank20 - [Ic72] Bank32)

    TB-7V-2000T-LSI Hardware User Manual Table 10-2 Pin Assignments for FPGA Interconnection ([IC26] Bank20 - [IC72] Bank32) Virtex-7 [IC26] Kintex-7 [IC72] Signal Name Bank Pin No. Pin No. Bank FPGA_D20_P AG15 FPGA_D20_N AH15 FPGA_D21_P AE16 FPGA_D21_N AF16 FPGA_D22_P AJ19 FPGA_D22_N AK19...
  • Page 131 TB-7V-2000T-LSI Hardware User Manual Virtex-7 [IC26] Kintex-7 [IC72] Signal Name Bank Pin No. Pin No. Bank FPGA_SRCC2_P AD17 FPGA_SRCC2_N AD16 FPGA_SRCC3_P AF18 FPGA_SRCC3_N AG18 FPGA_MRCC2_P AF17 FPGA_MRCC2_N AG17 FPGA_MRCC3_P AD18 FPGA_MRCC3_N AE18 FPGA_D2_S FPGA_D3_S AB14 Rev.1.03...

  • Page 132: Table 10-3 Pin Assignments For Fpga Interconnection ([Ic26] Bank39 - [Ic72] Bank33)

    TB-7V-2000T-LSI Hardware User Manual Table 10-3 Pin Assignments for FPGA Interconnection ([IC26] Bank39 - [IC72] Bank33) Virtex-7 [IC26] Kintex-7 [IC72] Signal Name Bank Pin No. Pin No. Bank FPGA_D40_P AK14 FPGA_D40_N AK13 FPGA_D41_P AC12 FPGA_D41_N AC11 FPGA_D42_P AJ13 FPGA_D42_N AJ12...
  • Page 133 TB-7V-2000T-LSI Hardware User Manual Virtex-7 [IC26] Kintex-7 [IC72] Signal Name Bank Pin No. Pin No. Bank FPGA_SRCC4_P AE10 FPGA_SRCC4_N AF10 FPGA_SRCC5_P AE11 FPGA_SRCC5_N AF11 FPGA_MRCC4_P AG10 FPGA_MRCC4_N AH10 FPGA_MRCC5_P AD12 FPGA_MRCC5_N AD11 FPGA_D4_S FPGA_D5_S AD13 Rev.1.03...

  • Page 134: Table 10-4 Pin Assignments For Fpga Interconnection ([Ic26] Bank40-[Ic72] Bank34)

    TB-7V-2000T-LSI Hardware User Manual Table 10-4 Pin Assignments for FPGA Interconnection ([IC26] Bank40-[IC72] Bank34) Virtex-7 [IC26] Kintex-7 [IC72] Signal Name Bank Pin No. Pin No. Bank FPGA_D60_P FPGA_D60_N FPGA_D61_P FPGA_D61_N FPGA_D62_P FPGA_D62_N FPGA_D63_P FPGA_D63_N FPGA_D64_P FPGA_D64_N FPGA_D65_P FPGA_D65_N FPGA_D66_P FPGA_D66_N...
  • Page 135 TB-7V-2000T-LSI Hardware User Manual Virtex-7 [IC26] Kintex-7 [IC72] Signal Name Bank Pin No. Pin No. Bank FPGA_SRCC6_P FPGA_SRCC6_N FPGA_SRCC7_P FPGA_SRCC7_N FPGA_MRCC6_P FPGA_MRCC6_N FPGA_MRCC7_P FPGA_MRCC7_N FPGA_D6_S FPGA_D7_S Rev.1.03...

  • Page 136: Generating A Kintex-7 Configuration File

    TB-7V-2000T-LSI Hardware User Manual Generating a Kintex-7 Configuration File 11.1. How to Generate a Configuration File (bit file) The following operations are described assuming that the user uses tool version “ISE14.2”. Similar setting procedure will be applied to 14.2 or later version.

  • Page 137: Required Configuration Time

    TB-7V-2000T-LSI Hardware User Manual 11.2. Required Configuration Time As for configuration using a Flash Memory, configuration time can be changed by selecting a desired configuration clock on ISE Tool. Figure 11-3 Changing Configuration Time Estimated configuration time: Configuration Rate = 3MHz: Configuration Time = approx.10 seconds Configuration Rate = 16MHz: Configuration Time = approx.

  • Page 138: How To Generate A Configuration File (Mcs File)

    TB-7V-2000T-LSI Hardware User Manual 11.4. How to Generate a Configuration File (mcs file) The following describes how to create a configuration file. Generate a configuration file that is loaded to the Flash Memory in accordance with the following procedure. 1. Double click Generate Target PROM/ACE File.

  • Page 139: Figure 11-7 Impact Window - 1

    TB-7V-2000T-LSI Hardware User Manual 3. When iMPACT is started, double click Create PROM File. Figure 11-7 iMPACT Window - 1 4. Select SPI Flash－Configure Single FPGA and click an “Arrow”. Figure 11-8 iMPACT Window - 2 Rev.1.03...

  • Page 140: Figure 11-9 Impact Window - 3

    TB-7V-2000T-LSI Hardware User Manual 5. Select 128M in the Storage Device(bits) field and click Add Storage Device. Figure 11-9 iMPACT Window - 3 6. After clicking an Arrow, enter your desired name (directory) in the Output File Name and the Output File Location field and click OK.

  • Page 141: Figure 11-11 Impact Window - 5

    TB-7V-2000T-LSI Hardware User Manual 7. Click OK. Figure 11-11 iMPACT Window - 5 8. Choose a bit file to generate a configuration file. Figure 11-12 iMPACT Window - 6 9. Click No. Figure 11-13 iMPACT Window - 7 10. Click OK.

  • Page 142: Figure 11-15 Impact Window - 9

    TB-7V-2000T-LSI Hardware User Manual 11. Doule click Generate File. Figure 11-15 iMPACT Window - 9 12. When the configuration file is generated successfully, a Generate Succeeded message will appear. Figure 11-16 iMPACT Window – 10 Rev.1.03...

  • Page 143: Loading A Configuration File To Flash Memory

    TB-7V-2000T-LSI Hardware User Manual 11.5. Loading a Configuration File to Flash Memory As shown in Figure 11-17, connect a Platform USB cable to the JTAG connector (CN27). Turn on the power switch of the board to run iMPACT and load a configuration file to the Flash memory.

  • Page 144: Figure 11-19 Loading A Configuration File To Device (2)

    TB-7V-2000T-LSI Hardware User Manual 2. A bit/jed file configuration window will appear. Cancel it. Select FPGA and then right click to select Add SPI/BPI Flash…. Figure 11-19 Loading a Configuration File to Device (2) 3. Choose a configuration file (xxx.mcs) you want to load to Flash Memory.

  • Page 145: Figure 11-21 Loading A Configuration File To Device (4)

    TB-7V-2000T-LSI Hardware User Manual 4. Select the onboard Flash of N25Q128 1.8/3.3V, set Data Width to 4, and click OK. Figure 11-21 Loading a Configuration File to Device (4) 5. Double click Program on the iMPACT Processes window. Figure 11-22 Loading a Configuration File to Device (5)

  • Page 146: Figure 11-23 Loading A Configuration File To Device (6)

    TB-7V-2000T-LSI Hardware User Manual 6. Click OK. Figure 11-23 Loading a Configuration File to Device (6) 7. A load operation to Flash Memory will start. Figure 11-24 Loading a Configuration File to Device (7) Rev.1.03...

  • Page 147: Figure 11-25 Loading A Configuration File To Device (8)

    TB-7V-2000T-LSI Hardware User Manual 8. When the load operation is completed successfully, a Program Succeeded message will appear. Figure 11-25 Loading a Configuration File to Device (8) 9. With the data loaded to Flash Memory, FPGA is configured using a QSPI.

  • Page 148: Qth-Fmc Conversion Board

    TB-7V-2000T-LSI Hardware User Manual QTH-FMC Conversion Board The TB-7V-2000T-LSI board comes with a QTH-FMC conversion board that is used to connect the FMC Card to the QTH Connector. This conversion board allows the FMC Card to be connected to the TB-7V-2000T-LSI board.

  • Page 149: Power Supply To Fmc Card

    TB-7V-2000T-LSI Hardware User Manual Figure 12-2 An Example of QTH-FMC Connection 12.1. Power Supply to FMC Card For supplying power to the FMC Card, it is needed to set the jumpers on TB-7V-2000T-LSI in accordance with the following procedure. 12.1.1. 12V Power Supply It is needed to supply +12V to the C35 and C37 pins on the FMC connector.

  • Page 150: Power Supply

    12.1.2. 3.3V Power Supply 3.3V required by the FMC connector is generated on the conversion board using 5V that is supplied from the TB-7V-2000T-LSI board and supplied to each C39, D32, D36, D38 and D40 pin on the FMC connector.

  • Page 151: Vadj Power Supply

    12.1.3. VADJ Power Supply Power supply to VADJ on the FMC Card is 3.3V/2.5V/1.8V selectable. Tables 12-5 through 12-9 show the jumper settings on the TB-7V-2000T-LSI board and the QTH-FMC conversion board. Table 12-5 JP Settings in Case of Using QTH1 (CN20) Board VADJ=3.3V...

  • Page 152: How To Attach Spacers

    Figure 12-3 illustrates how to attach the spacers for the QTH-FMC conversion board and the FMC Card. FMC Card Spacer QTH-FMC Board FMC Card 27mm Spacer 19mm Spacer 8.5mm Spacer Figure 12-3 How to Attach Spacers Use the accompanying long screws (10-mm type) to fix the TB-7V-2000T-LSI board and the QTH-FMC board with these spacers. Rev.1.03...

  • Page 153: Default Switch Settings

    TB-7V-2000T-LSI Hardware User Manual Default Switch Settings Figure 13-1 illustrates the default switch settings indicated by blue box. JP62 JP56 JP61,60,59,58,57 SW15 JP39 JP55 JP50 JP103 JP40 JP79,54,51,52,53 JP49,48,47,46 SW26 JP102,94 JP92 JP63 JP64 JP93 JP95 JP69,68,67,66,65 JP116 SW8,9,10 JP113...
  • Page 154 TB-7V-2000T-LSI Hardware User Manual Silk No. Initial Setting Function SW22,23 2-3, 5-6 QTH5 Connector FPGA/IIC Switching (FPGA / IIC) SW24,25 2-1, 5-4 IIC Power Supply Switching (3.3V / non-supply) SW26 ALL OFF Virtex-7 MGT Reference Clock Select Switch SW27 ALL OFF...
  • Page 155 TB-7V-2000T-LSI Hardware User Manual Silk No. Initial Setting Function JP79 USB RESET (non-supply / GND) Kintex-7 VCCADC Setting JP92 (K7_VCC+1.8V / CN28 9pin / non-supply) Kintex-7 VREFP Setting JP93 (K7_XADC_AGND / CN28 11pin / non-supply) Kintex-7 QTH4 VCCO Setting JP94,102 (K7_VCC+1.8V / K7_VCC+2.5V / K7_VCC+3.3V)
  • Page 156 TB-7V-2000T-LSI Hardware User Manual PLD Solution Dept. PLD Division URL: http://solutions.inrevium.com/ E-mail: psd-support@teldevice.co.jp HEAD Quarter: Yokohama East Square, 1-4 Kinko-cho, Kanagawa-ku, Yokohama City, Kanagawa, Japan 221-0056 TEL: +81-45-443-4016 FAX: +81-45-443-4058 Rev.1.03...

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