Philips LPC213 Series User Manual page 262

Philips Semiconductors
Volume 1
24.5 Figures
Fig 1. LPC2131/2/4/6/8 block diagram. . . . . . . . . . . . . . .7
Fig 2. System memory map. . . . . . . . . . . . . . . . . . . . . . .8
Fig 3. Peripheral memory map. . . . . . . . . . . . . . . . . . . . .9
Fig 4. AHB peripheral map . . . . . . . . . . . . . . . . . . . . . .10
Fig 5. VPB peripheral map. . . . . . . . . . . . . . . . . . . . . . .11
Fig 6. Map of lower memory is showing re-mapped and
re-mappable areas (LPC2138 with 512 kB
Flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Fig 7. Oscillator modes and models: a) slave mode of
operation, b) oscillation mode of operation, c)
external crystal model used for C
Fig 8. F selection algorithm . . . . . . . . . . . . . . . . . . .19
OSC
Fig 9. External interrupt logic . . . . . . . . . . . . . . . . . . . . .25
Fig 10. PLL block diagram . . . . . . . . . . . . . . . . . . . . . . . .28
Fig 11. Reset block diagram including the wakeup timer .37
Fig 12. VPB divider connections . . . . . . . . . . . . . . . . . . .39
Fig 13. Simplified block diagram of the Memory Accelerator
Module (MAM) . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Fig 14. Block diagram of the Vectored Interrupt Controller
(VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Fig 15. LPC2131 64-pin package . . . . . . . . . . . . . . . . . .64
Fig 16. LPC2132 64-pin package . . . . . . . . . . . . . . . . . .65
Fig 17. LPC2134/6/8 64-pin package . . . . . . . . . . . . . . .66
Fig 18. LPC2131/2/4/6/8 UART0 block diagram . . . . . . .94
Fig 19. LPC2131/2/4/6/8 UART1 block diagram . . . . . .108
2
Fig 20. I C-bus Configuration. . . . . . . . . . . . . . . . . . . . .110
Fig 21. Format in the Master Transmitter mode . . . . . . .111
Fig 22. Format of Master Receive mode . . . . . . . . . . . .112
Fig 23. A Master Receiver switches to Master Transmitter
after sending Repeated START . . . . . . . . . . . . .112
Fig 24. Format of Slave Receiver mode. . . . . . . . . . . . .113
Fig 25. Format of Slave Transmitter mode . . . . . . . . . . .113
2
Fig 26. I C serial interface block diagram . . . . . . . . . . .115
Fig 27. Arbitration procedure . . . . . . . . . . . . . . . . . . . . .116
Fig 28. Serial clock synchronization. . . . . . . . . . . . . . . .117
Fig 29. Format and States in the Master Transmitter
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Fig 30. Format and States in the Master Receiver
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Fig 31. Format and States in the Slave Receiver mode.128
Fig 32. Format and States in the Slave Transmitter
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Fig 33. Simultaneous repeated START conditions from two
masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Fig 34. Forced access to a busy I
Fig 35. Recovering from a bus obstruction caused by a low
level on SDA . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Fig 36. SPI data transfer format
User manual
/ evaluation18
X1 X2
2
C-bus . . . . . . . . . . . .138
Rev. 01 — 24 June 2005
Chapter 24: Supplementary information
(CPHA = 0 and CPHA = 1) . . . . . . . . . . . . . . . . 148
Fig 37. SPI block diagram . . . . . . . . . . . . . . . . . . . . . . . 155
Fig 38. Texas Instruments synchronous serial frame format:
a) single and b) continuous/back-to-back two frames
transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Fig 39. SPI frame format with CPOL=0 and CPHA=0 (a)
single and b) continuous transfer) . . . . . . . . . . . 159
Fig 40. SPI frame format with CPOL=0 and CPHA=1. . 160
Fig 41. SPI frame format with CPOL = 1 and CPHA = 0 (a)
single and b) continuous transfer) . . . . . . . . . . . 161
Fig 42. SPI frame format with CPOL = 1 and CPHA = 1162
Fig 43. Microwire frame format (single transfer) . . . . . . 163
Fig 44. Microwire frame format (continuos transfers) . . 164
Fig 45. Microwire frame format (continuos transfers) . . 164
Fig 46. A timer cycle in which PR=2, MRx=6, and both
interrupt and reset on match are enabled . . . . . 179
Fig 47. A timer cycle in which PR=2, MRx=6, and both
interrupt and stop on match are enabled . . . . . 179
Fig 48. Timer block diagram . . . . . . . . . . . . . . . . . . . . . 180
Fig 49. PWM block diagram . . . . . . . . . . . . . . . . . . . . . 183
Fig 50. Sample PWM waveforms . . . . . . . . . . . . . . . . . 184
Fig 51. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . 200
Fig 52. RTC prescaler block diagram . . . . . . . . . . . . . . 209
Fig 53. RTC 32kHz crystal oscillator circuit. . . . . . . . . . 211
Fig 54. Watchdog block diagram . . . . . . . . . . . . . . . . . . 215
Fig 55. Map of lower memory after reset . . . . . . . . . . . 217
Fig 56. Boot process flowchart . . . . . . . . . . . . . . . . . . . 220
Fig 57. IAP Parameter passing . . . . . . . . . . . . . . . . . . . 232
Fig 58. EmbeddedICE debug environment block
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Fig 59. ETM debug environment block diagram . . . . . . 243
Fig 60. RealMonitor components . . . . . . . . . . . . . . . . . 245
Fig 61. RealMonitor as a state machine . . . . . . . . . . . . 246
Fig 62. Exception handlers . . . . . . . . . . . . . . . . . . . . . . 249
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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