Table of Contents
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Philips Semiconductors
Volume 1
Interrupt Controller (VIC) . . . . . . . . . . . . . . . . .57
Table 56: Pin description . . . . . . . . . . . . . . . . . . . . . . . . .67
Table 57: Pin connect block register map. . . . . . . . . . . . .73
Table 58: Pin function Select register 0 (PINSEL0 - address
0xE002 C000) bit description . . . . . . . . . . . . .74
Table 59: Pin function Select register 1 (PINSEL1 - address
0xE002 C004) bit description . . . . . . . . . . . . .76
Table 60: Pin function Select register 2 (PINSEL2 -
0xE002 C014) bit description . . . . . . . . . . . . .78
Table 61: Pin function select register bits . . . . . . . . . . . . .78
Table 62: GPIO pin description . . . . . . . . . . . . . . . . . . . .79
Table 63: GPIO register map . . . . . . . . . . . . . . . . . . . . . .79
Table 64: GPIO Pin Value register 0 (IO0PIN - address
0xE002 8000) bit description . . . . . . . . . . . . . .80
Table 65: GPIO Pin Value register 1 (IO1PIN - address
0xE002 8010) bit description . . . . . . . . . . . . . .80
Table 66: GPIO Output Set register 0 (IO0SET - address
0xE002 8004 bit description . . . . . . . . . . . . . . .81
Table 67: GPIO Output Set register 1 (IO1SET - address
0xE002 8014) bit description . . . . . . . . . . . . . .81
Table 68: GPIO Output Clear register 0 (IO0CLR - address
0xE002 800C) bit description . . . . . . . . . . . . . .81
Table 69: GPIO Output Clear register 1 (IO1CLR - address
0xE002 801C) bit description . . . . . . . . . . . . . .81
Table 70: GPIO Direction Register 0 (IO0DIR - address
0xE002 8008) bit description . . . . . . . . . . . . . .82
Table 71: GPIO Direction Register 1 (IO1DIR - address
0xE002 8018) bit description . . . . . . . . . . . . . .82
Table 72: UART0 pin description . . . . . . . . . . . . . . . . . . .84
Table 73: UART0 register map . . . . . . . . . . . . . . . . . . . .85
Table 74: UART0 Receiver Buffer Register (U0RBR -
address 0xE000 C000, when DLAB = 0, Read
Only) bit description . . . . . . . . . . . . . . . . . . . . .86
Table 75: UART0 Transmit Holding Register (U0THR -
address 0xE000 C000, when DLAB = 0, Write
Only) bit description . . . . . . . . . . . . . . . . . . . . .86
Table 76: UART0 Divisor Latch LSB register (U0DLL -
address 0xE000 C000, when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 77: UART0 Divisor Latch MSB register (U0DLM -
address 0xE000 C004, when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 78: Some baud-rates available when using 20 MHz
peripheral clock (PCLK=20 MHz) . . . . . . . . . . .87
Table 79: UART0 Interrupt Enable Register (U0IER -
address 0xE000 C004, when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table 80: UART0 Interrupt Identification Register (UOIIR -
address 0xE000 C008, read only) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table 81: UART0 interrupt handling . . . . . . . . . . . . . . . . .89
User manual
Table 82: UART0 FIFO Control Register (U0FCR - address
0xE000 C008) bit description. . . . . . . . . . . . . . 90
Table 83: UART0 Line Control Register (U0LCR - address
0xE000 C00C) bit description . . . . . . . . . . . . . 91
Table 84: UART0 Line Status Register (U0LSR - address
0xE000 C014, read only) bit description . . . . . 91
Table 85: UART0 Scratch pad register (U0SCR - address
0xE000 C01C) bit description . . . . . . . . . . . . . 92
Table 86: UART0 Transmit Enable Register (U0TER -
address 0xE000 C030) bit description . . . . . . . 93
Table 87: UART1 pin description . . . . . . . . . . . . . . . . . . . 95
Table 88: UART1 register map . . . . . . . . . . . . . . . . . . . . 97
Table 89: UART1 Receiver Buffer Register (U1RBR -
address 0xE001 0000, when DLAB = 0 Read
Only) bit description . . . . . . . . . . . . . . . . . . . . 98
Table 90: UART1 Transmitter Holding Register (U1THR -
address 0xE001 0000, when DLAB = 0 Write
Only) bit description . . . . . . . . . . . . . . . . . . . . . 98
Table 91: UART1 Divisor Latch LSB register (U1DLL -
address 0xE001 0000, when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 92: UART1 Divisor Latch MSB register (U1DLM -
address 0xE001 0004, when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 93: Some baud-rates available when using 20 MHz
peripheral clock (PCLK = 20 MHz). . . . . . . . . . 99
Table 94: UART1 Interrupt Enable Register (U1IER -
address 0xE001 0004, when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 95: UART1 Interrupt Identification Register (U1IIR -
address 0xE001 0008, read only) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 96: UART1 interrupt handling. . . . . . . . . . . . . . . . 102
Table 97: UART1 FIFO Control Register ( U1FCR - address
0xE001 0008) bit description . . . . . . . . . . . . . 103
Table 98: UART1 Line Control Register (U1LCR - address
0xE001 000C) bit description. . . . . . . . . . . . . 103
Table 99: UART1 Modem Control Register (U1MCR -
address 0xE001 0010), LPC2134/6/8 only bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 100:UART1 Line Status Register (U1LSR - address
0xE001 0014, read only) bit description. . . . . 104
Table 101:UART1 Modem Status Register (U1MSR -
address 0xE001 0018), LPC2134/6/8 only bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 102:UART1 Scratch pad register (U1SCR - address
0xE001 0014) bit description . . . . . . . . . . . . . 106
Table 103:UART1 Transmit Enable Register (U1TER -
address 0xE001 0030) bit description . . . . . . 107
2
Table 104:I
C Pin Description. . . . . . . . . . . . . . . . . . . . . 110
Table 105:I2C0CONSET and I2C1CONSET used to
Rev. 01 — 24 June 2005
UM10120
Chapter 24: Supplementary information
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
continued >>
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