Philips LPC213 Series User Manual page 101

Philips Semiconductors
Volume 1
Table 95:
Bit
3:1
5:4
7:6
[1]
Interrupts are handled as described in Table 83. Given the status of U1IIR[3:0], an
interrupt handler routine can determine the cause of the interrupt and how to clear the
active interrupt. The U1IIR must be read in order to clear the interrupt prior to exiting the
Interrupt Service Routine.
The UART1 RLS interrupt (U1IIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the UART1RX input: overrun error
(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART1 Rx error
condition that set the interrupt can be observed via U1LSR[4:1]. The interrupt is cleared
upon an U1LSR read.
The UART1 RDA interrupt (U1IIR[3:1] = 010) shares the second level priority with the CTI
interrupt (U1IIR[3:1] = 110). The RDA is activated when the UART1 Rx FIFO reaches the
trigger level defined in U1FCR7:6 and is reset when the UART1 Rx FIFO depth falls below
the trigger level. When the RDA interrupt goes active, the CPU can read a block of data
defined by the trigger level.
The CTI interrupt (U1IIR[3:1] = 110) is a second level interrupt and is set when the UART1
Rx FIFO contains at least one character and no UART1 Rx FIFO activity has occurred in
3.5 to 4.5 character times. Any UART1 Rx FIFO activity (read or write of UART1 RSR) will
clear the interrupt. This interrupt is intended to flush the UART1 RBR after a message has
been received that is not a multiple of the trigger level size. For example, if a peripheral
wished to send a 105 character message and the trigger level was 10 characters, the CPU
would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI
interrupts (depending on the service routine) resulting in the transfer of the remaining 5
characters.
User manual
UART1 Interrupt Identification Register (U1IIR - address 0xE001 0008, read only)
bit description
Symbol Value
Interrupt
Identification
011
010
110
001
000
-
FIFO Enable
LPC2134/6/8 only. For all other LPC213x devices '000' combination is Reserved.
Rev. 01 — 24 June 2005
Description
U1IER[3:1] identifies an interrupt corresponding to
the UART1 Rx FIFO. All other combinations of
U1IER[3:1] not listed above are reserved
(100,101,111).
1 - Receive Line Status (RLS).
2a - Receive Data Available (RDA).
2b - Character Time-out Indicator (CTI).
3 - THRE Interrupt.
[1]
4 - Modem Interrupt.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
These bits are equivalent to U1FCR[0].
UM10120
Chapter 10: UART1
Reset value
0
NA
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
101