3.5
Digital Output
Insert an iDAQ module supporting digital output function to perform digital output
update/generation. The following sections describe the digital output update/genera-
tion mechanism. These output functions are applied to TTL digital output, isolated
digital output and SSR/Mechanical relay output, i.e. all the digital output modules. For
detailed specifications of the functions, refer to the document of the corresponding
iDAQ module.
3.5.1
Static Digital Output Update
With static digital output update, the digital output state is updated only when the soft-
ware sends a "write static digital output sample" command. The digital output state
remains unchanged at other times. This is shown in Figure 3.19.
3.5.2
Buffered Digital Output Waveform Generation
With buffered digital output waveform generation, the rate and duration of the gener-
ation is controlled by hardware timing signals. The digital output waveform to be gen-
erated are first programmed and stored in the buffer memory. The digital output state
then is updated for each sample clock as shown in Figure 3.20.
Figure 3.20 Buffered digital output waveform generation.
iDAQ-731_751_763D User Manual
Figure 3.19 Static digital output update.
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