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LCD mode setting
register (LCDMD)
SEGSET2 SEGSET1
SEGSET0 MDSET1
Note 64-pin product only.
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LCD clock control
LCD display mode
register (LCDC)
register (LCDM)
MDSET0
LCDC3 LCDC2 LCDC1 LCDC0
LCDON
SCOC
VLCON
2
2
2
f
LCLK
f
LCD
f
/2
LCLK
Prescaler
f
/2
2
LCLK
f
f
f
f
LCD
LCD
LCD
LCD
6
7
8
9
2
2
2
2
LCD
clock
selector
Clock
VLCON
generator for
boosting
Booster
circuit
LCD drive voltage controller
CAPH CAPL
V
V
V
LC2
LC1
LC0
Figure 3-2. Block Diagram of LCD Controller/Driver
Internal bus
LCD voltage boost control
register 0 (VLCG0)
LCDM2
LCDM1
LCDM0
CTSEL1 CTSEL0
GAIN
3
LCDCL
Timing
controller
Segment voltage
controller
Common voltage
Common driver
controller
COM0 COM1 COM2 COM3
Display data memory
LCDSEG's 00H
LCDSEG's 23H
LCDSEG's 24H
-------
7
6 5
4
3 2 1 0
7
6 5
4
3 2 1 0
7
6 5
4
-------
3 2 1 0
3 2 1 0
-------
selector
selector
LCDON
LCDON
LCDON
-------
-------
-------
-------
Segment
Segment
-------
driver
driver
- - - - - - - - - -
S35
S0
Display data memory
LCDSEG's 27H
-------
3 2 1 0
7
6 5
4
3 2 1 0
-------
3 2 1 0
3 2 1 0
-------
selector
selector
LCDON
-------
-------
-------
-------
Segment
Segment
-------
driver
driver
- - - - - - - - - -
Note
Note
S39
S36
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