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22
Table 21 Correspondence terminal position of through evaluation MCU all
hole for terminal check at time of selection with 48pin LCD (U1)
Port
Function
P61
S09/PPG11
P62
S10/TO10
P63
S11/TO11
P64
S12/EC1
P65
S13/SCK
P66
S14/SOT
P67
S15/SIN
P14
PPG0
P13
TRG0/ADTG
P12
UCK0
P11
UO0
P10
UI0
P07
INT07/AN07
P06
INT06/AN06
P05
INT05/AN05
P04
INT04/AN04
P03
INT03/AN03
P02
INT02/AN02
P01
INT01/AN01
P00
INT00/AN00
−
MOD
−
X0
−
X1
−
Vss
U1 No.
No.
Port
184
25
Vcc
183
26
PG0
182
27
X1A
181
28
X0A
180
29
RSTX
179
30
P90
178
31
P91
104
32
P92
103
33
P93
102
34
P94
101
35
P95
100
36
PA0
137
37
PA1
136
38
PA2
135
39
PA3
134
40
PB0
133
41
PB1
132
42
PB2
131
43
PB3
130
44
PB4
60
45
PB5
59
46
PB6
58
47
PB7
−
48
P60
Function
U1 No.
−
−
(Cpin)
46
−
56
−
55
FTEST
54
V3
219
V2
218
V1
217
V0
216
C0
215
C1
214
COM0
213
COM1
212
COM2
211
COM3
210
S00
209
S01
208
S02
207
S03/PPG00
206
S04/PPG01
205
S05/TO00
204
S06/TO01
203
S07/EC0
202
S08/PPG10
185
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