Table of Contents
Advertisement
4.7
DVMAIN SCHEMATIC DIAGRAM
MAIN (DVMAIN)
0
1
TO MAIN IF
CN105
TDO
TMS
TCMK
TRST
R3059
100
TO CAMERA DSP
TDB
5
C3047
L3002
TO REG
DIGITAL_3V
REG_3V
TO CAMERA DSP,
NQR0129-002X
REG
REG_2.5V
TO REG
REG_1.8V
C3003
1
TO REG
GND
∗
L3003
DIGITAL_2.5V
C3004
∗
L3005
DIGITAL_1.8V
NQR0006-001X
C3007
NCB10JK-106X
1
4
L3004
ANALOG_2.5V
NQR0006-001X
C3005
10
/6.3
T
∗
L3006
ANALOG_1.8V
C3008
10
/6.3
T
L3001
D3004
MA2Z720-X
PHY_2.85V
NQR0129-002X
C3001
10
/6.3
T
3
L3012
NQR0129-002X
R3025
∗
Q3001
∗
∗
C3009
C3006
R3026
∗
∗
2
TO PRE/REC
AGC_OUT
VRB_AGC
VREF_1.1
REC_DATA
REC_CLK
REC_CTL
REF_CLK
ATFI
VRB_ATF
L3015
NQR0006-001X
R3046
R3045
C3056
∗
T
1
R3070
∗
∗
NOTE : The parts with marked ( ) is not used.
A
B
C3041
C3040
∗
∗
N.C
N.C
∗
MON0
MON1
VDDE
VDDI
MON2
MON3
MON4
MON5
VSS
MON6
MON7
MON8
MON9
MON10
C3042
0.01
MON11
MON12
C3043
VDDE
VDDI
0.01
MON13
MON14
MON15
MON16
MON17
MON18
MON19
VSS
MON20
MON21
MON22
MON23
VDDE
MON24
MON25
MON26
MON27
VDDE
C3044
0.1
N.C
VDDP
VSSP
VDDA
VSS
N.C
N.C
VDDE
VSS
VSS
VDDE
VDDI
VSS
VDDE
VDDE
VDDI
VSS
VSS
MTEST
C3045
0.1
PHYAVD2
BUSRST
RA3004
10k
PHYAVS2
PMODE
PWR3
PWR1
PWR2
VDDI
PHYAVS1
PHYAVD3
C3046
0.01
PHYAVD1
VSS
VDDE
A/D
VCO
D/A
D/A
VDDI
VSS
R3071
0
C3011
0.1
TL3005
R3050
∗
R3003
1M
R3073
∗
C3014
Q3002
∗
C3054
1
∗
82k
R3040
2.2k
R3049
10
IC3004
R3074
12k
MC74VHC1G04DF-X
10K
VCO
IC3007
R3043
1.2k
JCY0174
R3041
R3044
560
R3072
C3067
1.5k
∗
∗
C3052
0.047
C
NOTES :
For the destination of each signal and further line connections that are cut off from
this diagram , refer to "4.1 BOARD INTERCONNECTIONS".
When ordering parts , be sure to order according to the Part Number indicated in the Parts List.
CPUBUSTYPE
CPUDSLOGIC
CPUWAITLOGIC
XCPUDSTB1
XCPUDSTB0
IC3001
JCY0152
[DVMAIN]
VCXO12O
VCXO11O
VCO
PWMAUDIO
A/D
L3007
2.2µ
CH
R3009
10k
R3010
10k
TL3001
∗
R3075
L3014
TL3002
10µ
IC3002
∗
R3047
BU2501FV-X
R3068
X3001
∗
∗
R3048
∗
[12ch_EVR_DAC]
C3068
∗
[41.85M]
C3058
NAX0169-001X
∗
CH
CH
C3057
∗
T
C3070
C3069
C3059
∗
∗
22/4
D
E
4-15
4-16
CPUWAIT
XINT
XCPUCS
XCPURW
CPUALE
INV
INH
OUTV
OUTH
BRSI3
BRSI2
BRSI1
BRSI0
YSI3
YSI2
YSI1
YSI0
BRSO3
BRSO2
BRSO1
BRSO0
YSO3
YSO2
YSO1
YSO0
AODAT0
AODAT1
VSS
AOBCK
AOLRCK
DODAT
C3038
0.1
VDDI
DOBCK
DOLRCK
AIDAT0
AIDAT1
AIMCK
AIBCK
AILRCK
DIDAT
R3034
DIMCK
C3037
8P
2.2k
DIBCK
X3002
DILRCK
OSC11O
[NAX0480-001X]
OSC11I
C3036
8P
R3033
∗
OSC24O
OSC24I
VCXO12I
L3008
L3009
∗
12µ
VCXO11I
C3031
0.1
VDDP
C3030
0.1
CH
C3034
CH
C3035
VCIAUD
C3032
C3033
∗
∗
0.001
12P
VSSP
VDDE
R3027
VSS
10k
VDDE
N.C
C3049
2200P
LPFIN
R3029
LPFOUT
15K
R3036
R3037
C3048
VDDE
10K
680
0.047
PHYAVS3
PHYVSR
C3029
PHYVSA
0.01
PHYVDR
PHYVDA
C3050
0.01
CH
F
TO VIDEO I/O,
CAMERA DSP
INV
INH
R3005
10
OUTV
TO D.CPU, CAMERA DSP
R3006
10
OUTH
TO CAMERA DSP
DCO3
DCO2
DCO1
TO VIDEO I/O,
DCO0
CAMERA DSP
DYO3
DYO2
DYO1
DYO0
DCI3
RA3001
DCI2
10
DCI1
DCI0
DYI3
RA3002
TO CAMERA DSP
DYI2
10
DYI1
DYI0
CLK27A
TO AUDIO
RA3003
AODAT
AIDAT
AIMCK
AIBCK
AILRCK
10
TO D.CPU
ADDT15
ADDT14
ADDT13
ADDT12
ADDT11
ADDT10
ADDT09
ADDT08
ADDT07
ADDT06
ADDT05
ADDT04
ADDT03
ADDT02
ADDT01
ADDT00
DV_WAIT
DRWSEL
DRE
DWE
DALE
DV_RST
CLK27SEL
SRV_TRK
TSR
FRP
SPA
HID1
TL3006
SBE
TO MAIN IF
CN105
FS_PLL
MAIN_VCO
PB_CLK
DISCRI
TO MAIN IF
RA3005
0Ω
CN103
NRZ0040-0R0X
TPA+
TPA-
TPB+
TPB-
DUMP_CTL
NOSIG_LV
TO PRE/REC
ATF_GAIN
RECCADJ
DATA_OUT
CLK_OUT
TO SYSCON
DAC_CS
H_OFFSET
TO OP DRIVER
H_GAIN
y10261001a_rev0
G
H
Advertisement
Table of Contents
