Transmitter System - Alinco DR-M03R Service Manual

5. Squelch Circuit

2) Transmitter System

1. Modulator Circuit
2. Power Amplifier Circuit
y 3. APC Circuit
3) PLL Synthesizer Circuit
1. PLL
2. Reference Frequency
Circuit
4
The detected output which is outputted from pin 9 of IC108 is inputted to
pin 8 of 1C108 after it was been amplified IC120:A and it is outputted from
pin 7 after the noise component was been eliminated from the composed
band pass filter in the built in amplifier of the iC, then the signal is rectified
by the internal diode in IC108 to convert into DC component. The adjusted
voltage level at VR101 is delivered to the comparator of the CPU.
The voltage is led to pin 2 of CPU and compared with the setting voltage.
The squelch will open if the input voltage is lower than the setting voltage.
During open squelch, pin 30 (SQC) of the CPU becomes "L" level, AF
control signal is begin controlled and sounds is outputted from speaker.
The audio signal is converted to an electrical signal by the microphone,
and input it to the microphone amplifier (Q6). Amplified signal which
passes through mic-mute control IC109 is adjusted to an appropriate
mic-volume by means of mic-gain adjust VR106.
1C114:D and C consists of two operational amplifiers; one amplifier (pin
12,13 and 14) is composed of pre-emphasis and I DC circuit and the other
(pin 8, 9 and 10) is composed of a splatter filter. The maximum frequency
deviation is obtained by VR107. And input to the signal switch (IC113)
(9600 bps packet signal, input switch) and input to the anode of the
variable capacitor of the VCO, to change the electric capacity in the
oscillation circuit. This produces the frequency modulation.
The transmitted signal is oscillated by the VCO, amplified by the younger
amplifier (Q115 and Q103), and input to the final power amplifier (Q701).
The signal is then amplified by the final power amplifier (Q701) and led to
the antenna switch (D110) and low-pass filter (L113, L114, L115, C215,
C216, C202, C203 and C204), where unwanted high harmonic waves are
reduced as needed, and the resulting signal is supplied to the antenna.
Part of the transmission power from the low-pass filter is detected by
D111, converted to DC. The detection voltage is passed through the APC
circuit (IC114:B), then it controls the APC voltage supplied to final power
amplifier Q701 to fix the transmission power.
The dividing ratio is obtained by sending data from CPU (1C1) to pin 10
and sending clock pulses to pin 9 of the PLL IC (IC116). The oscillated
signal from the VCO is amplified by the buffer (Q134 and Q135) and input
to pin 8 of IC116. Each programmable divider in 1C116 divides the
frequency of the input signal by N according to the frequency data, to
generate a comparison frequency of 5 or 6.25 kHz.
The reference frequency appropriate for the channel steps is obtained by
dividing the 11.15 MHz reference oscillation (X601) by 4250 or 3400,
according to the data from the CPU (IC1). When the resulting frequency is
5 kHz, channel step of 5, 8.33, 10, 15, 20, 25, 30 and 50 kHz are used.
When it is 6.25 kHz, the 12.5 kHz channel step is used.
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