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THEORY OF OPERATION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
2 2
23
24
25
26
27
28
4-9 .
DIGITAL OUTPUT (Refer to schematic no ' s 25715D,
257l6D, 257l7C, and 25823C ) .
a.
Isolation Circuitry,
LO and digital output LO is achieved through the use
of an optically coup'led isolator for each signal
transmitted between the 616 and 6162.
are NPN types and provide greater than 10
tion resistance.
The anodes of all light emitting
diodes are connected to +5 volts.
whenever the cathode is connected low (a 330n current
limit resistor is used with each input ) .
of each isolator transistor is connected in a ground
ed emitter or emitter- follower configuration .
b .
Decade Counters .
decade counter stages QA201, QA20 2 , and QA203 for
" I " ,
"10", and "lOa" respectively .
circuit provides BCD information using four lines
identified as 1 x lo n , 2 x lO n , 4 x lO n , and 8 x IO n .
c .
are used to control data flow to the output buffer
Integrated circuits QA20 5 , QA206 � and QA207
stages.
are enabled by the output of QA223A (ENB) .
Buffered Output Stage .
d .
of a Keithley Part No. IC-22 NAND gate (four gates
per circuit module ) .
The buffers utilize "open col
lector" output transis tors .
connected to an individual STROBE control for mon-
28
Pin Identification for LSI
F
G
Tl
T3
HOLD
MR
TH
CLK
B
A
D
E
-- --
C
CS
DP
f4 4
TO
Fl
F 4
+5
-12
LOW
CN
TZ
R4
Rl
R2
F2
Isolation of electrometer
The isolators
Ia
n isola
The diode conducts
The output
The Model 6162 utilizes three
Each integrated
Individual storage registers
Each buffer is composed
Each circuit module is
TABLE 4 - 7 .
Function
Segment drive
Segment drive
Multiplex Line
Display hold
Range Enab Ie
Threshold input
Clock Pulse
drive
Segment
Segment
drive
Segment
drive
drive
Segment
drive
Current
Switch
No connection
No connection
Multiplex line
---
-
-
-
Power
Power
Common
}
Count Now
Range
Line
Range
Line
Range
Line
---
itoring two or more 6162 outputs connected to a single
outpu� bus .
whenever the Strobe line is pulled down to digital
Each STROBE circuit consists of an inverter
low .
stage (Keithley IC-32) � a 4 . 7 kilohm pull-up resistor,
and a protection diode (Keithley RF-39 ) .
e .
Print Rate Control.
6162 consists of a timing circuit composed of inte
grated circuit QAl08, resistor Rl16 , potentiometer
Rl15 and capacitor CIOI.
continuous control of Print Rate from 1/5 second per
reading to 7 seconds per reading .
control has no effect on the Model 616 disp lay rate.
f .
by integrated circuit QAlO B .
s tage QA222C is high for a length of time estab lished
by the Print Rate Control.
output is made during the interval when Flag is high.
(Flag is low) .
BCD Hold Circuit .
Enab le pulse which in turn holds the information in
the storage registers .
ever DIOl is closed to output low.
QA109 is a flip-flop which is set b y �.
h .
display driver in the Model 616 .
is activated whenever Dl02 is closed to output low .
=
=
+5V
ON, OV
OFF
+5 V
=
ON
+5V
=
ON
=
+5V
ON
+5V - HOLD
=
inhib it 8utoranging
OV
+5V or -12V
L
,1,Ok,H? _, +SV to - IV
=
+5V
ON
+5V - ON
+SV '" ON
=
+5V
ON
+5V
ON
=
integrate mode
=
+5V
--
-
---
+5 V
ON
=
OV
+5V
+5V
-l� V
OV
2016 counts
+5V
=
=
+5V
ON
See Table 4
6 .
-
OV
Each set of four buffers is enab led
Print rate for the Model
Po tentiometer Rll5 permits
The Print Rate
The Flag output is generated
The output o f buffer
No change in the digital
This circuitry inhib its the
The Hold is activated when
This circuitry controls the
The Display Hold
MODEL 616
Integrated circuit
1175
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