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Chapters
Table of Contents
Related Manuals for Cypress CY8C28 Series
Summary of Contents for Cypress CY8C28 Series
- Page 1 Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio.
- Page 2 CY8C28xxx TRM CY8C28xxx ® PSoC Programmable System-on-Chip™ TRM (Technical Reference Manual) Document No. 001-52594 Rev. *G January 20, 2017 Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com...
- Page 3 Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products.
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Page 4: Table Of Contents
Contents Overview Section A: Overview Pin Information ........................29 ® Section B: PSoC Core CPU Core (M8C) ......................... 39 Supervisory ROM (SROM) ....................49 RAM Paging ........................57 Interrupt Controller ......................65 General Purpose I/O (GPIO) ....................73 Analog Output Drivers ......................79 Internal Main Oscillator (IMO) .................... - Page 5 Contents Overview 33. I/O Analog Multiplexer....................... 525 34. Real Time Clock (RTC) ..................... 533 35. 10-Bit SAR ADC Controller ....................537 Section H: Glossary Index CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
- Page 6 Contents Section A: Overview Document Organization ........................21 Top Level Architecture ........................22 PSoC Core ..........................22 Digital System .........................22 Analog System ........................22 System Resources ........................22 PSoC Device Characteristics ......................24 PSoC Device Distinctions ........................25 Getting Started ..........................26 Support ...........................26 Product Upgrades ........................26 Development Kits ........................26 Document History ..........................26 Documentation Conventions ......................27 Register Conventions ......................27...
- Page 7 Contents Addressing Modes........................43 2.6.1 Source Immediate ..................... 43 2.6.2 Source Direct......................44 2.6.3 Source Indexed ......................44 2.6.4 Destination Direct ...................... 45 2.6.5 Destination Indexed....................45 2.6.6 Destination Direct Source Immediate ................ 45 2.6.7 Destination Indexed Source Immediate..............46 2.6.8 Destination Direct Source Direct ................
- Page 8 Contents 4.2.7 CPU_F Register......................62 4.2.8 MVR_PP Register......................62 4.2.9 MVW_PP Register ....................63 4.2.10 CPU_F Register......................63 Interrupt Controller Architectural Description......................65 5.1.1 Posted versus Pending Interrupts................66 Application Description ......................67 Register Definitions.........................68 5.3.1 INT_CLRx Registers ....................68 5.3.1.1 INT_CLR0 Register ..................68 5.3.1.2 INT_CLR1 Register ..................69 5.3.1.3 INT_CLR2 Register ..................69 5.3.1.4...
- Page 9 Contents Internal Low Speed Oscillator (ILO) Architectural Description......................85 Register Definitions .......................85 9.2.1 ILO_TR Register .......................85 10. External Crystal Oscillator (ECO) 10.1 Architectural Description......................87 10.1.1 ECO External Components ..................88 10.2 Register Definitions .......................89 10.2.1 CPU_SCR1 Register ....................89 10.2.2 OSC_CR0 Register ....................90 10.2.3 OSC_CR2 Register ....................91 10.2.4 ECO_TR Register .....................91 11.
- Page 10 CY8C28x23 Register Maps ....................114 Register Map Bank 0 Table: User Space ..............114 Register Map Bank 1 Table: Configuration Space ...........115 CY8C28x33 Register Maps ....................116 Register Map Bank 0 Table: User Space ..............116 Register Map Bank 1 Table: Configuration Space ...........117 CY8C28x43 Register Maps ....................118 Register Map Bank 0 Table: User Space ..............118 Register Map Bank 1 Table: Configuration Space ...........119...
- Page 11 Contents 13.2.33 ASCxxCR1 ......................162 13.2.34 ASCxxCR2 ......................163 13.2.35 ASCxxCR3 ......................164 13.2.36 ASDxxCR0 ......................165 13.2.37 ASDxxCR1 ......................166 13.2.38 ASDxxCR2 ......................167 13.2.39 ASDxxCR3 ......................168 13.2.40 DECx_DH .......................169 13.2.41 DECx_DL ........................170 13.2.42 MULx_X ........................171 13.2.43 MULx_Y ........................172 13.2.44 MULx_DH .......................173 13.2.45 MULx_DL ........................174 13.2.46 MACx_X/ACCx_DR1 ....................175 13.2.47 MACx_Y/ACCx_DR0 ....................176 13.2.48 MACx_CL0/ACCx_DR3 ..................177...
- Page 12 13.3.3 PRTxIC0 .........................220 13.3.4 PRTxIC1 .........................221 13.3.5 DxCxxFN ........................222 13.3.6 DxCxxIN ........................224 13.3.7 DxCxxOU ........................226 13.3.8 DxCxxCR1 (Timer Control:000) ................228 13.3.9 DxCxxCR1 (Counter Control:001) ................229 13.3.10 DxCxxCR1 (CRCPRS Control:010) ................230 13.3.11 DxCxxCR1 (PWMDBL Control:011) ...............231 13.3.12 DxCxxCR1 (Dead Band Control:100) ..............232 13.3.13 DxCxxCR1 (SPIM Control:0-110) ................233 13.3.14 DxCxxCR1 (SPIS Control:0-110) ................234 13.3.15 DxCxxCR1 (DSM Control:111) ................235...
- Page 13 Contents 13.3.56 RTC_M ........................276 13.3.57 RTC_S ........................277 13.3.58 RTC_CR .........................278 13.3.59 SADC_CR0 ......................279 13.3.60 SADC_CR1 ......................280 13.3.61 SADC_CR2 ......................281 13.3.62 SADC_CR3 ......................282 13.3.63 SADC_CR4 ......................283 13.3.64 I2Cx_ADDR ......................284 13.3.65 AMUX_CLK ......................285 13.3.66 GDI_O_IN .......................286 13.3.67 GDI_E_IN .......................287 13.3.68 GDI_O_OU ......................288 13.3.69 GDI_E_OU ......................289 13.3.70 DECx_CR .......................290 13.3.71 MUX_CRx .......................291...
- Page 14 15. Array Digital Interconnect (ADI) 15.1 Architectural Description.......................325 16. Row Digital Interconnect (RDI) 16.1 Architectural Description.......................327 16.2 Register Definitions.......................329 16.2.1 RDIxRI Register.......................329 16.2.2 RDIxSYN Register ....................330 16.2.3 RDIxIS Register .......................331 16.2.4 RDIxLTx Registers ....................332 16.2.5 RDIxROx Registers ....................333 16.2.5.1 RDIxRO0 Register..................333 16.2.5.2 RDIxRO1 Register..................333 16.2.6 RDIxDSM Register ....................334 16.3 Timing Diagram ........................334...
- Page 15 Contents 17.1.14.4 Asynchronous Receiver Function..............346 17.1.14.5 Usability Exceptions ..................346 17.1.14.6 Block Interrupt ...................346 17.1.15 DSM function ......................346 17.1.15.1 Usability Exception ..................347 17.1.15.2 Block interrupt ...................347 17.2 Register Definitions ......................348 17.2.1 DxCxxDRx Registers ....................349 17.2.1.1 Timer Register Definitions .................349 17.2.1.2 Counter Register Definitions ..............350 17.2.1.3 Dead Band Register Definitions ..............350 17.2.1.4 PWMDBL Register Definitions ..............351 17.2.1.5 CRCPRS Register Definitions ..............351...
- Page 16 18.1.3.1 Column Clock Synchronization..............395 18.1.4 Decimator and Incremental ADC Interface ..............395 18.1.4.1 Decimator ....................395 18.1.4.2 Incremental ADC ..................395 18.1.5 Analog Modulator Interface (Mod Bits) ..............396 18.1.6 Analog Synchronization Interface (Stalling) .............396 18.2 Application Description ......................396 18.2.1 SAR Hardware Acceleration ..................396 18.2.1.1 Architectural Description................396 18.2.1.2 Application Description ................397 18.2.1.3 SAR Timing ....................399...
- Page 17 Contents ® 22. Continuous Time PSoC Block 22.1 Architectural Description ......................425 22.2 Register Definitions ......................426 22.2.1 ACCxxCR3 Register ....................427 22.2.2 ACCxxCR0 Register ....................429 22.2.3 ACCxxCR1 Register ....................429 22.2.4 ACCxxCR2 Register ....................430 ® 23. Switched Capacitor PSoC Block 23.1 Architectural Description.......................431 23.2 Application Description ......................433 23.3 Register Definitions ......................434 23.3.1 ASCxxCR0 Register ....................435...
- Page 18 24.3.11 ACE_ABF_CR0 Register ..................456 24.3.12 ACExxCR1 Register ....................456 24.3.13 ACExxCR2 Register ....................457 24.3.14 ASExxCR0 Register ....................457 24.3.15 ACE_AMD_CR1 Register ..................457 24.3.16 ACE_PWM_CR Register ..................458 24.3.17 ACE_ADCx_CR Register ..................458 24.3.18 ACE_CLK_CR0 Register ..................459 24.3.19 ACE_CLK_CR1 Register ..................459 24.3.20 ACE_CLK_CR3 Register ..................459 Section F: System Resources Top-Level System Resources Architecture ..................461 Interpreting the System Resources Documentation ...............461...
- Page 19 Contents 27.1.1.1 Dedicated Data/Clock Input Selections for Single Decimator Row ...485 27.1.1.2 Single External Decimation Clock Supports Four Decimators ....486 27.1.1.3 Single Incremental Gating Clock Supports Six Analog Compare Outputs 486 27.1.1.4 ACC/ACE Interrupts Replacement ............487 27.2 Register Definitions ......................488 27.2.1 DECx_DH Register ....................488 27.2.2 DECx_DL Register ....................488 27.2.3 DEC_CR0 Register....................489...
- Page 20 30.3.2 CPU_SCR0 Register ....................515 30.4 Timing Diagrams ........................516 30.4.1 Power On Reset .....................516 30.4.2 External Reset ......................516 30.4.3 Watchdog Timer Reset ...................516 30.4.4 Reset Details ......................518 30.5 Power Consumption ......................518 31. Switch Mode Pump (SMP) 31.1 Architectural Description.......................519 31.2 Application Description ......................520 31.2.1 Component Value Selection..................520 31.3 Register Definitions ......................521 31.3.1 VLT_CR Register ....................521...
- Page 21 Contents 34.2.4 RTC_CR ........................535 35. 10-Bit SAR ADC Controller 35.1 Architectural Description.......................537 35.1.1 ADC Clock Generation ....................537 35.1.2 Voltage Doubler Clock Generation ................538 35.1.3 ADC FSM ........................538 35.1.4 SAR Algorithm and Data Process................538 35.1.5 A-D-C Operation Mode ....................539 35.1.6 ‘Ready’ Bit, ‘Ongoing’ Bit and Interrupt..............540 35.1.7 Converted Data Format and Read Sequence ............540 35.2 Application Description ......................540 35.2.1 ADC Sample Rate and Clock Selection..............540...
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Page 22: Section A: Overview
25). For the most up-to-date Ordering, Pinout, Packaging, or Electrical Specification information, refer to the individual PSoC device’s data sheet. For the most current technical reference manual information, refer to the addendum. To obtain the newest product documentation, go to the Cypress web site at http://www.cypress.com/psoc. This section encompasses the following chapter: ■... -
Page 23: Top Level Architecture
Top Level Architecture The PSoC block diagram on the next page illustrates the top Analog System level architecture of the CY8C28xxx family of PSoC devices. The Analog System is composed of analog columns in a Each major grouping in the diagram is covered in this man- block array, analog references, analog input muxing, and ual in its own section: PSoC Core, Digital System, Analog analog drivers. - Page 24 PSoC Top-Level Block Diagram Analog Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Drivers ® PSoC CORE SYSTEM BUS Global Digital Interconnect Global Analog Interconnect Flash Nonvolatile Memory SRAM 1K Supervisory ROM (SROM) CPU Core (M8C) Sleep and Interrupt Watchdog...
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Page 25: Psoc Device Characteristics
PSoC Device Characteristics There are a number of parts in the CY8C28xxx PSoC Pro- The following table lists the resources available for specific grammable System-on-Chip family. Besides differentiating CY8C28xxx device groups. The check mark or appropriate these by way of part numbers, each part is easily distin- information denotes that a system resource is available for guished by the unique number of digital rows and/or analog the device. -
Page 26: Psoc Device Distinctions
PSoC Device Distinctions The PSoC Programmable System-on-Chip device distinctions are listed in the following table and in each chapter section where it is appropriate. The PSoC device distinctions are significant exceptions or differences between CY8C28xxx PSoC groups and devices. They represent a unique difference from the information otherwise presented in this manual which encompasses all CY8C28xxx PSoC devices. -
Page 27: Getting Started
Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Program- mable System-on-Chip) to view a current list of available items. -
Page 28: Documentation Conventions
Documentation Conventions Units of Measure The following table lists the units of measure used in this There are only four distinguishing font types used in this manual. manual, besides those found in the headings. ■ The first is the use of italics when referencing a docu- Units of Measure ment title or file name. -
Page 29: Acronyms
Acronyms Acronyms (continued) Acronym Description The following table lists the acronyms that are used in this program counter manual. program counter high program counter low Acronyms power down Acronym Description PSoC™ memory arbiter ABUS analog output bus power on reset alternating current PPOR precision power on reset... -
Page 30: Pin Information
1. Pin Information This chapter lists, describes, and illustrates all CY8C28xxx PSoC device pins and pinout configurations. For up-to-date Ordering, Pinout, and Packaging information, refer to the individual PSoC device's data sheet or go to: http://www.cypress.com/psoc. This chapter encompasses the following: ■... -
Page 31: 20-Pin Part Pinouts
Pin Information 1.1.1 20-Pin Part Pinouts Table 1-1. 20-Pin Part Pinout (SSOP) Type CY8C28243 PSoC Device Description Name S, AI, M, P0[7] Analog column mux input; Integration Cap for I, M, S P0[7] MR; ADC input channel. S, AIO, M, P0[5] P0[6], M, AI, S S, AIO, M, P0[3] P0[4], M, AIO, S... -
Page 32: 28-Pin Part Pinouts
Pin Information 1.1.2 28-Pin Part Pinouts Table 1-2. 28-Pin Part Pinout (SSOP) Type CY8C28403, CY8C28413, CY8C28433, CY8C28445, and Description Name CY8C28452 28-Pin PSoC Devices Analog column mux and SAR ADC I, M, S P0[7] S, AI, M, P0[7] input P0[6], M, AI, S S, AIO, M, P0[5] Analog column mux and SAR ADC I/O, M, S P0[5]... -
Page 33: 44-Pin Part Pinouts
Pin Information 1.1.3 44-Pin Part Pinouts Table 1-3. 44-Pin Part Pinout (TQFP) Type CY8C28513, CY8C28533, and CY8C28545 PSoC Devices Description Name P2[5] I, M P2[3] Direct switched capacitor block input. I, M P2[1] Direct switched capacitor block input. P4[7] P4[5] P4[3] M , P2[5] P2[4], M , External AG ND... -
Page 34: 48-Pin Part Pinouts
Pin Information 1.1.4 48-Pin Part Pinouts Table 1-4. 48-Pin Part Pinout (QFN**) CY8C28623, CY8C28643, and CY8C28645 PSoC Devices Type Description Name I/O I, M P2[3] Direct switched capacitor block input I/O I, M P2[1] Direct switched capacitor block input P4[7] P4[5] P2[4], M, External AGND AI, M, P2[3]... -
Page 35: 56-Pin Part Pinout
Pin Information 1.1.5 56-Pin Part Pinout The 56-pin SSOP package is for the CY8C28000 On-Chip Debug (OCD) PSoC device. Note OCD parts are only used for in-circuit debugging. OCD parts are NOT available for production. Table 1-5. 56-Pin Part Pinout (SSOP) Type CY8C28000 PSoC Devices Description... -
Page 36: Section B: Psoc ® Core
® Section B: PSoC Core ® The PSoC Core section discusses the core components of a PSoC device with a base part number of CY8C28xxx. This section encompasses the following chapters: ■ ■ CPU Core (M8C) on page 39 Internal Main Oscillator (IMO) on page 81 ■... -
Page 37: Core Register Summary
Core Register Summary The following table lists all the PSoC registers for the CPU core in address order within their system resource configuration. The bits that are grayed out are reserved bits. If these bits are written, they should always be written with a value of ‘0’. For the core registers, the first ‘x’... - Page 38 Summary Table of the Core Registers (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,01h PRT0DM1 Drive Mode 1[7:0] RW : FFh 1,02h PRT0IC0 Interrupt Control 0[7:0] RW : 00 1,03h PRT0IC1 Interrupt Control 1[7:0]...
- Page 39 Summary Table of the Core Registers (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access SLEEP AND WATCHDOG REGISTERS (page 99) Sleep GPIO Analog 3 Analog 2 Analog 1 Analog 0 V Monitor 0,E0h...
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Page 40: Cpu Core (M8C)
For additional information concerning the M8C instruction set, refer to ® the PSoC Designer™ Assembly Language User Guide available at the Cypress web site (http://www.cypress.com/psoc). For a complete table of the CPU Core registers, refer to the “Summary Table of the Core Registers” on page 36. -
Page 41: Instruction Set Summary
If more information is needed, the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (refer to the http://www.cypress.com/psoc web site). Table 2-1. Instruction Set Summary Sorted Numerically by Opcode... - Page 42 CPU Core (M8C) Table 2-2. Instruction Set Summary Sorted Alphabetically by Mnemonic Instruction Format Flags Instruction Format Flags Instruction Format Flags 09 4 ADC A, expr C, Z INC [expr] C, Z POP X 0A 6 ADC A, [expr] C, Z INC [X+expr] C, Z POP A...
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Page 43: Instruction Formats
CPU Core (M8C) Instruction Formats 2.5.2 Two-Byte Instructions The majority of M8C instructions are two bytes in length. The M8C has a total of seven instruction formats which use While these instructions can be divided into categories iden- instruction lengths of one, two, and three bytes. All instruc- tical to the one-byte instructions, this does not provide a tion bytes are fetched from the program memory (Flash), useful distinction between the three two-byte instruction for-... -
Page 44: Three-Byte Instructions
CPU Core (M8C) 2.5.3 Three-Byte Instructions These instructions change program execution uncondition- ally to an absolute address. The instructions use an 8-bit The three-byte instruction formats are the second most opcode, leaving room for a 16-bit destination address. prevalent instruction formats. These instructions need three The second three-byte instruction format, shown in the sec- bytes because they either move data between two ond row of... -
Page 45: Source Direct
CPU Core (M8C) 2.6.2 Source Direct For these instructions, the source address is stored in operand 1 of the instruction. During instruction execution, the address will be used to retrieve the source value from RAM or register address space. The result of these instructions is placed in either the M8C A or X register as indicated by the instruction’s opcode. -
Page 46: Destination Direct
CPU Core (M8C) 2.6.4 Destination Direct For these instructions, the destination address is stored in the machine code of the instruction. The source for the operation is either the M8C A or X register as indicated by the instruction’s opcode. All instructions using the Destination Direct address- ing mode are two bytes in length. -
Page 47: Destination Indexed Source Immediate
CPU Core (M8C) 2.6.7 Destination Indexed Source Immediate For these instructions, the destination offset from the X register is stored in operand 1 of the instruction. The source value is stored in operand 2 of the instruction. All instructions using the Destination Indexed Source Immediate addressing mode are three bytes in length. -
Page 48: Source Indirect Post Increment
CPU Core (M8C) 2.6.9 Source Indirect Post Increment Only one instruction uses this addressing mode. The source address stored in operand 1 is actually the address of a pointer. During instruction execution, the pointer’s current value is read to determine the address in RAM where the source value is found. -
Page 49: Register Definitions
CPU Core (M8C) Register Definitions The following register is associated with the CPU Core (M8C). The register description has an associated register table show- ing the bit structure. The bits that are grayed out in the table are reserved bits and are not detailed in the register description that follows. -
Page 50: Supervisory Rom (Srom)
3. Supervisory ROM (SROM) ® This chapter discusses the Supervisory ROM (SROM) functions. For a quick reference of all PSoC registers in address order, refer to “Register Reference” on page 109. Architectural Description The SROM holds code that boots the PSoC device, cali- Table 3-1. -
Page 51: Additional Srom Feature
Supervisory ROM (SROM) The following code example puts the correct value in KEY1 more information on which SRAM addresses are modified.) and KEY2. The code is preceded by a HALT, to force the If the checksum is not valid, an internal reset is executed program to jump directly into the setup code and not acci- and the boot process starts over. -
Page 52: Hwbootreset Function
Supervisory ROM (SROM) Table 3-4. SRAM Map Post SWBootReset (00h) The HWBootReset function only requires that the CPU_A, KEY1, and KEY2 be setup correctly. As with all other SROM Address functions, if the setup is incorrect, the SROM executes a HALT. -
Page 53: Writeblock Function
Supervisory ROM (SROM) 3.1.2.4 WriteBlock Function 3.1.2.5 EraseBlock Function The WriteBlock function stores data in the Flash. Data The EraseBlock function is used to erase a block of 64 con- moves 64 bytes at a time from SRAM to Flash using this tiguous bytes in Flash. -
Page 54: Eraseall Function
Supervisory ROM (SROM) One of the uses of the TableRead function is to retrieve the protection block in each Flash bank to all zeros (the unpro- values needed to optimize Flash programming for tempera- tected state). This function is only executed by an external ture. -
Page 55: Calibrate1 Function
Supervisory ROM (SROM) Table 3-13. Calibrate0 Parameters (08h) described in the section titled “TableRead Function” on page Name Address Type Description KEY1 0,F8h Table 3-14. Calibrate1 Parameters (09h) Stack Pointer value+3, when SSC is KEY2 0,F9h executed. Name Address Type Description KEY1 0,F8h... - Page 56 Supervisory ROM (SROM) on page 51 to determine the number of Flash banks in up to the first 8K of user code, as well as the cal table. The PSoC devices. optional Flash bank 1 holds additional user code. For additional information, refer to the FLS_PR1 register on Bit 0: Bank.
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Page 57: Clocking Strategy
Supervisory ROM (SROM) Clocking Strategy Using the correct values for B, M, and T, in the Equation 3, is required to achieve the endurance specifications of the Flash. However, for device programmers where this calcula- Successful programming and erase operations, on the tion is difficult to perform, the equation is simplified by set- Flash, require you to set the CLOCK and DELAY parame- ting T to 0°C and using the hot value for B and M. -
Page 58: Ram Paging
4. RAM Paging ® This chapter explains the PSoC device’s use of RAM Paging and its associated registers. For a complete table of the RAM Paging registers, refer to the “Summary Table of the Core Registers” on page 36. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 125. -
Page 59: Stack Operations
RAM Paging 4.1.2 Stack Operations SRAM addressing modes. However, any change made to the CUR_PP, IDX_PP, or STK_PP registers will persist after As mentioned previously, the paging architecture's reset the ISR returns. Therefore, the ISR should save the current state puts the PSoC in a mode that is identical to that of a value of any paging register it modifies and restore its value 256 byte PSoC device. -
Page 60: Index Memory
RAM Paging RETI; but if the CUR_PP register is changed in the ISR, the After reset, the PgMode bits are set to 00b. In this mode, ISR is also required to restore the value before executing index memory accesses are forced to SRAM Page 0, just as the RETI instruction. -
Page 61: Register Definitions
RAM Paging Register Definitions The following registers are associated with RAM Paging and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow. -
Page 62: Stk_Pp Register
RAM Paging 4.2.3 STK_PP Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,D1h STK_PP Page Bits[2:0] RW : 00 The Stack Page Pointer Register (STK_PP) is used to set value after the stack has grown, the program must ensure the effective SRAM page for stack memory accesses in a that the STK_PP value is restored when needed. -
Page 63: Mvw_Pp Register
RAM Paging 4.2.6 MVW_PP Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,D5h MVW_PP Page Bits[2:0] RW : 00 The MVI Write Page Pointer Register (MVW_PP) is used to is written by the instruction is determined by the value of the set the effective SRAM page for MVI write memory least significant bits in this register. -
Page 64: Mvw_Pp Register
RAM Paging User Guide for more information on the MVI A, [expr] The function of this register and the MVI instructions are instruction. independent of the SRAM Paging bits in the CPU_F register. For additional information, refer to the MVR_PP register on page 192. - Page 65 RAM Paging CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
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Page 66: Interrupt Controller
5. Interrupt Controller This chapter presents the Interrupt Controller and its associated registers. The interrupt controller provides a mechanism for a ® hardware resource in PSoC devices, to change program execution to a new address without regard to the current task being performed by the code being executed. -
Page 67: Posted Versus Pending Interrupts
Interrupt Controller 4. Program execution vectors to the interrupt table. Typi- Interrupt Priority. The priorities of the interrupts only come cally, a LJMP instruction in the interrupt table sends exe- into consideration if more than one interrupt is pending dur- cution to the user's interrupt service routine (ISR) for this ing the same instruction cycle. -
Page 68: Application Description
Interrupt Controller Application Description The interrupt controller and its associated registers allow the clear all pending and posted interrupts, or clear individual user's code to respond to an interrupt from almost every posted or pending interrupts. A software mechanism is pro- functional block in the PSoC devices. -
Page 69: Register Definitions
Interrupt Controller Register Definitions The following registers are associated with the Interrupt Controller and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow. -
Page 70: Int_Clr1 Register
Interrupt Controller 5.3.1.2 INT_CLR1 Register 5.3.1.3 INT_CLR2 Register Depending on the digital row configuration of your PSoC Bit 3: DCC23. This bit allows posted DCC23 interrupts to device (see the table titled “CY8C28xxx Device Characteris- be read, cleared, or set for row 2 block 3. tics”... -
Page 71: Int_Mskx Registers
Interrupt Controller 5.3.2 INT_MSKx Registers Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,DEh INT_MSK3 ENSWINT Analog 5 Analog 4 SARADC I2C1 I2C0 RW : 00 0,DFh INT_MSK2 DCC23 DCC22 DBC21 DBC20... -
Page 72: Int_Msk1 Register
Interrupt Controller Bit 2: Analog 1. This bit allows posted analog column 1 Bit 6: DCC12. This bit allows posted DCC12 interrupts to interrupts to be read, masked, or set. be read, masked, or set for row 1 block 2. Bit 1: Analog 0. -
Page 73: Cpu_F Register
Interrupt Controller 5.3.4 CPU_F Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,F7h CPU_F PgMode[1:0] Carry Zero RL : 02 LEGEND L The AND F, expr; OR F, expr; and XOR F, expr flag instructions can be used to modify this register. x An “x”... -
Page 74: General Purpose I/O (Gpio)
6. General Purpose I/O (GPIO) This chapter discusses the General Purpose I/O (GPIO) and its associated registers, which is the circuit responsible for inter- ® facing to the I/O pins of a PSoC device. The GPIO blocks provide the interface between the M8C core and the outside world. They offer a large number of configurations to support several types of input/output (I/O) operations for both digital and ana- log systems. -
Page 75: Analog Input
General Purpose I/O (GPIO) The global I/O feature of each GPIO (port pin) is off by 6.1.3 Analog Input default. To access the feature, two parameters must be Analog signals can pass into the PSoC device core from changed. To configure a GPIO as a global input, the port PSoC device pins through the block’s AOUT pin. -
Page 76: Gpio Block Interrupts
General Purpose I/O (GPIO) 6.1.4 GPIO Block Interrupts ately high or low, to match the interrupt mode configuration. When this happens, the INTO line will pull low to assert the Each GPIO block can be individually configured for interrupt GPIO interrupt. This assumes the other system-level capability. -
Page 77: Register Definitions
General Purpose I/O (GPIO) Register Definitions The following registers are associated with the General Purpose I/O (GPIO) and are listed in address order. The register descriptions in this section have an associated register table showing the bit structure for that register. For a complete table of GPIO registers, refer to the “Summary Table of the Core Registers”... -
Page 78: Prtxdmx Registers
General Purpose I/O (GPIO) 6.2.4 PRTxDMx Registers Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,xxh PRTxDM2 Drive Mode 2[7:0] RW : FFh 1,xxh PRTxDM0 Drive Mode 0[7:0] RW : 00 1,xxh PRTxDM1 Drive Mode 1[7:0]... - Page 79 General Purpose I/O (GPIO) There are four possible interrupt modes for each port pin. Figure 6-3. GPIO Interrupt Mode 11b Two mode bits are required to select one of these modes Last Value Read From Pin was ‘0’ and these two bits are spread into two different registers Pin State Waveform Pin State Waveform (PRTxIC0 and PRTxIC1).
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Page 80: Analog Output Drivers
7. Analog Output Drivers This chapter presents the Analog Output Drivers and their associated register. The analog output drivers provide a means for ® driving analog signals off the PSoC device. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 125. -
Page 81: Register Definitions
Analog Output Drivers Register Definitions The following register is associated with the Analog Output Drivers. The register description has an associated register table showing the bit structure of the register. The bits that are grayed out in the following table are reserved bits and are not detailed in the register description that follows. -
Page 82: Internal Main Oscillator (Imo)
8. Internal Main Oscillator (IMO) This chapter presents the Internal Main Oscillator (IMO) and its associated registers. The IMO produces clock signals of 24 MHz and 48 MHz. For a complete table of the IMO registers, refer to the “Summary Table of the Core Registers” on ®... -
Page 83: Register Definitions
Internal Main Oscillator (IMO) Register Definitions The following registers are associated with the Internal Main Oscillator (IMO). The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow. -
Page 84: Imo_Tr Register
Internal Main Oscillator (IMO) on the order of 50 ms. After lock is achieved, it is recom- Oscillator (ILO) or the crystal oscillator, are synchronized to mended that this bit be forced high to decrease the jitter on this clock source. If an external clock is enabled, PLL mode the output. - Page 85 Internal Main Oscillator (IMO) CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
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Page 86: Internal Low Speed Oscillator (Ilo)
9. Internal Low Speed Oscillator (ILO) This chapter briefly explains the Internal Low Speed Oscillator (ILO) and its associated register. The Internal Low Speed ® Oscillator produces a 32 kHz clock. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 125. - Page 87 Internal Low Speed Oscillator (ILO) CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
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Page 88: External Crystal Oscillator (Eco)
10. External Crystal Oscillator (ECO) This chapter briefly explains the External Crystal Oscillator (ECO) and its associated registers. The 32.768 kHz external crys- tal oscillator circuit allows the user to replace the internal low speed oscillator with a more precise time source at low cost and low power. -
Page 89: Eco External Components
External Crystal Oscillator (ECO) 6. It is strongly advised to wait the one-second stabilization period prior to engaging the PLL mode to lock the IMO frequency to the ECO frequency. Note 1 The ILO switches back instantaneously by writing the 32 kHz Select Control bit to ‘0’. Note 2 If the proper settings are selected in PSoC Designer, these steps are automatically done in boot.asm. -
Page 90: Register Definitions
External Crystal Oscillator (ECO) 10.2 Register Definitions The following registers are associated with the External Crystal Oscillator and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The bits that are grayed out in the tables below are reserved bits and are not detailed in the register descriptions. -
Page 91: Osc_Cr0 Register
External Crystal Oscillator (ECO) 10.2.2 OSC_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,E0h OSC_CR0 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed[2:0] RW : 00 The Oscillator Control Register 0 (OSC_CR0) is used to The reset value for the CPU Speed bits is zero;... -
Page 92: Osc_Cr2 Register
External Crystal Oscillator (ECO) 10.2.3 OSC_CR2 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access SLP_EXTE SYSCLKX2 1,E2h OSC_CR2 PLLGAIN WDR32_SE EXTCLKEN RSVD RW : 00 The Oscillator Control Register 2 (OSC_CR2) is used to Bit 2: EXTCLKEN. - Page 93 External Crystal Oscillator (ECO) CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
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Page 94: Phase-Locked Loop (Pll)
11. Phase-Locked Loop (PLL) This chapter presents the Phase-Locked Loop (PLL) and its associated registers. For a complete table of the PLL registers, ® refer to the “Summary Table of the Core Registers” on page 36. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page... -
Page 95: Osc_Cr0 Register
Phase-Locked Loop (PLL) 11.2.1 OSC_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,E0h OSC_CR0 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed[2:0] RW : 00 The Oscillator Control Register 0 (OSC_CR0) is used to The reset value for the CPU Speed bits is zero;... -
Page 96: Osc_Cr2 Register
Phase-Locked Loop (PLL) 11.2.2 OSC_CR2 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access SLP_EXTE SYSCLKX2 1,E2h OSC_CR2 PLLGAIN WDR32_SE EXTCLKEN RSVD RW : 00 The Oscillator Control Register 2 (OSC_CR2) is used to Bit 2: EXTCLKEN. - Page 97 Phase-Locked Loop (PLL) CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
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Page 98: Sleep And Watchdog
12. Sleep and Watchdog This chapter discusses the Sleep and Watchdog operations and their associated registers. For a complete table of the Sleep ® and Watchdog registers, refer to the “Summary Table of the Core Registers” on page 36. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 125. -
Page 99: Application Description
Sleep and Watchdog The reset state of the sleep timer is a count value of all Note 3 On wakeup, the instruction immediately after the zeros. There are two ways to reset the sleep timer. Any sleep instruction is executed before the interrupt service rou- hardware reset, (that is, POR, XRES, or Watchdog Reset tine (if enabled). -
Page 100: Register Definitions
Sleep and Watchdog 12.3 Register Definitions The following registers are associated with Sleep and Watchdog and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The bits that are grayed out in the tables below are reserved bits and are not detailed in the register descriptions. -
Page 101: Cpu_Scr1 Register
Sleep and Watchdog 12.3.3 CPU_SCR1 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,FEh CPU_SCR1 IRESS SLIMO ECO EXW ECO EX IRAMDIS # : 00 LEGEND An “x” before the comma in the address field indicates that this register can be read or written to no matter what bank is used. Access is bit specific. -
Page 102: Cpu_Scr0 Register
Sleep and Watchdog 12.3.4 CPU_SCR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,FFh CPU_SCR0 GIES WDRS PORS Sleep STOP # : XX LEGEND X The value for power on reset is unknown. An “x”... -
Page 103: Osc_Cr0 Register
Sleep and Watchdog 12.3.5 OSC_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,E0h OSC_CR0 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed[2:0] RW : 00 The Oscillator Control Register 0 (OSC_CR0) is used to The reset value for the CPU Speed bits is zero;... -
Page 104: Osc_Cr2 Register
Sleep and Watchdog 12.3.6 OSC_CR2 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access SLP_EXTE SYSCLKX2 1,E2h OSC_CR2 PLLGAIN WDR32_SE EXTCLKEN RSVD RW : 00 The Oscillator Control Register 2 (OSC_CR2) is used to Bit 2: EXTCLKEN. -
Page 105: Eco_Tr Register
Sleep and Watchdog 12.3.8 ECO_TR Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,EBh ECO_TR PSSDC[1:0] RW : 00 The External Crystal Oscillator Trim Register (ECO_TR) Bits 7 and 6: PSSDC[1:0]. These bits are used to set the sets the adjustment for the 32.768 kHz external crystal oscil- sleep duty cycle. -
Page 106: Wakeup Sequence
Sleep and Watchdog Figure 12-1. Sleep Sequence On the falling edge of Firmware write to CPU captures CPUCLK, PD is asserted. the SLEEP bit BRQ on next responds The 24/48 MHz system clock causes an with a BRA. CPUCLK edge. is halted;... - Page 107 Sleep and Watchdog Figure 12-2. Wakeup Sequence Interrupt is double sampled by Sleep timer or GPIO CPU is restarted after 32K clock and PD is negated to 75 s (nominal). interrupt occurs. system. CLK32K LVD/PPOR is valid SLEEP BANDGAP LVD/PPOR ENABLE POR/LVD/ BANDGAP...
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Page 108: Bandgap Refresh
Sleep and Watchdog 12.4.3 Bandgap Refresh 12.4.4 Watchdog Timer During normal operation, the bandgap circuit provides a On device boot up, the Watchdog Timer (WDT) is initially voltage reference (VRef) to the system, for use in the analog disabled. The PORS bit in the system control register con- blocks, Flash, and low voltage detect (LVD) circuitry. -
Page 109: Power Consumption
Sleep and Watchdog In practical application, it is important to know that the watchdog timer interval can be anywhere between two and three times the sleep timer interval. The only way to guaran- tee that the WDT interval is a full three times that of the sleep interval is to clear the sleep timer (write 38h) when clearing the WDT register. -
Page 110: Section C: Register Reference
Section C: Register Reference ® The Register Reference section discusses the registers of the PSoC device. It lists all the registers in mapping tables, in address order. For easy reference, each register is linked to the page of a detailed description located in the next chapter. This section encompasses the following chapter: ■... -
Page 111: Cy8C28X03 Register Maps
CY8C28x03 Register Maps Register Map Bank 0 Table: User Space PRT0DR DBC20DR0 RDI2RI PRT0IE DBC20DR1 RDI2SYN PRT0GS DBC20DR2 RDI2IS PRT0DM2 DBC20CR0 RDI2LT0 PRT1DR DBC21DR0 RDI2LT1 PRT1IE DBC21DR1 RDI2RO0 PRT1GS DBC21DR2 RDI2RO1 PRT1DM2 DBC21CR0 RDI2DSM PRT2DR DCC22DR0 PRT2IE DCC22DR1 PRT2GS DCC22DR2 PRT2DM2 DCC22CR0 PRT3DR... -
Page 112: Register Map Bank 1 Table: Configuration Space
Register Map Bank 1 Table: Configuration Space PRT0DM0 DBC20FN RDI2RI PRT0DM1 DBC20IN SADC_TSCMPL RDI2SYN PRT0IC0 DBC20OU SADC_TSCMPH RDI2IS PRT0IC1 DBC20CR1 RDI2LT0 PRT1DM0 DBC21FN RDI2LT1 PRT1DM1 DBC21IN RDI2RO0 PRT1IC0 DBC21OU RDI2RO1 PRT1IC1 DBC21CR1 RDI2DSM PRT2DM0 DCC22FN PRT2DM1 DCC22IN PRT2IC0 DCC22OU PRT2IC1 DCC22CR1 PRT3DM0 DCC23FN... -
Page 113: Cy8C28X13 Register Maps
CY8C28x13 Register Maps Register Map Bank 0 Table: User Space PRT0DR DBC20DR0 RDI2RI PRT0IE DBC20DR1 RDI2SYN PRT0GS DBC20DR2 RDI2IS PRT0DM2 DBC20CR0 RDI2LT0 PRT1DR DBC21DR0 RDI2LT1 PRT1IE DBC21DR1 RDI2RO0 PRT1GS DBC21DR2 RDI2RO1 PRT1DM2 DBC21CR0 RDI2DSM PRT2DR DCC22DR0 PRT2IE DCC22DR1 PRT2GS DCC22DR2 PRT2DM2 DCC22CR0 PRT3DR... -
Page 114: Register Map Bank 1 Table: Configuration Space
Register Map Bank 1 Table: Configuration Space PRT0DM0 DBC20FN RDI2RI PRT0DM1 DBC20IN SADC_TSCMPL RDI2SYN PRT0IC0 DBC20OU SADC_TSCMPH RDI2IS PRT0IC1 DBC20CR1 ACE_AMD_CR1 RDI2LT0 PRT1DM0 DBC21FN RDI2LT1 PRT1DM1 DBC21IN ACE_PWM_CR RDI2RO0 PRT1IC0 DBC21OU ACE_ADC0_CR RDI2RO1 PRT1IC1 DBC21CR1 ACE_ADC1_CR RDI2DSM PRT2DM0 DCC22FN PRT2DM1 DCC22IN ACE_CLK_CR0 PRT2IC0... -
Page 115: Cy8C28X23 Register Maps
CY8C28x23 Register Maps Register Map Bank 0 Table: User Space PRT0DR DBC20DR0 ASC10CR0 RDI2RI PRT0IE DBC20DR1 ASC10CR1 RDI2SYN PRT0GS DBC20DR2 ASC10CR2 RDI2IS PRT0DM2 DBC20CR0 ASC10CR3 RDI2LT0 PRT1DR DBC21DR0 ASD11CR0 RDI2LT1 PRT1IE DBC21DR1 ASD11CR1 RDI2RO0 PRT1GS DBC21DR2 ASD11CR2 RDI2RO1 PRT1DM2 DBC21CR0 ASD11CR3 RDI2DSM PRT2DR... -
Page 116: Register Map Bank 1 Table: Configuration Space
Register Map Bank 1 Table: Configuration Space PRT0DM0 DBC20FN RDI2RI PRT0DM1 DBC20IN RDI2SYN PRT0IC0 DBC20OU RDI2IS PRT0IC1 DBC20CR1 RDI2LT0 PRT1DM0 DBC21FN RDI2LT1 PRT1DM1 DBC21IN RDI2RO0 PRT1IC0 DBC21OU RDI2RO1 PRT1IC1 DBC21CR1 RDI2DSM PRT2DM0 DCC22FN PRT2DM1 DCC22IN PRT2IC0 DCC22OU PRT2IC1 DCC22CR1 PRT3DM0 DCC23FN PRT3DM1 DCC23IN... -
Page 117: Cy8C28X33 Register Maps
CY8C28x33 Register Maps Register Map Bank 0 Table: User Space PRT0DR DBC20DR0 ASC10CR0 RDI2RI PRT0IE DBC20DR1 ASC10CR1 RDI2SYN PRT0GS DBC20DR2 ASC10CR2 RDI2IS PRT0DM2 DBC20CR0 ASC10CR3 RDI2LT0 PRT1DR DBC21DR0 ASD11CR0 RDI2LT1 PRT1IE DBC21DR1 ASD11CR1 RDI2RO0 PRT1GS DBC21DR2 ASD11CR2 RDI2RO1 PRT1DM2 DBC21CR0 ASD11CR3 RDI2DSM PRT2DR... -
Page 118: Register Map Bank 1 Table: Configuration Space
Register Map Bank 1 Table: Configuration Space PRT0DM0 DBC20FN RDI2RI PRT0DM1 DBC20IN SADC_TSCMPL RDI2SYN PRT0IC0 DBC20OU SADC_TSCMPH RDI2IS PRT0IC1 DBC20CR1 ACE_AMD_CR1 RDI2LT0 PRT1DM0 DBC21FN RDI2LT1 PRT1DM1 DBC21IN ACE_PWM_CR RDI2RO0 PRT1IC0 DBC21OU ACE_ADC0_CR RDI2RO1 PRT1IC1 DBC21CR1 ACE_ADC1_CR RDI2DSM PRT2DM0 DCC22FN PRT2DM1 DCC22IN ACE_CLK_CR0 PRT2IC0... -
Page 119: Cy8C28X43 Register Maps
CY8C28x43 Register Maps Register Map Bank 0 Table: User Space PRT0DR DBC20DR0 ASC10CR0 RDI2RI PRT0IE DBC20DR1 ASC10CR1 RDI2SYN PRT0GS DBC20DR2 ASC10CR2 RDI2IS PRT0DM2 DBC20CR0 ASC10CR3 RDI2LT0 PRT1DR DBC21DR0 ASD11CR0 RDI2LT1 PRT1IE DBC21DR1 ASD11CR1 RDI2RO0 PRT1GS DBC21DR2 ASD11CR2 RDI2RO1 PRT1DM2 DBC21CR0 ASD11CR3 RDI2DSM PRT2DR... -
Page 120: Register Map Bank 1 Table: Configuration Space
Register Map Bank 1 Table: Configuration Space PRT0DM0 DBC20FN RDI2RI PRT0DM1 DBC20IN SADC_TSCMPL RDI2SYN PRT0IC0 DBC20OU SADC_TSCMPH RDI2IS PRT0IC1 DBC20CR1 RDI2LT0 PRT1DM0 DBC21FN RDI2LT1 PRT1DM1 DBC21IN RDI2RO0 PRT1IC0 DBC21OU RDI2RO1 PRT1IC1 DBC21CR1 RDI2DSM PRT2DM0 DCC22FN PRT2DM1 DCC22IN PRT2IC0 DCC22OU PRT2IC1 DCC22CR1 PRT3DM0 DCC23FN... -
Page 121: Cy8C28X45 Register Maps
CY8C28x45 Register Maps Register Map Bank 0 Table: User Space PRT0DR DBC20DR0 ASC10CR0 RDI2RI PRT0IE DBC20DR1 ASC10CR1 RDI2SYN PRT0GS DBC20DR2 ASC10CR2 RDI2IS PRT0DM2 DBC20CR0 ASC10CR3 RDI2LT0 PRT1DR DBC21DR0 ASD11CR0 RDI2LT1 PRT1IE DBC21DR1 ASD11CR1 RDI2RO0 PRT1GS DBC21DR2 ASD11CR2 RDI2RO1 PRT1DM2 DBC21CR0 ASD11CR3 RDI2DSM PRT2DR... -
Page 122: Register Map Bank 1 Table: Configuration Space
Register Map Bank 1 Table: Configuration Space PRT0DM0 DBC20FN RDI2RI PRT0DM1 DBC20IN SADC_TSCMPL RDI2SYN PRT0IC0 DBC20OU SADC_TSCMPH RDI2IS PRT0IC1 DBC20CR1 ACE_AMD_CR1 RDI2LT0 PRT1DM0 DBC21FN RDI2LT1 PRT1DM1 DBC21IN ACE_PWM_CR RDI2RO0 PRT1IC0 DBC21OU ACE_ADC0_CR RDI2RO1 PRT1IC1 DBC21CR1 ACE_ADC1_CR RDI2DSM PRT2DM0 DCC22FN PRT2DM1 DCC22IN ACE_CLK_CR0 PRT2IC0... -
Page 123: Cy8C28X52 Register Maps
CY8C28x52 Register Maps Register Map Bank 0 Table: User Space PRT0DR ASC10CR0 PRT0IE ASC10CR1 PRT0GS ASC10CR2 PRT0DM2 ASC10CR3 PRT1DR ASD11CR0 PRT1IE ASD11CR1 PRT1GS ASD11CR2 PRT1DM2 ASD11CR3 PRT2DR ASC12CR0 PRT2IE ASC12CR1 PRT2GS ASC12CR2 PRT2DM2 ASC12CR3 PRT3DR ASD13CR0 PRT3IE ASD13CR1 PRT3GS ASD13CR2 PRT3DM2 ASD13CR3 PRT4DR... -
Page 124: Register Map Bank 1 Table: Configuration Space
Register Map Bank 1 Table: Configuration Space PRT0DM0 DBC20FN RDI2RI PRT0DM1 DBC20IN SADC_TSCMPL RDI2SYN PRT0IC0 DBC20OU SADC_TSCMPH RDI2IS PRT0IC1 DBC20CR1 ACE_AMD_CR1 RDI2LT0 PRT1DM0 DBC21FN RDI2LT1 PRT1DM1 DBC21IN ACE_PWM_CR RDI2RO0 PRT1IC0 DBC21OU ACE_ADC0_CR RDI2RO1 PRT1IC1 DBC21CR1 ACE_ADC1_CR RDI2DSM PRT2DM0 DCC22FN PRT2DM1 DCC22IN ACE_CLK_CR0 PRT2IC0... - Page 125 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
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Page 126: Register Details
13. Register Details ® This chapter is a reference for all the PSoC device registers in address order, for Bank 0 and Bank 1. The most detailed descriptions of the PSoC registers are in the Register Definitions section of each chapter. The registers that are in both banks are incorporated with the Bank 0 registers, designated with an ‘x’, rather than a ‘0’... -
Page 127: Register Conventions
Register Details Use the register tables, in addition to the detailed register bit descriptions, to determine which bits are reserved for some smaller PSoC devices. Reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. -
Page 128: Bank 0 Registers
Register Details 13.2 Bank 0 Registers The following registers are all in bank 0 and are listed in address order. An ‘x’ before the comma in the register’s address indi- cates that the register can be accessed independent of the XIO bit in the CPU_F register. Registers that are in both Bank 0 and Bank 1 are listed in address order in Bank 0. -
Page 129: Prtxie
PRTxIE 0,01h 13.2.2 PRTxIE Port Interrupt Enable Register Individual Register Names and Addresses: 0,01h PRT0IE : 0,01h PRT1IE : 0,05h PRT2IE : 0,09h PRT3IE : 0,0Dh PRT4IE : 0,11h PRT5IE : 0,15h Access : POR RW : 00 Bit Name Interrupt Enables[7:0] This register is used to enable or disable the interrupt enable internal to the GPIO block. -
Page 130: Prtxgs
PRTxGS 0,02h 13.2.3 PRTxGS Port Global Select Register Individual Register Names and Addresses: 0,02h PRT0GS : 0,02h PRT1GS : 0,06h PRT2GS : 0,0Ah PRT3GS : 0,0Eh PRT4GS : 0,12h PRT5GS : 0,16h Access : POR RW : 00 Bit Name Global Select[7:0] This register is used to select the block for connection to global inputs or outputs. -
Page 131: Prtxdm2
PRTxDM2 0,03h 13.2.4 PRTxDM2 Port Drive Mode Bit 2 Register Individual Register Names and Addresses: 0,03h PRT0DM2 : 0,03h PRT1DM2 : 0,07h PRT2DM2 : 0,0Bh PRT3DM2 : 0,0Fh PRT4DM2 : 0,13h PRT5DM2 : 0,17h Access : POR RW : FFh Bit Name Drive Mode 2[7:0] This register is one of three registers whose combined value determines the unique Drive mode of each bit in a GPIO port. -
Page 132: Dxcxxdr0
DxCxxDR0 0,20h 13.2.5 DxCxxDR0 Digital Basic/Communication Type C Block Data Register 0 Individual Register Names and Addresses: 0,20h DBC00DR0 : 0,20h DBC01DR0 : 0,24h DCC02DR0 : 0,28h DCC03DR0 : 0,2Ch DBC10DR0 : 0,30h DBC11DR0 : 0,34h DCC12DR0 : 0,38h DCC13DR0 : 0,3Ch DBC20DR0 : 0,40h DBC21DR0 : 0,44h DCC22DR0 : 0,48h... -
Page 133: Dxcxxdr1
DxCxxDR1 0,21h 13.2.6 DxCxxDR1 Digital Basic/Communication Type C Block Data Register 1 Individual Register Names and Addresses: 0,21h DBC00DR1 : 0,21h DBC01DR1 : 0,25h DCC02DR1 : 0,29h DCC03DR1 : 0,2Dh DBC10DR1 : 0,31h DBC11DR1 : 0,35h DCC12DR1 : 0,39h DCC13DR1 : 0,3Dh DBC20DR1 : 0,41h DBC21DR1 : 0,45h DCC22DR1 : 0,49h... -
Page 134: Dxcxxdr2
DxCxxDR2 0,22h 13.2.7 DxCxxDR2 Digital Basic/Communication Type C Block Data Register 2 Individual Register Names and Addresses: 0,22h DBC00DR2 : 0,22h DBC01DR2 : 0,26h DCC02DR2 : 0,2Ah DCC03DR2 : 0,2Eh DBC10DR2 : 0,32h DBC11DR2 : 0,36h DCC12DR2 : 0,3Ah DCC13DR2 : 0,3Eh DBC20DR2 : 0,42h DBC21DR2 : 0,46h DCC22DR2 : 0,4Ah... -
Page 135: Dxcxxcr0 (Timer Control:000)
DxCxxCR0 (Timer Control:000) 0,23h 13.2.8 DxCxxCR0 (Timer Control:000) Digital Basic/Communication Type C Block Control Register 0 Individual Register Names and Addresses: 0,23h DBC00CR0 : 0,23h DBC01CR0 : 0,27h DCC02CR0 : 0,2Bh DCC03CR0 : 0,2Fh DBC10CR0 : 0,33h DBC11CR0 : 0,37h DCC12CR0 : 0,3Bh DCC13CR0 : 0,3Fh DBC20CR0 : 0,43h... -
Page 136: Dxcxxcr0 (Counter Control:001)
DxCxxCR0 (Counter Control:001) 0,23h 13.2.9 DxCxxCR0 (Counter Control:001) Digital Basic/Communication Type C Block Control Register 0 Individual Register Names and Addresses: 0,23h DBC00CR0: 0,23h DBC01CR0: 0,27h DCC02CR0: 0,2Bh DCC03CR0: 0,2Fh DBC10CR0: 0,33h DBC11CR0: 0,37h DCC12CR0: 0,3Bh DCC13CR0: 0,3Fh DBC20CR0: 0,43h DBC21CR0: 0,47h DCC22CR0: 0,4Bh DCC23CR0: 0,4Fh... -
Page 137: Dxcxxcr0 (Dead Band Control:100)
DxCxxCR0 (Dead Band Control:100) 0,23h 13.2.10 DxCxxCR0 (Dead Band Control:100) Digital Basic/Communication Type C Block Control Register 0 Individual Register Names and Addresses: 0,23h DBC00CR0: 0,23h DBC01CR0: 0,27h DCC02CR0: 0,2Bh DCC03CR0: 0,2Fh DBC10CR0: 0,33h DBC11CR0: 0,37h DCC12CR0: 0,3Bh DCC13CR0: 0,3Fh DBC20CR0: 0,43h DBC21CR0: 0,47h DCC22CR0: 0,4Bh... -
Page 138: Dxcxxcr0 (Crcprs Control:010)
DxCxxCR0 (CRCPRS Control:010) 0,23h 13.2.11 DxCxxCR0 (CRCPRS Control:010) Digital Basic/Communication Type C Block Control Register 0 Individual Register Names and Addresses: 0,23h DBC00CR0: 0,23h DBC01CR0: 0,27h DCC02CR0: 0,2Bh DCC03CR0: 0,2Fh DBC10CR0: 0,33h DBC11CR0: 0,37h DCC12CR0: 0,3Bh DCC13CR0: 0,3Fh DBC20CR0: 0,43h DBC21CR0: 0,47h DCC22CR0: 0,4Bh DCC23CR0: 0,4Fh... -
Page 139: Dxcxxcr0 (Pwmdbl Control:011)
DxCxxCR0 (PWMDBL Control:011) 0,23h 13.2.12 DxCxxCR0 (PWMDBL Control:011) Digital Basic/Communication Type C Block Control Register 0 Individual Register Names and Addresses: 0,23h DBC00CR0: 0,23h DBC01CR0: 0,27h DCC02CR0: 0,2Bh DCC03CR0: 0,2Fh DBC10CR0: 0,33h DBC11CR0: 0,37h DCC12CR0: 0,3Bh DCC13CR0: 0,3Fh DBC20CR0: 0,43h DBC21CR0: 0,47h DCC22CR0: 0,4Bh DCC23CR0: 0,4Fh... - Page 140 DxCxxCR0 (PWMDBL Control:011) 0,23h 13.2.12 DxCxxCR0 (PWMDBL Control:011) (continued) Disables software trigger mode. Enables software trigger mode. If SWT is set to ‘1’, writing Enable (bit 0) to ‘1’ software will start PPG mode. If SWT is cleared to ‘0’, PWMDBL will wait for the rising edge of START to trigger PPG.
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Page 141: Dccxxcr0 (Spim Control:0-110)
DCCxxCR0 (SPIM Control:0-110) 0,2Bh 13.2.13 DCCxxCR0 (SPIM Control:0-110) Digital Communication Type C Block Control Register 0 Individual Register Names and Addresses: 0,2Bh DCC02CR0: 0,2Bh DCC03CR0: 0,2Fh DCC12CR0: 0,3Bh DCC13CR0: 0,3Fh DCC22CR0: 0,4Bh DCC23CR0: 0,4Fh Access : POR RW : 0 R : 0 R : 0 R : 1... -
Page 142: Dccxxcr0 (Spis Control:1-110)
DCCxxCR0 (SPIS Control:1-110) 0,2Bh 13.2.14 DCCxxCR0 (SPIS Control:1-110) Digital Basic/Communication Type C Block Control Register 0 Individual Register Names and Addresses: 0,2Bh DCC02CR0: 0,2Bh DCC03CR0: 0,2Fh DCC12CR0: 0,3Bh DCC13CR0: 0,3Fh DCC22CR0: 0,4Bh DCC23CR0: 0,4Fh Access : POR RW : 0 R : 0 R : 0 R : 1... -
Page 143: Dxcxxcr0 (Dsm Control:111)
DxCxxCR0 (DSM Control:111) 0,23h 13.2.15 DxCxxCR0 (DSM Control:111) Digital Basic/Communication Type C Block Control Register 0 Individual Register Names and Addresses: 0,23h DBC00CR0: 0,23h DBC01CR0: 0,27h DCC02CR0: 0,2Bh DCC03CR0: 0,2Fh DBC10CR0: 0,33h DBC11CR0: 0,37h DCC12CR0: 0,3Bh DCC13CR0: 0,3Fh DBC20CR0: 0,43h DBC21CR0: 0,47h DCC22CR0: 0,4Bh DCC23CR0: 0,4Fh... -
Page 144: Dccxxcr0 (Uart Transmitter Control)
DCCxxCR0 (UART Transmitter Control) 0,2Bh 13.2.16 DCCxxCR0 (UART Transmitter Control) Digital Basic/Communication Type C Block Control Register 0 Individual Register Names and Addresses: 0,2Bh DCC02CR0: 0,2Bh DCC03CR0: 0,2Fh DCC12CR0: 0,3Bh DCC13CR0: 0,3Fh DCC22CR0: 0,4Bh DCC23CR0: 0,4Fh Access : POR R : 0 R : 1 RW : 0 RW : 0... -
Page 145: Dccxxcr0 (Uart Receiver Control)
DCCxxCR0 (UART Receiver Control) 0,2Bh 13.2.17 DCCxxCR0 (UART Receiver Control) Digital Basic/Communication Type C Block Control Register 0 Individual Register Names and Addresses: 0,2Bh DCC02CR0: 0,2Bh DCC03CR0: 0,2Fh DCC12CR0: 0,3Bh DCC13CR0: 0,3Fh DCC22CR0: 0,4Bh DCC23CR0: 0,4Fh Access : POR R : 0 R : 0 R : 0 R : 0... -
Page 146: Amx_In
AMX_IN 0,60h 13.2.18 AMX_IN Analog Input Select Register Individual Register Names and Addresses: 0,60h AMX_IN: 0,60h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name ACI3[1:0] ACI2[1:0] ACI1[1:0] ACI0[1:0] This register controls the analog muxes that feed signals in from port pins into the analog column. For additional information, refer to the “Register Definitions”... -
Page 147: Amux_Cfg
AMUX_CFG 0,61h 13.2.19 AMUX_CFG Analog Mux Configuration Register Individual Register Names and Addresses: 0,61h AMUX_CFG : 0,61h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name ABusMux1 ABusMux0 INTCAP[1:0] MUXCLK0[2:0] This register is used to configure the clocked pre-charge mode of the analog multiplexer system. -
Page 148: Clk_Cr3
CLK_CR3 0,62h 13.2.20 CLK_CR3 Analog Clock Source Control Register 3 Individual Register Names and Addresses: 0,62h CLK_CR3: 0,62h Access : POR RW : 0 Bit Name SYSDIR[3:0] The Analog Clock Source Control Register 3 (CLK_CR3) is used to select the clock source for an individual analog column. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. -
Page 149: Arf_Cr
ARF_CR 0,63h 13.2.21 ARF_CR Analog Reference Control Register Individual Register Names and Addresses: 0,63h ARF_CR: 0,63h Access : POR RW : 0 RW : 0 RW : 0 Bit Name REF[2:0] PWR[2:0] This register is used to configure various features of the configurable analog references. In the table, note that the reserved bit is a gray table cell and is not described in the bit description section. -
Page 150: Cmp_Cr0
CMP_CR0 0,64h 13.2.22 CMP_CR0 Analog Comparator Bus Control Register 0 Individual Register Names and Addresses: 0,64h CMP_CR0: 0,64h Access : POR R : 0 RW : 0 Bit Name COMP[3:0] AINT[3:0] This register is used to poll the analog column comparator bus states and select column interrupts. For additional information, see “Register Definitions”... -
Page 151: Asy_Cr
ASY_CR 0,65h 13.2.23 ASY_CR Analog Synchronization Control Register Individual Register Names and Addresses: 0,65h ASY_CR: 0,65h 4, 2 COLUMN Access : POR W : 0 RW : 0 RW : 0 RW : 0 Bit Name SARCNT[2:0] SARSIGN SARCOL[1:0] SYNCEN This register is used to control SAR operation, except for the SYNCEN bit which is associated with analog register write stall- ing. -
Page 152: Cmp_Cr1
CMP_CR1 0,66h 13.2.24 CMP_CR1 Analog Comparator Bus Control Register 1 Individual Register Names and Addresses: 0,66h CMP_CR1: 0,66h 4 COLUMN Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name... - Page 153 CMP_CR1 0,66h 13.2.24 CMP_CR1 (continued) CLK1X[0] Controls the digital comparator bus 0 synchronization clock. Comparator bit is synchronized by rising edge of PHI2. Comparator bit is synchronized directly by selected column clock. (This clock is not divided by 4.) CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
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Page 154: Sadc_Dh
SADC_DH 0,6Ah 13.2.25 SADC_DH SAR ADC Data High Register Individual Register Names and Addresses: 0,6Ah SADC_DH : 0,6Ah Access : POR R : 00 Bit Name Data High [7:0] The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45 PSoC devices. -
Page 155: Sadc_Dl
SADC_DL 0,6Bh 13.2.26 SADC_DL SAR ADC Data Low Register Individual Register Names and Addresses: 0,6Bh SADC_DL : 0,6Bh Access : POR R : 00 Bit Name Data Low [7:0] The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45 PSoC devices. -
Page 156: Tmp_Drx
TMP_DRx x,6Ch 13.2.27 TMP_DRx Temporary Data Register Individual Register Names and Addresses: x,6Ch TMP_DR0 : x,6Ch TMP_DR1 : x,6Dh TMP_DR2 : x,6Eh TMP_DR3 : x,6Fh Access : POR RW : 00 Bit Name Data[7:0] This register is used to enhance the performance in multiple SRAM page PSoC devices. For additional information, refer to the “Register Definitions”... -
Page 157: Accxxcr3
ACCxxCR3 0,70h 13.2.28 ACCxxCR3 Analog Continuous Time Type C Block Control Register 3 Individual Register Names and Addresses: 0,70h ACC00CR3 : 0,70h ACC01CR3 : 0,74h ACC02CR3 : 0,78h ACC03CR3 : 0,7Ch Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0... -
Page 158: Accxxcr0
ACCxxCR0 0,71h 13.2.29 ACCxxCR0 Analog Continuous Time Type C Block Control Register 0 Individual Register Names and Addresses: 0,71h ACC00CR0 : 0,71h ACC01CR0 : 0,75h ACC02CR0 : 0,79h ACC03CR0 : 0,7Dh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name... - Page 159 ACCxxCR0 0,71h 13.2.29 ACCxxCR0 (continued) RBotMux[1:0] Encoding for feedback resistor select. Bits [1:0] are overridden if bit 1 of the ACCxxCR3 register is set. In that case, the bottom of the resistor string is connected across columns. Note that available mux inputs vary by individual PSoC block.
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Page 160: Accxxcr1
ACCxxCR1 0,72h 13.2.30 ACCxxCR1 Analog Continuous Time Type C Block Control Register 1 Individual Register Names and Addresses: 0,72h ACC00CR1 : 0,72h ACC01CR1 : 0,76h ACC02CR1 : 0,7Ah ACC03CR1 : 0,7Eh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name... -
Page 161: Accxxcr2
ACCxxCR2 0,73h 13.2.31 ACCxxCR2 Analog Continuous Time Type C Block Control Register 2 Individual Register Names and Addresses: 0,73h ACC00CR2 : 0,73h ACC01CR2 : 0,77h ACC02CR2 : 0,7Bh ACC03CR2 : 0,7Fh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0... -
Page 162: Ascxxcr0
ASCxxCR0 0,80h 13.2.32 ASCxxCR0 Analog Switch Cap Type C Block Control Register 0 Individual Register Names and Addresses: 0,80h ASC10CR0 : 0,80h ASC12CR0 : 0,88h ASC21CR0 : 0,94h ASC23CR0 : 0,9Ch Access : POR RW : 0 RW : 0 RW : 0 RW : 00 Bit Name... -
Page 163: Ascxxcr1
ASCxxCR1 0,81h 13.2.33 ASCxxCR1 Analog Switch Cap Type C Block Control Register 1 Individual Register Names and Addresses: 0,81h ASC10CR1 : 0,81h ASC12CR1 : 0,89h ASC21CR1 : 0,95h ASC23CR1 : 0,9Dh Access : POR RW : 0 RW : 00 Bit Name ACMux[2:0] BCap[4:0]... -
Page 164: Ascxxcr2
ASCxxCR2 0,82h 13.2.34 ASCxxCR2 Analog Switch Cap Type C Block Control Register 2 Individual Register Names and Addresses: 0,82h ASC10CR2 : 0,82h ASC12CR2 : 0,8Ah ASC21CR2 : 0,96h ASC23CR2 : 0,9Eh Access : POR RW : 0 RW : 0 RW : 0 RW : 00 Bit Name... -
Page 165: Ascxxcr3
ASCxxCR3 0,83h 13.2.35 ASCxxCR3 Analog Switch Cap Type C Block Control Register 3 Individual Register Names and Addresses: 0,83h ASC10CR3 : 0,83h ASC12CR3 : 0,8Bh ASC21CR3 : 0,97h ASC23CR3 : 0,9Fh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0... -
Page 166: Asdxxcr0
ASDxxCR0 0,84h 13.2.36 ASDxxCR0 Analog Switch Cap Type D Block Control Register 0 Individual Register Names and Addresses: 0,84h ASD11CR0 : 0,84h ASD13CR0 : 0,8Ch ASD20CR0 : 0,90h ASD22CR0 : 0,98h Access : POR RW : 0 RW : 0 RW : 0 RW : 00 Bit Name... -
Page 167: Asdxxcr1
ASDxxCR1 0,85h 13.2.37 ASDxxCR1 Analog Switch Cap Type D Block Control Register 1 Individual Register Names and Addresses: 0,85h ASD11CR1 : 0,85h ASD13CR1 : 0,8Dh ASD20CR1 : 0,91h ASD22CR1 : 0,99h Access : POR RW : 0 RW : 00 Bit Name AMux[2:0] BCap[4:0]... -
Page 168: Asdxxcr2
ASDxxCR2 0,86h 13.2.38 ASDxxCR2 Analog Switch Cap Type D Block Control Register 2 Individual Register Names and Addresses: 0,86h ASD11CR2 : 0,86h ASD13CR2 : 0,8Eh ASD20CR2 : 0,92h ASD22CR2 : 0,9Ah Access : POR RW : 0 RW : 0 RW : 0 RW : 00 Bit Name... -
Page 169: Asdxxcr3
ASDxxCR3 0,87h 13.2.39 ASDxxCR3 Analog Switch Cap Type D Block Control Register 3 Individual Register Names and Addresses: 0,87h ASD11CR3 : 0,87h ASD13CR3 : 0,8Fh ASD20CR3 : 0,93h ASD22CR3 : 0,9Bh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0... -
Page 170: Decx_Dh
DECx_DH 0,A0h 13.2.40 DECx_DH Decimator Data High Register Individual Register Names and Addresses: 0,A0h DEC0_DH : 0,A0h DEC1_DH : 0,A2h DEC2_DH : 0,A4h DEC3_DH : 0,A6h Access : POR RC : XX Bit Name Data High Byte[7:0] This register is a dual purpose register and is used to read the high byte of the decimator’s output or clear the decimator. Note that the CY8C28x03 does not have a decimator, and that the CY8C28x13 and CY8C28x23 only have two decimators. -
Page 171: Decx_Dl
DECx_DL 0,A1h 13.2.41 DECx_DL Decimator Data Low Register Individual Register Names and Addresses: 0,A1h DEC0_DL : 0,A1h DEC1_DL : 0,A3h DEC2_DL : 0,A5h DEC3_DL : 0,A7h Access : POR RC : XX Bit Name Data Low Byte[7:0] This register is a dual purpose register and is used to read the low byte of the decimator’s output or clear the decimator. When a hardware reset occurs, the internal state of the Decimator is reset, but the output data registers (DECx_DH and DECx_DL) are not. -
Page 172: Mulx_X
MULx_X 0,A8h 13.2.42 MULx_X Multiply Input X Register Individual Register Names and Addresses: 0,A8h MUL1_X : 0,A8h MUL0_X : 0,E8h Access : POR W : XX Bit Name Data[7:0] This register is one of two multiplicand registers for the signed 8-bit multiplier in the PSoC MAC. This register is for 2 MAC block PSoC devices only. -
Page 173: Mulx_Y
MULx_Y 0,A9h 13.2.43 MULx_Y Multiply Input Y Register Individual Register Names and Addresses: 0,A9h MUL1_Y : 0,A9h MUL0_Y : 0,E9h Access : POR W : XX Bit Name Data[7:0] This register is one of two multiplicand registers for the signed 8-bit multiplier in the PSoC MAC. This register is for 2 MAC block PSoC devices only. -
Page 174: Mulx_Dh
MULx_DH 0,AAh 13.2.44 MULx_DH Multiply Result High Byte Register Individual Register Names and Addresses: 0,AAh MUL1_DH : 0,AAh MUL0_DH : 0,EAh Access : POR R : XX Bit Name Data[7:0] This register holds the most significant byte of the 16-bit product. This register is for 2 MAC block PSoC devices only. -
Page 175: Mulx_Dl
MULx_DL 0,ABh 13.2.45 MULx_DL Multiply Result Low Byte Register Individual Register Names and Addresses: 0,ABh MUL1_DL : 0,ABh MUL0_DL : 0,EBh Access : POR R : XX Bit Name Data[7:0] This register holds the least significant byte of the 16-bit product. This register is for 2 MAC block PSoC devices only. -
Page 176: Macx_X/Accx_Dr1
MACx_X/ACCx_DR1 0,ACh 13.2.46 MACx_X/ACCx_DR1 Accumulator Data Register 1 Individual Register Names and Addresses: 0,ACh MAC1_X/ACC1_DR1 : 0,ACh MAC0_X/ACC0_DR1 : 0,ECh Access : POR RW : 00 Bit Name Data[7:0] This is the multiply accumulate X register and the second byte of the accumulated value. This register is only for PSoC devices with two MAC blocks. -
Page 177: Macx_Y/Accx_Dr0
MACx_Y/ACCx_DR0 0,ADh 13.2.47 MACx_Y/ACCx_DR0 Accumulator Data Register 0 Individual Register Names and Addresses: 0,ADh MAC1_Y/ACC1_DR0 : 0,ADh MAC0_Y/ACC0_DR0 : 0,EDh Access : POR RW : 00 Bit Name Data[7:0] This is the multiply accumulate Y register and the first byte of the accumulated value. This register is only for PSoC devices with two MAC blocks.For additional information, refer to the “Register Definitions”... -
Page 178: Macx_Cl0/Accx_Dr3
MACx_CL0/ACCx_DR3 0,AEh 13.2.48 MACx_CL0/ACCx_DR3 Accumulator Data Register 3 Individual Register Names and Addresses: 0,AEh MAC1_CL0/ACC1_DR3 : 0,AEh MAC0_CL0/ACC0_DR3 : 0,EEh Access : POR RW : 00 Bit Name Data[7:0] This is an accumulator clear register and the fourth byte of the accumulated value. This register is for 2 MAC block PSoC devices only. -
Page 179: Macx_Cl1/Accx_Dr2
MACx_CL1/ACCx_DR2 0,AFh 13.2.49 MACx_CL1/ACCx_DR2 Accumulator Data Register 2 Individual Register Names and Addresses: 0,AFh MAC1_CL1/ACC1_DR2 : 0,AFh MAC0_CL1/ACC0_DR2 : 0,EFh Access : POR RW : 00 Bit Name Data[7:0] This is an accumulator clear register and the third byte of the accumulated value. This register is only for PSoC devices with two MAC blocks. -
Page 180: Rdixri
RDIxRI x,B0h 13.2.50 RDIxRI Row Digital Interconnect Row Input Register Individual Register Names and Addresses: x,B0h RDI0RI : x,B0h RDI1RI : x,B8h RDI2RI : x,C0h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name RI3[1:0] RI2[1:0]... -
Page 181: Rdixsyn
RDIxSYN x,B1h 13.2.51 RDIxSYN Row Digital Interconnect Synchronization Register Individual Register Names and Addresses: x,B1h RDI0SYN : x,B1h RDI1SYN : x,B9h RDI2SYN : x,C1h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name RI3SYN RI2SYN RI1SYN... -
Page 182: Rdixis
RDIxIS x,B2h 13.2.52 RDIxIS Row Digital Interconnect Input Select Register Individual Register Names and Addresses: x,B2h RDI0IS : x,B2h RDI1IS : x,BAh RDI2IS : x,C2h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name BCSEL[1:0]... -
Page 183: Rdixlt0
RDIxLT0 x,B3h 13.2.53 RDIxLT0 Row Digital Interconnect Logic Table Register 0 Individual Register Names and Addresses: x,B3h RDI0LT0 : x,B3h RDI1LT0 : x,BBh RDI2LT0 : x,C3h Access : POR RW : 0 RW : 0 Bit Name LUT1[3:0] LUT0[3:0] This register is used to select the logic function of the digital row LUTS. The ‘x’... - Page 184 RDIxLT0 x,B3h RDIxLT0 13.2.53 (continued) LUT0[3:0] Select logic function for LUT0. Function 0000b FALSE 0001b A AND B 0010b A AND B 0011b 0100b A AND B 0101b 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b...
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Page 185: Rdixlt1
RDIxLT1 x,B4h 13.2.54 RDIxLT1 Row Digital Interconnect Logic Table Register 1 Individual Register Names and Addresses: x,B4h RDI0LT1 : x,B4h RDI1LT1 : x,BCh RDI2LT1 : x,C4h Access : POR RW : 0 RW : 0 Bit Name LUT3[3:0] LUT2[3:0] This register is used to select the logic function of the digital row LUTS. The ‘x’... - Page 186 RDIxLT1 x,B4h RDIxLT1 13.2.54 (continued) LUT2[3:0] Select logic function for LUT2. Function 0000b FALSE 0001b A AND B 0010b A AND B 0011b 0100b A AND B 0101b 0110b A XOR B 0111b A OR B 1000b A NOR B 1001b A XNOR B 1010b...
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Page 187: Rdixro0
RDIxRO0 x,B5h 13.2.55 RDIxRO0 Row Digital Interconnect Row Output Register 0 Individual Register Names and Addresses: x,B5h RDI0RO0 : x,B5h RDI1RO0 : x,BDh RDI2RO0 : x,C5h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0... -
Page 188: Rdixro1
RDIxRO1 x,B6h 13.2.56 RDIxRO1 Row Digital Interconnect Row Output Register 1 Individual Register Names and Addresses: x,B6h RDI0RO1 : x,B6h RDI1RO1 : x,BEh RDI2RO1 : x,C6h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0... -
Page 189: Rdixdsm
RDIxDSM x,B7h 13.2.57 RDIxDSM Row Digital Interconnect Delta Sigma Modulator Function Select Register Individual Register Names and Addresses: x,B7h RDI0DSM : x,B7h RDI1DSM : x,BFh RDI2DSM : x,C7h Access : POR RW : 0000 RW : 0000 Bit Name AVG_SEL[3:0] AVG_EN[3:0] The Row Digital Interconnect Delta Sigma Modulator Register (RDIxDSM) is used to select the Delta Sigma Modulator func- tion on the row outputs. -
Page 190: Cur_Pp
CUR_PP 0,D0h 13.2.58 CUR_PP Current Page Pointer Register Individual Register Names and Addresses: 0,D0h CUR_PP: 0,D0h Access : POR RW : 0 Bit Name Page Bits[2:0] This register is used to set the effective SRAM page for normal memory accesses in a multi-SRAM page PSoC device. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. -
Page 191: Stk_Pp
STK_PP 0,D1h 13.2.59 STK_PP Stack Page Pointer Register Individual Register Names and Addresses: 0,D1h STK_PP: 0,D1h Access : POR RW : 0 Bit Name Page Bits[2:0] This register is used to set the effective SRAM page for stack memory accesses in a multi-SRAM page PSoC device. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. -
Page 192: Idx_Pp
IDX_PP 0,D3h 13.2.60 IDX_PP Indexed Memory Access Page Pointer Register Individual Register Names and Addresses: 0,D3h IDX_PP: 0,D3h Access : POR RW : 0 Bit Name Page Bits[2:0] This register is used to set the effective SRAM page for indexed memory accesses in a multi-SRAM page PSoC device. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. -
Page 193: Mvr_Pp
MVR_PP 0,D4h 13.2.61 MVR_PP MVI Read Page Pointer Register Individual Register Names and Addresses: 0,D4h MVR_PP: 0,D4h Access : POR RW : 0 Bit Name Page Bits[2:0] This register is used to set the effective SRAM page for MVI read memory accesses in a multi-SRAM page PSoC device. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. -
Page 194: Mvw_Pp
MVW_PP 0,D5h 13.2.62 MVW_PP MVI Write Page Pointer Register Individual Register Names and Addresses: 0,D5h MVW_PP: 0,D5h Access : POR RW : 0 Bit Name Page Bits[2:0] This register is used to set the effective SRAM page for MVI write memory accesses in a multi-SRAM page PSoC device. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. -
Page 195: I2Cx_Cfg
I2Cx_CFG 0,D6h 13.2.63 I2Cx_CFG C Configuration Register Individual Register Names and Addresses: 0,D6h I2C0_CFG : 0,D6h I2C1_CFG : 1,6Bh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name PSelect Bus Error IE... -
Page 196: I2Cx_Scr
I2Cx_SCR 0,D7h 13.2.64 I2Cx_SCR C Status and Control Register Individual Register Names and Addresses: 0,D7h I2C0_SCR : 0,D7h I2C1_SCR : 0,E4h Access : POR RC : 0 RC : 0 RC : 0 RW : 0 RC : 0 RW : 0 RC : 0 RC : 0 Bit Name... - Page 197 I2Cx_SCR 0,D7h I2Cx_SCR 13.2.64 (continued) Byte Complete Transmit/Receive Mode: No completed transmit/receive since last cleared by firmware. Any Start detect or a write to the Start or Restart generate bits, when operating in Master mode, will also clear the bit. Transmit Mode: Eight bits of data have been transmitted and an ACK or NAK has been received.
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Page 198: I2Cx_Dr
I2Cx_DR 0,D8h 13.2.65 I2Cx_DR C Data Register Individual Register Names and Addresses: 0,D8h I2C1_DR : 0,67h I2C0_DR : 0,D8h Access : POR RW : 00 Bit Name Data[7:0] This register provides read/write access to the Shift register. Note that the second I C block is available in the CY8C28x03, CY8C28x23, CY8C28x43, and CY8C28x45 PSoC devices only. -
Page 199: I2Cx_Mscr
I2Cx_MSCR 0,D9h 13.2.66 I2Cx_MSCR C Master Status and Control Register Individual Register Names and Addresses: 0,D9h I2C0_MSCR : 0,D9h I2C1_MSCR : 0,E5h Access : POR R : 0 R : 0 RW : 0 RW : 0 Bit Name Bus Busy Master Mode Restart Gen Start Gen... -
Page 200: Int_Clr0
INT_CLR0 0,DAh 13.2.67 INT_CLR0 Interrupt Clear Register 0 Individual Register Names and Addresses: 0,DAh INT_CLR0: 0,DAh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name Sleep... - Page 201 INT_CLR0 0,DAh 13.2.67 INT_CLR0 (continued) Analog 2 Read 0 No posted interrupt for analog columns. Read 1 Posted interrupt present for analog columns Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect.
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Page 202: Int_Clr1
INT_CLR1 0,DBh 13.2.68 INT_CLR1 Interrupt Clear Register 1 Individual Register Names and Addresses: 0,DBh INT_CLR1: 0,DBh 4, 2 Rows Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name... - Page 203 INT_CLR1 0,DBh 13.2.68 INT_CLR1 (continued) DBC10 Digital Basic Block type B, row 1, position 0. Read 0 No posted interrupt. Read 1 Posted interrupt present. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect.
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Page 204: Int_Clr2
INT_CLR2 0,DCh 13.2.69 INT_CLR2 Interrupt Clear Register 2 Individual Register Names and Addresses: 0,DCh INT_CLR2: 0,DCh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name DCC23 DCC22 DBC21 DBC20 This register is used to enable the individual interrupt sources’ ability to clear posted interrupts for digital blocks. When bits in this register are read, a ‘1’... -
Page 205: Int_Clr3
INT_CLR3 0,DDh 13.2.70 INT_CLR3 Interrupt Clear Register 3 Individual Register Names and Addresses: 0,DDh INT_CLR3: 0,DDh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name Analog 5 Analog 4 SARADC I2C1... - Page 206 INT_CLR3 0,DDh 13.2.70 INT_CLR3 (continued) I2C1 Read 0 No posted interrupt for I2C1. Read 1 Posted interrupt present for I2C1. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect.
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Page 207: Int_Msk3
INT_MSK3 0,DEh 13.2.71 INT_MSK3 Interrupt Mask Register 3 Individual Register Names and Addresses: 0,DEh INT_MSK3: 0,DEh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name ENSWINT Analog 5... -
Page 208: Int_Msk2
INT_MSK2 0,DFh 13.2.72 INT_MSK2 Interrupt Mask Register 2 Individual Register Names and Addresses: 0,DFh INT_MSK2: 0,DFh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name DCC23 DCC22 DBC21 DBC20 This register is used to enable the individual sources’ ability to create pending interrupts for digital blocks. When an interrupt is masked off in this register, the mask bit is ‘0’. -
Page 209: Int_Msk0
INT_MSK0 0,E0h 13.2.73 INT_MSK0 Interrupt Mask Register 0 Individual Register Names and Addresses: 0,E0h INT_MSK0: 0,E0h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name Sleep... -
Page 210: Int_Msk1
INT_MSK1 0,E1h 13.2.74 INT_MSK1 Interrupt Mask Register 1 Individual Register Names and Addresses: 0,E1h INT_MSK1: 0,E1h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name DCC13... -
Page 211: Int_Vc
INT_VC 0,E2h 13.2.75 INT_VC Interrupt Vector Clear Register Individual Register Names and Addresses: 0,E2h INT_VC: 0,E2h Access : POR RC : 00 Bit Name Pending Interrupt[7:0] This register returns the next pending interrupt and clears all pending interrupts when written. For additional information, refer to the “Register Definitions”... -
Page 212: Res_Wdt
RES_WDT 0,E3h 13.2.76 RES_WDT Reset Watchdog Timer Register Individual Register Names and Addresses: 0,E3h RES_WDT: 0,E3h Access : POR W : 00 Bit Name WDSL_Clear[7:0] This register is used to clear the watchdog timer and clear both the watchdog timer and the sleep timer. For additional information, refer to the “Register Definitions”... -
Page 213: Dec_Cr0
DEC_CR0 0,E6h 13.2.77 DEC_CR0 Decimator Global Control Register 0 Individual Register Names and Addresses: 0,E6h DEC_CR0: 0,E6h Access : POR RW : 00 Bit Name ACC_IGEN[3:0] ICLKS[0] ACE_IGEN[1:0] DCLKS[0] This register contains control bits for selecting the incremental gate enable signal and for selecting the decimator output latch signal. -
Page 214: Dec_Cr1
DEC_CR1 0,E7h 13.2.78 DEC_CR1 Decimator Global Control Register 1 Individual Register Names and Addresses: 0,E7h DEC_CR1: 0,E7h Access : POR RW : 00 Bit Name IDEC ICLKS[3] ICLKS[2] ICLKS[1] DCLKS[3] DCLKS[2] DCLKS[1] This register is used to configure the incremental gate enable signal, and the decimator output latch. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. -
Page 215: Cpu_F
CPU_F x,F7h 13.2.79 CPU_F M8C Flag Register Individual Register Names and Addresses: x,F7h CPU_F: x,F7h Access : POR RL : 0 RL : 0 RL : 0 RL : 0 RL : 0 Bit Name PgMode[1:0] Carry Zero This register provides read access to the M8C flags. The AND f, expr;... -
Page 216: Idacx_D
IDACx_D 0,FCh 13.2.80 IDACx_D IDAC Data Register Individual Register Names and Addresses: 0,FCh IDAC1_D : 0,FCh IDAC0_D : 0,FDh Access : POR RW : 00 Bit Name IDACx This register specifies the 8-bit multiplying factor that determines the output DAC current. For additional information, refer to the “Register Definitions”... -
Page 217: Cpu_Scr1
CPU_SCR1 x,FEh 13.2.81 CPU_SCR1 System Status and Control Register 1 Individual Register Names and Addresses: x,FEh CPU_SCR1: x,FEh Access : POR R : 0 RW : 0 R : 0 RW : 0 RW : 0 Bit Name IRESS SLIMO ECO EXW ECO EX IRAMDIS... -
Page 218: Cpu_Scr0
CPU_SCR0 x,FFh 13.2.82 CPU_SCR0 System Status and Control Register 0 Individual Register Names and Addresses: x,FFh CPU_SCR0: x,FFh Access : POR R : 0 RC : 0 RC : 1 RW : 0 RW : 0 Bit Name GIES WDRS PORS Sleep STOP... -
Page 219: Bank 1 Registers
PRTxDM0 1,00h 13.3 Bank 1 Registers The following registers are all in bank 1 and are listed in address order. Registers that are in both Bank 0 and Bank 1 are listed in address order in the section titled “Bank 0 Registers” on page 127. -
Page 220: Prtxdm1
PRTxDM1 1,01h 13.3.2 PRTxDM1 Port Drive Mode Bit Register 1 Individual Register Names and Addresses: 1,01h PRT0DM1 : 1,01h PRT1DM1 : 1,05h PRT2DM1 : 1,09h PRT3DM1 : 1,0Dh PRT4DM1 : 1,11h PRT5DM1 : 1,15h Access : POR RW : FFh Bit Name Drive Mode 1[7:0] This register is one of three registers whose combined value determines the unique Drive mode of each bit in a GPIO port. -
Page 221: Prtxic0
PRTxIC0 1,02h 13.3.3 PRTxIC0 Port Interrupt Control Register 0 Individual Register Names and Addresses: 1,02h PRT0IC0 : 1,02h PRT1IC0 : 1,06h PRT2IC0 : 1,0Ah PRT3IC0 : 1,0Eh PRT4IC0 : 1,12h PRT5IC0 : 1,16h Access : POR RW : 00 Bit Name Interrupt Control 0[7:0] This register is one of two registers whose combined value determine the unique Interrupt mode of each bit in a GPIO port. -
Page 222: Prtxic1
PRTxIC1 1,03h 13.3.4 PRTxIC1 Port Interrupt Control Register 1 Individual Register Names and Addresses: 1,03h PRT0IC1 : 1,03h PRT1IC1 : 1,07h PRT2IC1 : 1,0Bh PRT3IC1 : 1,0Fh PRT4IC1 : 1,13h PRT5IC1 : 1,17h Access : POR RW : 00 Bit Name Interrupt Control 1[7:0] This register is one of two registers whose combined value determine the unique Interrupt mode of each bit in a GPIO port. -
Page 223: Dxcxxfn
DxCxxFN 1,20h 13.3.5 DxCxxFN Digital Basic/Communications Type C Block Function Register Individual Register Names and Addresses: 1,20h DBC00FN : 1,20h DBC01FN : 1,24h DCC02FN : 1,28h DCC03FN : 1,2Ch DBC10FN : 1,30h DBC11FN : 1,34h DCC12FN : 1,38h DCC13FN : 1,3Ch DBC20FN : 1,40h DBC21FN : 1,44h DCC22FN : 1,48h... - Page 224 DxCxxFN 1,20h 13.3.5 DxCxxFN (continued) PWMDBL Same as Dead Band that follows: (cont.) Dead Band: Mode[1:0] are encoded as the Kill Type. Synchronous Restart KILL mode Disable KILL mode Asynchronous KILL mode Reserved UART: Mode[0] signifies the Direction. Receiver Transmitter Mode[1] signifies the Interrupt Type.
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Page 225: Dxcxxin
DxCxxIN 1,21h 13.3.6 DxCxxIN Digital Basic/Communications Type C Block Input Register Individual Register Names and Addresses: 1,21h DBC00IN : 1,21h DBC01IN : 1,25h DCC02IN : 1,29h DCC03IN : 1,2Dh DBC10IN : 1,31h DBC11IN : 1,35h DCC12IN : 1,39h DCC13IN : 1,3Dh DBC20IN : 1,41h DBC21IN : 1,45h DCC22IN : 1,49h... - Page 226 DxCxxIN 1,21h 13.3.6 DxCxxIN (continued) Clock Input[3:0] 0000b Clock disabled (low) 0001b 0010b Row broadcast net 0011b Previous block primary output (low for DBC00) 0100b SYSCLKX2 0101b 0110b 0111b CLK32K 1000b Row output 0 1001b Row output 1 1010b Row output 2 1011b Row output 3 1100b...
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Page 227: Dxcxxou
DxCxxOU 1,22h 13.3.7 DxCxxOU Digital Basic/Communications Type C Block Output Register Individual Register Names and Addresses: 1,22h DBC00OU : 1,22h DBC01OU : 1,26h DCC02OU : 1,2Ah DCC03OU : 1,2Eh DBC10OU : 1,32h DBC11OU : 1,36h DCC12OU : 1,3Ah DCC13OU : 1,3Eh DBC20OU : 1,42h DBC21OU : 1,46h DCC22OU : 1,4Ah... - Page 228 DxCxxOU 1,22h 13.3.7 DxCxxOU (continued) AUX IO Select[1:0] SPI Slave Source for SS_ Input if AUXEN =1. (cont.) Force SS_ Active Reserved Reserved Reserved OUTEN Enable Primary Function Output Driver Disabled Enabled Output Select[1:0] Row Output Select for Primary Function Output Row Output 0 Row Output 1 Row Output 2...
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Page 229: Dxcxxcr1 (Timer Control:000)
DxCxxCR1 (Timer Control:000) 1,23h 13.3.8 DxCxxCR1 (Timer Control:000) Digital Basic/Communication Type C Block Control Register 1 Individual Register Names and Addresses: 1,23h DBC00CR1 : 1,23h DBC01CR1 : 1,27h DCC02CR1 : 1,2Bh DCC03CR1 : 1,2Fh DBC10CR1 : 1,33h DBC11CR1 : 1,37h DCC12CR1 : 1,3Bh DCC13CR1 : 1,3Fh DBC20CR1 : 1,43h... -
Page 230: Dxcxxcr1 (Counter Control:001)
DxCxxCR1 (Counter Control:001) 1,23h 13.3.9 DxCxxCR1 (Counter Control:001) Digital Basic/Communication Type C Block Control Register 1 Individual Register Names and Addresses: 1,23h DBC00CR1 : 1,23h DBC01CR1 : 1,27h DCC02CR1 : 1,2Bh DCC03CR1 : 1,2Fh DBC10CR1 : 1,33h DBC11CR1 : 1,37h DCC12CR1 : 1,3Bh DCC13CR1 : 1,3Fh DBC20CR1 : 1,43h... -
Page 231: Dxcxxcr1 (Crcprs Control:010)
DxCxxCR1 (CRCPRS Control:010) 1,23h 13.3.10 DxCxxCR1 (CRCPRS Control:010) Digital Basic/Communication Type C Block Control Register 1 Individual Register Names and Addresses: 1,23h DBC00CR1 : 1,23h DBC01CR1 : 1,27h DCC02CR1 : 1,2Bh DCC03CR1 : 1,2Fh DBC10CR1 : 1,33h DBC11CR1 : 1,37h DCC12CR1 : 1,3Bh DCC13CR1 : 1,3Fh DBC20CR1 : 1,43h... -
Page 232: Dxcxxcr1 (Pwmdbl Control:011)
DxCxxCR1 (PWMDBL Control:011) 1,23h 13.3.11 DxCxxCR1 (PWMDBL Control:011) Digital Basic/Communication Type C Block Control Register 1 Individual Register Names and Addresses: 1,23h DBC00CR1 : 1,23h DBC01CR1 : 1,27h DCC02CR1 : 1,2Bh DCC03CR1 : 1,2Fh DBC10CR1 : 1,33h DBC11CR1 : 1,37h DCC12CR1 : 1,3Bh DCC13CR1 : 1,3Fh DBC20CR1 : 1,43h... -
Page 233: Dxcxxcr1 (Dead Band Control:100)
DxCxxCR1 (Dead Band Control:100) 1,23h 13.3.12 DxCxxCR1 (Dead Band Control:100) Digital Basic/Communication Type C Block Control Register 1 Individual Register Names and Addresses: 1,23h DBC00CR1 : 1,23h DBC01CR1 : 1,27h DCC02CR1 : 1,2Bh DCC03CR1 : 1,2Fh DBC10CR1 : 1,33h DBC11CR1 : 1,37h DCC12CR1 : 1,3Bh DCC13CR1 : 1,3Fh DBC20CR1 : 1,43h... -
Page 234: Dxcxxcr1 (Spim Control:0-110)
DxCxxCR1 (SPIM Control:0-110) 1,23h 13.3.13 DxCxxCR1 (SPIM Control:0-110) Digital Basic/Communication Type C Block Control Register 1 Individual Register Names and Addresses: 1,23h DBC00CR1 : 1,23h DBC01CR1 : 1,27h DCC02CR1 : 1,2Bh DCC03CR1 : 1,2Fh DBC10CR1 : 1,33h DBC11CR1 : 1,37h DCC12CR1 : 1,3Bh DCC13CR1 : 1,3Fh DBC20CR1 : 1,43h... -
Page 235: Dxcxxcr1 (Spis Control:0-110)
DxCxxCR1 (SPIS Control:0-110) 1,23h 13.3.14 DxCxxCR1 (SPIS Control:0-110) Digital Basic/Communication Type C Block Control Register 1 Individual Register Names and Addresses: 1,23h DBC00CR1 : 1,23h DBC01CR1 : 1,27h DCC02CR1 : 1,2Bh DCC03CR1 : 1,2Fh DBC10CR1 : 1,33h DBC11CR1 : 1,37h DCC12CR1 : 1,3Bh DCC13CR1 : 1,3Fh DBC20CR1 : 1,43h... -
Page 236: Dxcxxcr1 (Dsm Control:111)
DxCxxCR1 (DSM Control:111) 1,23h 13.3.15 DxCxxCR1 (DSM Control:111) Digital Basic/Communication Type C Block Control Register 1 Individual Register Names and Addresses: 1,23h DBC00CR1 : 1,23h DBC01CR1 : 1,27h DCC02CR1 : 1,2Bh DCC03CR1 : 1,2Fh DBC10CR1 : 1,33h DBC11CR1 : 1,37h DCC12CR1 : 1,3Bh DCC13CR1 : 1,3Fh DBC20CR1 : 1,43h... -
Page 237: Clk_Cr0
CLK_CR0 1,60h 13.3.16 CLK_CR0 Analog Column Clock Control Register 0 Individual Register Names and Addresses: 1,60h CLK_CR0: 1,60h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name AColumn3[1:0] AColumn2[1:0] AColumn1[1:0] AColumn0[1:0] This register is used to select the clock source for an individual analog column. Each column has two bits that select the column clock input source. -
Page 238: Clk_Cr1
CLK_CR1 1,61h 13.3.17 CLK_CR1 Analog Clock Source Control Register 1 Individual Register Names and Addresses: 1,61h CLK_CR1: 1,61h Access : POR RW : 0 RW : 0 RW : 0 Bit Name SHDIS ACLK1[2:0] ACLK0[2:0] This register is used to select the clock source for an individual analog column. There are two ranges of Digital PSoC blocks shown. -
Page 239: Abf_Cr0
ABF_CR0 1,62h 13.3.18 ABF_CR0 Analog Output Buffer Control Register 0 Individual Register Names and Addresses: 1,62h ABF_CR0: 1,62h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name ACol1Mux... -
Page 240: Amd_Cr0
AMD_CR0 1,63h 13.3.19 AMD_CR0 Analog Modulation Control Register 0 Individual Register Names and Addresses: 1,63h AMD_CR0: 1,63h Access : POR RW : 0 RW : 0 Bit Name AMOD2[2:0] AMOD0[2:0] This register is used to select the modulator bits used with each column. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. -
Page 241: Cmp_Go_En
CMP_GO_EN 1,64h 13.3.20 CMP_GO_EN Comparator Bus to Global Outputs Enable Register Individual Register Names and Addresses: 1,64h CMP_GO_EN: 1,64h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name GOO5 GOO1... -
Page 242: Cmp_Go_En1
CMP_GO_EN1 1,65h 13.3.21 CMP_GO_EN1 Comparator Bus to Global Outputs Enable Register 1 Individual Register Names and Addresses: 1,65h CMP_GO_EN1: 1,65h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name GOO7 GOO3... -
Page 243: Amd_Cr1
AMD_CR1 1,66h 13.3.22 AMD_CR1 Analog Modulation Control Register 1 Individual Register Names and Addresses: 1,66h AMD_CR1: 1,66h Access : POR RW : 0 RW : 0 Bit Name AMOD3[2:0] AMOD1[2:0] This register is used to select the modulator bits used with each column. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. -
Page 244: Alt_Cr0
ALT_CR0 1,67h 13.3.23 ALT_CR0 Analog LUT Control Register 0 Individual Register Names and Addresses: 1,67h ALT_CR0: 1,67h Access : POR RW : 0 RW : 0 Bit Name LUT1[3:0] LUT0[3:0] This register is used to select the logic function. For additional information, see “Register Definitions”... -
Page 245: Alt_Cr1
ALT_CR1 1,68h 13.3.24 ALT_CR1 Analog LUT Control Register 1 Individual Register Names and Addresses: 1,68h ALT_CR1: 1,68h 4 COLUMN Access : POR RW : 0 RW : 0 Bit Name LUT3[3:0] LUT2[3:0] This register is used to select the logic function performed by the LUT for each analog column. This register is for 4 column PSoC devices only. -
Page 246: Clk_Cr2
CLK_CR2 1,69h 13.3.25 CLK_CR2 Analog Clock Source Control Register 2 Individual Register Names and Addresses: 1,69h CLK_CR2: 1,69h 4 COLUMN Access : POR RW : 0 RW : 0 Bit Name ACLK1R ACLK0R This register, in conjunction with the CLK_CR1 and CLK_CR0 registers, selects a digital block as a source for analog column clocking. -
Page 247: Amux_Cfg1
AMUX_CFG1 1,6Ah 13.3.26 AMUX_CFG1 Analog Mux Config Register 1 Individual Register Names and Addresses: 1,6Ah AMUX_CFG1: 1,6Ah Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name ABusMux3 ABusMux2 ACol3Mux... -
Page 248: Sadc_Tscr0
SADC_TSCR0 1,71h 13.3.27 SADC_TSCR0 SAR ADC Trigger Source Control Register 0 Individual Register Names and Addresses: 1,71h SADC_TSCR0: 1,71h Access : POR RW : 0000 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name TS_INCMP_SEL[3:0] INCMP_INV INCMP_EN CMPH_EN... -
Page 249: Sadc_Tscr1
SADC_TSCR1 1,72h 13.3.28 SADC_TSCR1 SAR ADC Trigger Source Control Register 1 Individual Register Names and Addresses: 1,72h SADC_TSCR1: 1,72h Access : POR RW : 000 RW : 000 Bit Name TS_CMPH_SEL[2:0] TS_CMPL_SEL[2:0] This register controls the selection of digital blocks for high and low channel comparison. The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45 PSoC devices. -
Page 250: Ace_Amd_Cr0
ACE_AMD_CR0 1,73h 13.3.29 ACE_AMD_CR0 Analog Type-E Modulation Control Register 0 Individual Register Names and Addresses: 1,73h ACE_AMD_CR0: 1,73h 2L* Column Access : POR RW : 0 Bit Name AMOD4[3:0] * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. -
Page 251: Ace_Amx_In
ACE_AMX_IN 1,75h 13.3.30 ACE_AMX_IN Analog Type-E Input Select Register Individual Register Names and Addresses: 1,75h ACE_AMX_IN: 1,75h 2L* Column Access : POR RW : 0 RW : 0 Bit Name ACI5[1:0] ACI4[1:0] * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. -
Page 252: Ace_Cmp_Cr0
ACE_CMP_CR0 1,76h 13.3.31 ACE_CMP_CR0 Analog Type-E Comparator Bus 0 Register Individual Register Names and Addresses: 1,76h ACE_CMP_CR0: 1,76h 2L* Column Access : POR R : 0 RW : 0 Bit Name COMP[5:4] AINT[5:4] * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. -
Page 253: Ace_Cmp_Cr1
ACE_CMP_CR1 1,77h 13.3.32 ACE_CMP_CR1 Analog Type-E Comparator Bus 1 Register Individual Register Names and Addresses: 1,77h ACE_CMP_CR1: 1,77h 2L* Column Access : POR RW : 0 RW : 0 Bit Name CLDIS[5 CLDIS[4] * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. -
Page 254: Ace_Cmp_Gi_En
ACE_CMP_GI_EN 1,79h 13.3.33 ACE_CMP_GI_EN Analog Type-E Columns Compare Bus to Global Inputs Control Register Individual Register Names and Addresses: 1,79h ACE_CMP_GI_EN : 1,79h 2L* Column Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name... -
Page 255: Ace_Alt_Cr0
ACE_ALT_CR0 1,7Ah 13.3.34 ACE_ALT_CR0 Analog Type-E LUT Control Register 0 Individual Register Names and Addresses: 1,7Ah ACE_ALT_CR0: 1,7Ah 2L* Column Access : POR RW : 0 RW : 0 Bit Name LUT5[3:0] LUT4[3:0] * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. -
Page 256: Ace_Abf_Cr0
ACE_ABF_CR0 1,7Bh 13.3.35 ACE_ABF_CR0 Analog Type-E Output Buffer Control Register 0 Individual Register Names and Addresses: 1,7Bh ACE_ABF_CR0: 1,7Bh 2L* Column Access : POR RW : 0 RW : 0 Bit Name ACE1Mux ACE0Mux * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. -
Page 257: Acexxcr1
ACExxCR1 1,7Dh 13.3.36 ACExxCR1 Analog Continuous Time Type E Block Control Register 1 Individual Register Names and Addresses: 1,7Dh ACE00CR1 : 1,7Dh ACE01CR1 : 1,8Dh 2L* Column Access : POR RW : 0 RW : 0 RW : 0 Bit Name CompBus NMux[2:0] PMux[2:0]... -
Page 258: Acexxcr2
ACExxCR2 1,7Eh 13.3.37 ACE xCR2 Analog Continuous Time Type E Block Control Register 2 Individual Register Names and Addresses: 1,7Eh ACE00CR2 : 1,7Eh ACE01CR2 : 1,8Eh 2L* Column Access : POR RW : 0 RW : 0 Bit Name FullRange * This register is only available for CY8C28xxx devices that have E-type analog blocks. -
Page 259: Asexxcr0
ASExxCR0 1,7Fh 13.3.38 ASE xCR0 Analog Switch Cap Type E Block Control Register 0 Individual Register Names and Addresses: 1,7Fh ASE10CR0 : 1,7Fh ASE11CR0 : 1,8Fh 2L* Column Access : POR RW : 0 Bit Name FVal * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. -
Page 260: Sadc_Tscmpl
SADC_TSCMPL 1,81h 13.3.39 SADC_TSCMPL SAR ADC Trigger Source Compare Low Register Individual Register Names and Addresses: 1,81h SADC_TSCMPL: 1,81h Access : POR RW : 00 Bit Name TS_CMPL[7:0] This byte contains the low channel comparison value. This value is compared against the DR0 register of the digital block chosen in TS_CMPL_SEL. -
Page 261: Sadc_Tscmph
SADC_TSCMPH 1,82h 13.3.40 SADC_TSCMPH SAR ADC Trigger Source Compare High Register Individual Register Names and Addresses: 1,82h SADC_TSCMPH: 1,82h Access : POR RW : 00 Bit Name TS_CMPH[7:0] This byte contains the high channel comparison value. This value is compared against the DR0 register of the digital block chosen in TS_CMPH_SEL. -
Page 262: Ace_Amd_Cr1
ACE_AMD_CR1 1,83h 13.3.41 ACE_AMD_CR1 Analog Type-E Modulation Control Register 1 Individual Register Names and Addresses: 1,83h ACE_AMD_CR1: 1,83h 2L* Column Access : POR RW : 0 Bit Name AMOD5[3:0] * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. -
Page 263: Ace_Pwm_Cr
ACE_PWM_CR 1,85h 13.3.42 ACE_PWM_CR ADC PWM Control Register Individual Register Names and Addresses: 1,85h ACE_PWM_CR: 1,85h 2L* Column Access : POR RW : 0 RW : 0 RW : 0 Bit Name HIGH[2:0] LOW[1:0] PWMEN * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. -
Page 264: Ace_Adcx_Cr
ACE_ADCx_CR 1,86h 13.3.43 ACE_ADCx_CR ADC Column 0 and Column 1 Configuration Register Individual Register Names and Addresses: 1,86h ACE_ADC0_CR : 1,86h ACE_ADC1_CR : 1,87h 2L* Column Access : POR R : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name... -
Page 265: Ace_Clk_Cr0
ACE_CLK_CR0 1,89h 13.3.44 ACE_CLK_CR0 Analog Type-E Column Clock Control Register 0 Individual Register Names and Addresses: 1,89h ACE_CLK_CR0: 1,89h 2L* Column Access : POR RW : 0 RW : 0 Bit Name AColumn5[1:0] AColumn4[1:0] * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. -
Page 266: Ace_Clk_Cr1
ACE_CLK_CR1 1,8Ah 13.3.45 ACE_CLK_CR1 Analog Type E Columns Clock Control Register 1 Individual Register Names and Addresses: 1,8Ah ACE_CLK_CR1 : 1,8Ah 2L* Column Access : POR RW : 0 RW : 0 Bit Name ACLK5[3:0] ACLK4[3:0] * This register is only available for CY8C28xxx devices that have E-type analog blocks. This register is reserved for CY8C28x03, CY8C28x23, and CY8C28x43 devices. -
Page 267: Ace_Clk_Cr3
ACE_CLK_CR3 1,8Bh 13.3.46 ACE_CLK_CR3 Analog Clock Source Control Register 3 Individual Register Names and Addresses: 1,8Bh ACE_CLK_CR3: 1,8Bh 2L* Column Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name SYS5 DIVCLK5[1:0] SYS4 DIVCLK4[1:0] * This register is only available for CY8C28xxx devices that have E-type analog blocks. -
Page 268: Decx_Cr0
DECx_CR0 1,91h 13.3.47 DECx_CR0 Decimator Control Register 0 Individual Register Names and Addresses: 1,91h DEC0_CR0 : 1,91h DEC1_CR0 : 1,95h DEC2_CR0 : 1,99h DEC3_CR0 : 1,9Dh Access : POR RW : 00 Bit Name GOOO GOOE DATA_IN[2:0] This register controls the data inputs for the decimator. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. -
Page 269: Dec_Cr3
DEC_CR3 1,92h 13.3.48 DEC_CR3 Decimator Global Control Register 3 Individual Register Names and Addresses: 1,92h DEC_CR3: 1,92h Access : POR RW : 00 Bit Name DEC1_EN CLK_IN1[2:0] DEC0_EN CLK_IN0[2:0] This register controls decimator enabling and clock selection. For additional information, refer to the “Register Definitions”... -
Page 270: Dec_Cr4
DEC_CR4 1,96h 13.3.49 DEC_CR4 Decimator Global Control Register 4 Individual Register Names and Addresses: 1,96h DEC_CR4: 1,96h Access : POR RW : 00 Bit Name DEC3_EN CLK_IN3[2:0] DEC2_EN CLK_IN2[2:0] This register controls decimator enabling and clock selection. For additional information, refer to the “Register Definitions”... -
Page 271: Dec_Cr5
DEC_CR5 1,9Ah 13.3.50 DEC_CR5 Decimator Global Control Register 5 Individual Register Names and Addresses: 1,9Ah DEC_CR5: 1,9Ah Access : POR RW : 00 Bit Name DSCLK[3:0] In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. -
Page 272: Gdi_O_In_Cr
GDI_O_IN_CR 1,A0h 13.3.51 GDI_O_IN_CR Global Digital Interconnect Odd Inputs Control Register Individual Register Names and Addresses: 1,A0h GDI_O_IN_CR: 1,A0h Access : POR RW : 00 Bit Name GDIOICR[7] GDIOICR[6] GDIOICR[5] GDIOICR[4] GDIOICR[3] GDIOICR[2] GDIOICR[1] GDIOICR[0] This register allows a global input net to drive its corresponding next global output net. Note that the corresponding bit in GDI_O_IN must be set. -
Page 273: Gdi_E_In_Cr
GDI_E_IN_CR 1,A1h 13.3.52 GDI_E_IN_CR Global Digital Interconnect Even Inputs Control Register Individual Register Names and Addresses: 1,A1h GDI_E_IN_CR: 1,A1h Access : POR RW : 00 Bit Name GDIEICR[7] GDIEICR[6] GDIEICR[5] GDIEICR[4] GDIEICR[3] GDIEICR[2] GDIEICR[1] GDIEICR[0] This register allows a global input net to drive its corresponding next global output net. Note that the corresponding bit in GDI_E_IN must be set. -
Page 274: Gdi_O_Ou_Cr
GDI_O_OU_CR 1,A2h 13.3.53 GDI_O_OU_CR Global Digital Interconnect Odd Outputs Control Register Individual Register Names and Addresses: 1,A2h GDI_O_OU_CR: 1,A2h Access : POR RW : 00 Bit Name GDIOOCR[7] GDIOOCR[6] GDIOOCR[5] GDIOOCR[4] GDIOOCR[3] GDIOOCR[2] GDIOOCR[1] GDIOOCR[0] This register allows a global output net to drive its corresponding next global input net. Note that corresponding bit in GDI_O_OU must be set. -
Page 275: Gdi_E_Ou_Cr
GDI_E_OU_CR 1,A3h 13.3.54 GDI_E_OU_CR Global Digital Interconnect Even Outputs Control Register Individual Register Names and Addresses: 1,A3h GDI_E_OU_CR: 1,A3h Access : POR RW : 00 Bit Name GDIEOCR[7] GDIEOCR[6] GDIEOCR[5] GDIEOCR[4] GDIEOCR[3] GDIEOCR[2] GDIEOCR[1] GDIEOCR[0] This register allows a global output net to drive its corresponding next global input net. Note that corresponding bit in GDI_E_OU must be set. -
Page 276: Rtc_H
RTC_H 1,A4h 13.3.55 RTC_H Real Time Clock Hours Register Individual Register Names and Addresses: 1,A4h RTC_H: 1,A4h Access : POR RW : 00 RW : 0000 Bit Name HR1[1:0] HR0[3:0] This register is used to read and write the current hour value in BCD format. Writing to this register will reset count 65536 to all zeros. -
Page 277: Rtc_M
RTC_M 1,A5h 13.3.56 RTC_M Real Time Clock Minutes Register Individual Register Names and Addresses: 1,A5h RTC_M: 1,A5h Access : POR RW : 00 RW : 0000 Bit Name MIN1[2:0] MIN0[3:0] This register is used to read and write the current minute value in BCD format. Writing to this register will reset count 65536 to all zeros. -
Page 278: Rtc_S
RTC_S 1,A6h 13.3.57 RTC_S Real Time Clock Seconds Register Individual Register Names and Addresses: 1,A6h RTC_S: 1,A6h Access : POR RW : 00 RW : 0000 Bit Name SEC1[2:0] SEC0[3:0] This register is used to read and write the current second value in BCD format. Writing to this register will reset count 65536 to all zeros. -
Page 279: Rtc_Cr
RTC_CR 1,A7h 13.3.58 RTC_CR Real Time Clock Control Register Individual Register Names and Addresses: 1,A7h RTC_CR: 1,A7h Access : POR RW : 0 RW : 0 RW : 00 RW : 0 RW : 0 Bit Name INT_EN CLKSE INT_SEL[1:0] SYNCRD_EN RTC_EN This register controls the RTC. -
Page 280: Sadc_Cr0
SADC_CR0 1,A8h 13.3.59 SADC_CR0 SAR ADC Control Register 0 Individual Register Names and Addresses: 1,A8h SADC_CR0: 1,A8h Access : POR RW : 0000 RW : 0 RW : 0 RW : 0 Bit Name ADC_CHS[3:0] READY Start/ONGOING ADCEN This register controls the input selection for the SAR ADC, and contains status and enable bits. The 10-bit SAR ADC control- ler only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45 PSoC devices. -
Page 281: Sadc_Cr1
SADC_CR1 1,A9h 13.3.60 SADC_CR1 SAR ADC Control Register 1 Individual Register Names and Addresses: 1,A9h SADC_CR1: 1,A9h Access : POR RW : 00 RW : 00 RW : 000 RW : 0 Bit Name CVTMD[1:0] TIGSEL[1:0] CLKSEL[2:0] ALIGN_EN This register contains control bit for the 10-bit SAR ADC. The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45 PSoC devices. -
Page 282: Sadc_Cr2
SADC_CR2 1,AAh 13.3.61 SADC_CR2 SAR ADC Control Register 2 Individual Register Names and Addresses: 1,AAh SADC_CR2: 1,AAh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name REFSEL BUFEN VDBEN VDB_CLK FREERUN The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45... -
Page 283: Sadc_Cr3
SADC_CR3 1,ABh 13.3.62 SADC_CR3 SAR ADC Control Register 3 Individual Register Names and Addresses: 1,ABh SADC_CR3: 1,ABh Access : POR RW : 0 RW : 0 Bit Name LALIGN ADC_TRIM0[2:0] The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45 PSoC devices. -
Page 284: Sadc_Cr4
SADC_CR4 1,ACh 13.3.63 SADC_CR4 SAR ADC Control Register 4 Individual Register Names and Addresses: 1,ACh SADC_CR4: 1,ACh Access : POR RW : 0 Bit Name EXTREF The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45 PSoC devices. -
Page 285: I2Cx_Addr
I2Cx_ADDR 1,ADh 13.3.64 I2Cx_ADDR C Address Register Individual Register Names and Addresses: 1,ADh I2C0_ADDR : 1,ADh I2C1_ADDR : 1,AEh Access : POR RW:0 RW : 000000 Bit Name HwAddrEn Addr[6:0] The I C address register is used to configure the hardware address automatic comparison feature so that the microcontroller will not be disturbed by an unwanted slave request. -
Page 286: Amux_Clk
AMUX_CLK 1,AFh 13.3.65 AMUX_CLK Analog Mux Clock Register Individual Register Names and Addresses: 1,AFh AMUX_CLK: 1,AFh 2 Column Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name CLKTOR CLKTOL CLK1SYNC[1:0] CLK0SYNC[1:0] This register is used to adjust the phase of the clock to the analog mux bus. This register is only used by the CY8C28xxx PSoC devices. -
Page 287: Gdi_O_In
GDI_O_IN 1,D0h 13.3.66 GDI_O_IN Global Digital Interconnect Odd Inputs Register Individual Register Names and Addresses: 1,D0h GDI_O_IN: 1,D0h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name GIONOUT7... -
Page 288: Gdi_E_In
GDI_E_IN 1,D1h 13.3.67 GDI_E_IN Global Digital Interconnect Even Inputs Register Individual Register Names and Addresses: 1,D1h GDI_E_IN: 1,D1h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name GIENOUT7... -
Page 289: Gdi_O_Ou
GDI_O_OU 1,D2h 13.3.68 GDI_O_OU Global Digital Interconnect Odd Outputs Register Individual Register Names and Addresses: 1,D2h GDI_O_OU: 1,D2h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name GOOUTIN7... -
Page 290: Gdi_E_Ou
GDI_E_OU 1,D3h 13.3.69 GDI_E_OU Global Digital Interconnect Even Outputs Register Individual Register Names and Addresses: 1,D3h GDI_E_OU: 1,D3h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name GOEUTIN7... -
Page 291: Decx_Cr
DECx_CR 1,D4h 13.3.70 DECx_CR Decimator Type 2 Control Register Individual Register Names and Addresses: 1,D4h DEC0_CR : 1,D4h DEC1_CR : 1,D5h DEC2_CR : 1,D6h DEC3_CR : 1,D7h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name Mode[1:0] Data Out Shift[1:0]... -
Page 292: Mux_Crx
MUX_CRx 1,D8h 13.3.71 MUX_CRx Analog Mux Port Bit Enables Register Individual Register Names and Addresses: 1,D8h MUX_CR0 : 1,D8h MUX_CR1 : 1,D9h MUX_CR2 : 1,DAh MUX_CR3 : 1,DBh MUX_CR4 : 1,ECh MUX_CR5 : 1,EDh Access : POR RW : 00 Bit Name ENABLE[7:0] This register is used to control the connection between the analog mux bus and the corresponding pin. -
Page 293: Idac_Cr1
IDAC_CR1 1,DCh 13.3.72 IDAC_CR1 IDAC Control Register 1 Individual Register Names and Addresses: 1,DCh IDAC_CR1 : 1,DCh Access : POR RW : 0 RW : 0 RW : 00 RW : 1000 RW : 0 Bit Name MuxClkGE1 ICEN IDAC_TRIM Double_Current This register contains the control bits for the IDAC current that drives the analog mux bus and for selecting the split configuration. -
Page 294: Osc_Go_En
OSC_GO_EN 1,DDh 13.3.73 OSC_GO_EN Oscillator to Global Outputs Enable Register Individual Register Names and Addresses: 1,DDh OSC_GO_EN: 1,DDh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name SLPINT... -
Page 295: Osc_Cr4
OSC_CR4 1,DEh 13.3.74 OSC_CR4 Oscillator Control Register 4 Individual Register Names and Addresses: 1,DEh OSC_CR4: 1,DEh Access : POR RW : 0 Bit Name VC3 Input Select[1:0] This register selects the input clock to variable clock 3 (VC3). In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’. -
Page 296: Osc_Cr3
OSC_CR3 1,DFh 13.3.75 OSC_CR3 Oscillator Control Register 3 Individual Register Names and Addresses: 1,DFh OSC_CR3: 1,DFh Access : POR RW : 00 Bit Name VC3 Divider[7:0] This register selects the divider value for variable clock 3 (VC3). The output frequency of the VC3 Clock Divider is the input frequency divided by the value in this register, plus one. For exam- ple, if this register contains 07h, the clock frequency output from the VC3 Clock Divider will be one eighth the input frequency. -
Page 297: Osc_Cr0
OSC_CR0 1,E0h 13.3.76 OSC_CR0 Oscillator Control Register 0 Individual Register Names and Addresses: 1,E0h OSC_CR0: 1,E0h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed[2:0]... -
Page 298: Osc_Cr1
OSC_CR1 1,E1h 13.3.77 OSC_CR1 Oscillator Control Register 1 Individual Register Names and Addresses: 1,E1h OSC_CR1: 1,E1h Access : POR RW : 0 RW : 0 Bit Name VC1 Divider[3:0] VC2 Divider[3:0] This register selects the divider value for variable clocks 1 and 2 (VC1 and VC2). For additional information, refer to the “Register Definitions”... -
Page 299: Osc_Cr2
OSC_CR2 1,E2h 13.3.78 OSC_CR2 Oscillator Control Register 2 Individual Register Names and Addresses: 1,E2h OSC_CR2: 1,E2h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name PLLGAIN SLP_EXTEND WDR32_SE EXTCLKEN... -
Page 300: Vlt_Cr
VLT_CR 1,E3h 13.3.79 VLT_CR Voltage Monitor Control Register Individual Register Names and Addresses: 1,E3h VLT_CR: 1,E3h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name PORLEV[1:0] LVDTBEN VM[2:0] This register is used to set the trip points for POR, LVD, and the supply pump. Note that reserved bits are grayed table cells and are not described in the bit description section. -
Page 301: Vlt_Cmp
VLT_CMP 1,E4h 13.3.80 VLT_CMP Voltage Monitor Comparators Register Individual Register Names and Addresses: 1,E4h VLT_CMP: 1,E4h Access : POR R : 0 R : 0 R : 0 Bit Name PUMP PPOR This register is used to read the state of internal supply voltage monitors. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. -
Page 302: Adcx_Tr
ADCx_TR 1,E5h 13.3.81 ADCx_TR Type E ADC Trim Register Individual Register Names and Addresses: 1,E5h ADC0_TR : 1,E5h ADC1_TR : 1,E6h 2L* Column Access : POR RW : 00 Bit Name CAPVAL_[7:0] * This table shows the two column limited functionality of the CY8C28xxx PSoC devices for this register. This register controls a combination of capacitor and current values that determine the slope of the ADC voltage ramp. -
Page 303: Idac_Mode
IDAC_MODE 1,E7h 13.3.82 IDAC_MODE IDAC Mode Control Register Individual Register Names and Addresses: 1,E7h IDAC_MODE: 1,E7h Access : POR RW : 00 RW : 00 RW : 00 RW : 00 Bit Name IDAC1_MD[3:0] IDAC0_MD[3:0] This register controls the selection of the IDAC ON/OFF Control. For additional information, refer to the “Register Definitions”... -
Page 304: Imo_Tr
IMO_TR 1,E8h 13.3.83 IMO_TR Internal Main Oscillator Trim Register Individual Register Names and Addresses: 1,E8h IMO_TR: 1,E8h Access : POR W : 00 Bit Name Trim[7:0] This register is used to manually center the oscillator’s output to a target frequency. It is strongly recommended that the user not alter this register’s values. -
Page 305: Ilo_Tr
ILO_TR 1,E9h 13.3.84 ILO_TR Internal Low Speed Oscillator Trim Register Individual Register Names and Addresses: 1,E9h ILO_TR: 1,E9h Access : POR RW : 0 RW : 0 Bit Name Bias Trim[1:0] Freq Trim[3:0] This register sets the adjustment for the Internal Low Speed Oscillator (ILO). It is strongly recommended that the user not alter this register’s values. -
Page 306: Bdg_Tr
BDG_TR 1,EAh 13.3.85 BDG_TR Bandgap Trim Register Individual Register Names and Addresses: 1,EAh BDG_TR: 1,EAh Access : POR RW : 0 RW : 01 RW : 8h Bit Name AGNDBYP TC[1:0] V[3:0] This register is used to adjust the bandgap and add an RC filter to AGND. Note that reserved bits are grayed table cells and are not described in the bit description section. -
Page 307: Eco_Tr
ECO_TR 1,EBh 13.3.86 ECO_TR External Crystal Oscillator Trim Register Individual Register Names and Addresses: 1,EBh ECO_TR: 1,EBh Access : POR RW : 0 Bit Name PSSDC[1:0] This register sets the adjustment for the 32.768 kHz External Crystal Oscillator. The value in this register should not be changed. The value is used to trim the 32.768 kHz external crystal oscillator and is set to the device specific, best value during boot. -
Page 308: Imo_Tr1
IMO_TR1 1,EFh 13.3.87 IMO_TR1 Internal Main Oscillator Trim Register 1 Individual Register Names and Addresses: 1,EFh IMO_TR1: 1,EFh Access : POR RW : 0 Bit Name CATA_Trim[1:0] This register is used to tune CATA current. For additional information, refer to the “Register Definitions”... -
Page 309: Fls_Pr1
FLS_PR1 1,FAh 13.3.88 FLS_PR1 Flash Program Register 1 Individual Register Names and Addresses: 1,FAh FLS_PR1: 1,FAh Access : POR RW : 0 Bit Name Bank This register is used to specify which Flash bank should be used for SROM operations. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. -
Page 310: Idac_Cr0
IDAC_CR0 1,FDh 13.3.89 IDAC_CR0 IDAC Control Register 0 Individual Register Names and Addresses: 1,FDh IDAC_CR0 : 1,FDh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name SplitMux MuxClkGE0 OSCMD1[1:0]... - Page 311 IDAC_CR0 1,FDh CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
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Page 312: Section D: Digital System
Section D: Digital System ® The configurable Digital System section discusses the digital components of the PSoC device and the registers associated with those components. This section encompasses the following chapters: ■ ■ Global Digital Interconnect (GDI) on page 317 Row Digital Interconnect (RDI) on page 327 ■... -
Page 313: Digital Register Summary
Digital Register Summary The following table lists all the PSoC registers for the digital system in address order (Add. column) within their system resource configuration. The bits that are grayed out are reserved bits. If these bits are written, they should always be written with a value of ‘0’. - Page 314 Summary Table of the Digital Registers (continued) Digital Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Rows DIGITAL BLOCK REGISTERS (page 348) Digital Block Data and Control Registers (page 348) 0,20h DBC00DR0 3, 2,...
- Page 315 Summary Table of the Digital Registers (continued) Digital Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Rows 0,38h DCC12DR0 3, 2, Data[7:0] # : 00 0,39h DCC12DR1 3, 2, Data[7:0] W : 00 0,3Ah...
- Page 316 Summary Table of the Digital Registers (continued) Digital Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Rows 0,DFh INT_MSK2 DCC23 DCC22 DBC21 DBC20 RW : 00 0,E0h INT_MSK0 Sleep GPIO Analog 3 Analog 2...
- Page 317 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
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Page 318: Global Digital Interconnect (Gdi)
14. Global Digital Interconnect (GDI) ® This chapter discusses the Global Digital Interconnect (GDI) and its associated registers. All PSoC CY8C28xxx devices have the exact same global digital interconnect options, varying only in the number of 8-bit ports connected to the globals. For a complete table of the GDI registers, refer to the “Summary Table of the Digital Registers”... -
Page 319: 20-Pin Global Interconnect
Global Digital Interconnect (GDI) 14.1.1 20-Pin Global Interconnect To determine the number of digital rows and digital blocks in your PSoC device, refer to the table titled “PSoC Device Charac- teristics” on page 311. Figure 14-1. Global Interconnect Block Diagram for the CY8C28243 20-Pin Package GOE[7] GOE[5] GOE[3]... -
Page 320: 28-Pin Global Interconnect
Global Digital Interconnect (GDI) 14.1.2 28-Pin Global Interconnect Because up to two ports are connected to a single global bus, there is a one-to-many mapping between individual For 28-pin PSoC devices, there are three 8-bit ports. There- nets in a global bus and port pins. For example, if GIE[1] is fore, there are two ports connected to the even global buses used to bring an input signal into a digital PSoC block, either and one port connected to the odd global buses. -
Page 321: 44-Pin Global Interconnect
Global Digital Interconnect (GDI) 14.1.3 44-Pin Global Interconnect Because several ports are connected to a single global bus, there is a one-to-many mapping between individual nets in a For 44-pin PSoC devices, there are five 8-bit ports. There- global bus and port pins. For example, if GIO[1] is used to fore, there are up to three ports connected to the even bring an input signal into a digital PSoC block, either pin global buses and two ports connected to the odd global... -
Page 322: 48-Pin Global Interconnect
Global Digital Interconnect (GDI) 14.1.4 48-Pin Global Interconnect To determine the number of digital rows and digital blocks in your PSoC device, refer to the table titled “PSoC Device Charac- teristics” on page 311. Figure 14-4. Global Interconnect Block Diagram for the CY8C286xx 48-Pin Package GOE[7] GOE[5] GOE[3]... -
Page 323: 56-Pin Global Interconnect
Global Digital Interconnect (GDI) 14.1.5 56-Pin Global Interconnect The CY8C28xxx 56-pin PSoC device is only for OCD pur- poses. Therefore the 56-pin global connection is the same as the CY8C28xxx 44-pin package. 14.2 Register Definitions The following registers are associated with the Global Digital Interconnect and are listed in address order. Each register description has an associated register table showing the bit structure for that register. -
Page 324: Gdi_X_Ou/Gdi_X_Ou_Cr Registers
Global Digital Interconnect (GDI) Bits 7 to 0: GDIxICRx. Using the configuration bits in the GDI_x_IN_CR registers, a global input net may be config- Table 14-4. GDI_x_IN_CR Register ured to drive its corresponding next global output net. For example, 0: Data source is GIx[0] GDI_xICR[0] 1: Data source is GIx[7] GIE 7 ... - Page 325 Global Digital Interconnect (GDI) For additional information, refer to the GDI_O_OU register There are a total of 16 bits that control the ability of global on page 288 and the GDI_E_OU register on page 289. outputs to drive global inputs. These bits are in the GDI_x_OU_CR registers.
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Page 326: Array Digital Interconnect (Adi)
15. Array Digital Interconnect (ADI) ® This chapter presents the Array Digital Interconnect (ADI). The digital PSoC array uses a scalable architecture that is designed to support from one to four digital PSoC rows, as defined in the Row Digital Interconnect (RDI) chapter on page 327. - Page 327 Array Digital Interconnect (ADI) Figure 15-1, the detailed view of a Digital PSoC block row has been replaced by a box labeled digital PSoC block row x. The rest of this figure illustrates how all rows are con- nected to the same globals, clocks, and so on. The figure also illustrates how the broadcast clock nets (BCrowx) are connected between rows.
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Page 328: Row Digital Interconnect (Rdi)
16. Row Digital Interconnect (RDI) This chapter explains the Row Digital Interconnect (RDI) and its associated registers. This chapter discusses a single digital ® PSoC block row. It does not discuss the functions, inputs, or outputs for individual digital PSoC blocks; nor does it cover spe- cific instances of multiple rows in a single part. - Page 329 Row Digital Interconnect (RDI) As shown in Figure 16-2, there is a keeper connected to the Notice on the left side of Figure 16-2 that global inputs row broadcast net and each of the row outputs. The keeper (GIE[n] and GIO[n]) are inputs to 4-to-1 multiplexers. The sets the value of these nets to ‘1’...
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Page 330: Register Definitions
Row Digital Interconnect (RDI) 16.2 Register Definitions The following registers are associated with the Row Digital Interconnect (RDI) and are listed in address order. Each register description has an associated register table showing the bit structure for that register. For a complete table of RDI registers, refer to the “Summary Table of the Digital Registers”... -
Page 331: Rdixsyn Register
Row Digital Interconnect (RDI) 16.2.2 RDIxSYN Register Add. Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,B1h RDI0SYN 3, 2 RI3SYN RI2SYN RI1SYN RI0SYN RW : 00 x,B9h RDI1SYN 3, 2 RI3SYN RI2SYN... -
Page 332: Rdixis Register
Row Digital Interconnect (RDI) 16.2.3 RDIxIS Register Add. Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,B2h RDI0IS 3, 2 BCSEL[1:0] RW : 00 x,BAh RDI1IS 3, 2 BCSEL[1:0] RW : 00 x,C2h RDI2IS... -
Page 333: Rdixltx Registers
Row Digital Interconnect (RDI) 16.2.4 RDIxLTx Registers Add. Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,B3h RDI0LT0 3, 2 LUT1[3:0] LUT0[3:0] RW : 00 x,B4h RDI0LT1 3, 2 LUT3[3:0] LUT2[3:0] RW : 00... -
Page 334: Rdixrox Registers
Row Digital Interconnect (RDI) 16.2.5 RDIxROx Registers Add. Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,B5h RDI0RO0 3, 2 GOO5EN GOO1EN GOE5EN GOE1EN GOO4EN GOO0EN GOE4EN GOE0EN RW : 00 x,B6h RDI0RO1 3, 2... -
Page 335: Rdixdsm Register
Row Digital Interconnect (RDI) 16.2.6 RDIxDSM Register Add. Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,B7h RDI0DSM 3, 2 AVG_SEL[3:0] AVG_EN[3:0] RW : 00 x,BFh RDI1DSM 3, 2 AVG_SEL[3:0] AVG_EN[3:0] RW : 00... -
Page 336: Digital Blocks
17. Digital Blocks ® This chapter covers the configuration and use of the digital PSoC blocks and their associated registers. For a complete table of the Digital PSoC Block registers, refer to the “Summary Table of the Digital Registers” on page 312. -
Page 337: Input Multiplexers
Digital Blocks Each digital PSoC block also has three data registers (DR0, 4. Choose direct SYSCLKX2 (select SYSCLKX2 in the DR1, and DR2) and two control registers (CR0 and CR1). Clock Input field of the DxCxxIN register) for clocking The bit meanings for these registers are heavily function directly off of SYSCLKX2. -
Page 338: Clock Resynchronization Summary
Digital Blocks Table 17-1. AUXCLK Bit Selections 17.1.6 Timer Function Code Description Usage A timer consists of a period register, a synchronous down Use this setting only when SYSCLKX2 (48 MHz) is counter, and a capture/compare register, all of which are selected. -
Page 339: Usability Exceptions
Digital Blocks Table 17-2. Timer Interrupt Source Non Multi-shot Mode Multi-shot Mode Interrupt KILL_INT Capture INT Compare True KILL_INT Capture INT Compare True Source (CR1[0]) (CR0[1]) (FN[1]) (CR1[0]) (CR0[1]) (FN[1]) KILL Capture Compare Last-Shot ■ Timers may be chained in 8-bit lengths up to 32 bits. The compare output is the primary output and the Termi- nal Count (TC) is the auxiliary output (opposite of the Timer). -
Page 340: Usability Exceptions
Digital Blocks outputs are gated to zeros when KILL is asserted. For more 17.1.8 Dead Band Function detail see “Timing Diagrams” on page 363. The Dead Band function generates output signals on both The data input functions as a gate to counter operation. The the primary and auxiliary outputs of the block, see counter only counts and reloads when the data input is Figure... -
Page 341: Usability Exceptions
Digital Blocks Figure 17-3. Dead Band Functional Overview Primary Output Dead Band Function Auxiliary Output Mode bits are encoded for kill options and are detailed in the 3. If the period (of either the high time or the low time of following table. -
Page 342: Usability Exceptions
Digital Blocks ■ The comparison is DR0 > DR2, instead of DR0<= DR2 disabled and a seed value is written into DR2, the seed or DR0<DR2. Therefore the compare out waveform is value is also loaded into DR0. When the CRCPRS is reversed. -
Page 343: Usability Exceptions
Digital Blocks Figure 17-4. CRCPRS LFSR Structure SHIFT_ FB Tri-state Bus (Data input for CRC, if PRS, force to logic ‘0’.) DATA (To next block, if chained.) (From previous block DO, if chained.) SHIFT_ In Shift mode, the shift registers MSB Tri-state Bus MSB SEL is determined by a are just like a digital delay line. -
Page 344: Spi Protocol Function
Digital Blocks 17.1.11 SPI Protocol Function The Serial Peripheral Interface (SPI) is a Motorola™ specification for implementing full-duplex synchronous serial communi- cation between devices. The 3-wire protocol uses both edges of the clock to enable synchronous communication, without the need for stringent setup and hold requirements. Figure 17-5 shows the basic signals in a simple connection Figure 17-5. -
Page 345: Spi Master Function
Digital Blocks 17.1.12 SPI Master Function 17.1.12.1 Usability Exceptions The following are usability exceptions for the SPI Protocol The SPI Master (SPIM) offers SPI operating modes 0-3. By function: default, the MSb of the data byte is shifted out first. An addi- tional option can be set to reverse the direction and shift the 1. -
Page 346: Usability Exceptions
Digital Blocks When SS_ is negated, the SPIS ignores any MOSI/SCLK 17.1.13.1 Usability Exceptions input from the master. In addition, the SPIS state machine The following are usability exceptions for the SPI Slave is reset, and the MISO output is forced to idle at logic 1. This function: allows for a wired-AND connection in a multi-slave environ- ment. -
Page 347: Usability Exceptions
Digital Blocks A write to the TX Buffer register (DR1) initiates a transmis- RXD input at the center of the bit time. Every subsequent sion and an additional byte can be buffered in this register, START bit resynchronizes the clock generator to the incom- while transmission is in progress. -
Page 348: Usability Exception
Digital Blocks Figure 17-7 illustrates density signal generation flow. The initial data will be loaded into DR0 by writing it into DR1. DR2 is density register. Then DR0 = DR0 – DR2 and the registered carry out is the generated density signal output. It can go to auxiliary output. -
Page 349: Register Definitions
Digital Blocks 17.2 Register Definitions The following registers are associated with the Digital Blocks and listed in address order. Note that there are two banks of reg- isters associated with the PSoC device. Bank 0 encompasses the user registers (Data and Control registers, and Interrupt Mask registers) for the device and Bank 1 encompasses the Configuration registers for the device. -
Page 350: Dxcxxdrx Registers
Digital Blocks 17.2.1 DxCxxDRx Registers Add. Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,xxh DxCxxDR0 3, 2 Data[7:0] # : 00 0,xxh DxCxxDR1 3, 2 Data[7:0] W : 00 0,xxh DxCxxDR2 3, 2... -
Page 351: Counter Register Definitions
Digital Blocks 17.2.1.2 Counter Register Definitions There are three 8-bit Data registers and two Control registers (a 7 bit and an 8 bit). Table 17-12 explains the meaning of these registers in the context of the Counter operation. Note that the descriptions of the registers are dependent on the enable/dis- able state of the block. -
Page 352: Pwmdbl Register Definitions
Digital Blocks 17.2.1.4 PWMDBL Register Definitions There are three 8-bit Data registers and two Control registers (a 7-bit and an 8-bit). Table 17-14 explains the meaning of these registers in the context of the PWMDBL operation. The Control registers are described beginning with section 17.2.2 DxCxxCR0 Register. -
Page 353: Spi Master Register Definitions
Digital Blocks 17.2.1.6 SPI Master Register Definitions There are three 8-bit Data registers and two Control/Status registers (an 8-bit and a 7-bit). Table 17-16 explains the meaning of these registers in the context of SPIM operation. The Control registers are described beginning with section 17.2.2 DxCxxCR0 Register. -
Page 354: Receiver Register Definitions
Digital Blocks 17.2.1.9 Receiver Register Definitions There are three 8-bit Data registers and one 8-bit Control/Status register. Table 17-19 explains the meaning of these registers in the context of Receiver operation. The Control registers are described beginning with section 17.2.2 DxCxxCR0 Register. - Page 355 Digital Blocks Add. Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access DxCxxCR0 KILL[3:0] DR2BufEN Enable 0,xxh (Counter 3, 2 RW : 00 Control:001) LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary”...
- Page 356 Digital Blocks Add. Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access DCCxxCR0 SPI Com- TX Reg Clock Clock Polar- 0,xxh (SPIM Con- 4, 3, 2, 1 LSb First Overrun RX Reg Full Enable # : 00...
- Page 357 Digital Blocks Add. Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access DxCxxCR0 KILL_SEL[3:0] Enable 0,xxh (DSM Con- 3, 2 RW : 00 trol:111) LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary”...
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Page 358: Dxcxxcr1 Register
Digital Blocks 17.2.3 DxCxxCR1 Register The DxCxxCR1 registers are the digital blocks’ Control registers (located in bank 1 of the PSoC device’s memory map). The bits for the following registers are described by function in Table 17-22. Add. Name Rows Bit 7 Bit 6 Bit 5... - Page 359 Digital Blocks Add. Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access DxCxxCR1 1,xxh (SPIM Con- 3, 2 Chain SPI Length RW : 00 trol:0-110) LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary”...
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Page 360: Int_Msk1 Register
Digital Blocks Interrupt Mask Registers The following are the interrupt mask registers for the digital blocks. 17.2.4 INT_MSK1 Register Add. Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,E1h INT_MSK1 3, 2 DCC13... -
Page 361: Dxcxxfn Registers
Digital Blocks Configuration Registers The configuration block contains 3 registers: Function (DxCxxFN), Input (DxCxxIN), and Output (DxCxxOU). The values in these registers should not be changed while the block is enabled. Note that the Digital Block Configuration registers are all located in bank 1 of the PSoC device’s memory map. -
Page 362: Dxcxxin Registers
Digital Blocks 17.2.6 DxCxxIN Registers Add. Name Rows Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,xxh DxCxxIN 4, 3, 2, 1 Data Input[3:0] Clock Input[3:0] RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, refer to the “Digital Register Summary”... - Page 363 Digital Blocks Table 17-26. Digital Block Output Definitions The following table summarizes the available selections of the AUXCLK bits. Outputs Function Primary Auxiliary Interrupt Table 17-27. AUXCLK Bit Selections Terminal Count or Last-shot or Com- Timer Terminal Count Compare Code Description Usage pare True or Cap-...
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Page 364: Timing Diagrams
Digital Blocks 17.3 Timing Diagrams The timing diagrams in this section are presented according to their functionality and are in the following order. ■ ■ “Timer Timing” on page 363 “SPIM Timing” on page 371 ■ “Counter Timing” on page 366 ■... - Page 365 Digital Blocks Figure 17-10. Last-shot meets IOW Multi-Shot Counter Multi-Shot Counter Last-Shot Last-Shot Last shot takes IOW enable takes ENCLR (internal) ENCLR (internal) over the control over the control IOW_ IOW_ IOW disable IOW enable CMP OUT CMP OUT If the ENCLR and IOW enable occur simultaneously, the Figure 17-12.
- Page 366 Digital Blocks Figure 17-13. Multi-Block Timing Reload occurs Example of multi-block timer counting when all blocks MSB Period = k, ISB Period = m, LSB Period = n reach Terminal Count (TC). Count LSB Zero Detect LSB Carry Out LSB Count ISB Zero Detect ISB Carry Out ISB...
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Page 367: Counter Timing
Digital Blocks 17.3.2 Counter Timing Enable/Disable Operation. See Timer “Enable/Disable Operation” on page 363. Terminal Count/Compare Operation. See Timer “Termi- nal Count/Compare Operation” on page 363. Multi-Shot Operation. See Timer “Multi-shot Operation” on page 363. KILL-Disable Operation. See Timer “KILL Disable Opera- tion”... -
Page 368: Dead Band Timing
Digital Blocks 17.3.3 Dead Band Timing Figure 17-16. Basic Dead Band Timing A PWM reference edge A Bit Bang clock can occur running on the same anywhere up to one 24 A high on the reference clock occurs here. MHz clock, before the next asserts PH1, a low PHI2. -
Page 369: Kill Operation
Digital Blocks Figure 17-19. PWM Width Equal to Dead Band Period Figure 17-20. Synchronous Restart KILL Mode Short KILL, outputs off for Operation resumes on remainder of current cycle. the next PWM edge. PHI1 REFERENCE PHI2 PHI1 PHI2 KILL In the case where the dead band period is greater than the high or low of the PWM reference, the output of the associ- Operation resumes Output is off for duration... -
Page 370: Pwmdbl Timing
Digital Blocks 17.3.4 PWMDBL Timing In any other condition, the START signal does not affect PWMDBL. To ensure safe timing, START is synchronized at the rising edge of the block clock. See Figure 17-22. Enable/Disable Operation. See Timer “Enable/Disable Operation” on page 363. -
Page 371: Crcprs Timing
Digital Blocks 17.3.5 CRCPRS Timing 17.3.6 SPI Mode Timing Figure 17-24 shows the SPI modes, which are typically Enable/Disable Operation. See Timer “Enable/Disable defined as 0,1, 2, or 3. These mode numbers are an encod- Operation” on page 363. ing of two control bits: Clock Phase and Clock Polarity. Multi-Shot Operation in PRS. -
Page 372: Spim Timing
Digital Blocks 17.3.7 SPIM Timing Enable/Disable Operation. As soon as the block is config- Normal Operation. Typical timing for a SPIM transfer is ured for SPIM, the primary output is the MSb or LSb of the shown in Figure 17-25 Figure 17-26. - Page 373 Digital Blocks Figure 17-26. Typical SPIM Timing in Mode 2 and 3 Last bit of received Shifter is loaded Free running, data is valid on this with the next Shifter is loaded Setup time internal bit rate edge and is latched byte.
- Page 374 Digital Blocks Figure 17-27. SPI Status Timing for Modes 0 and 1 SS Forced Low Transfer in Progress SCLK (Mode 0) SCLK (Mode 1) SS Toggled on a Message Basis Transfer in Progress Transfer in Progress SCLK (Mode 0) SCLK (Mode 1) SS Toggled on Each Byte Transfer in Progress Transfer in Progress...
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Page 375: Spis Timing
Digital Blocks Chained SPIM. When two adjacent communication blocks the primary output is the MSb or LSb of the shift register, are chained to form a more-than-8-bit SPIM function, the depending on the LSb First configuration in bit 7 of the Con- preceding operations are maintained the same, with the fol- trol register. - Page 376 Digital Blocks Figure 17-30. Typical SPIS Timing in Modes 2 and 3 Shifter is loaded with Last bit of received data is valid Shifter is first byte (by leading on this edge and is latched into loaded with First edge of the SCLK). the RX Buffer register.
- Page 377 Digital Blocks Figure 17-31. Mode 0 and 1 Transfer in Progress SS Forced Low Transfer in Progress SCLK (Mode 0) SCLK (Mode 1) SS Toggled on a Message Basis Transfer in Progress Transfer in Progress SCLK (Mode 0) SCLK (Mode 1) SS Toggled on Each Byte Transfer in Progress Transfer in Progress...
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Page 378: Transmitter Timing
Digital Blocks 17.3.9 Transmitter Timing When the block is disabled, the clock is immediately gated low. All internal state is reset (including CR0 status) to its configuration-specific reset state, except for DR0, DR1, and Enable/Disable Operation. As soon as the block is config- DR2 which are unaffected. - Page 379 Digital Blocks Figure 17-34 shows a detail of the Tx Buffer load timing. The TX Reg Empty indicates that a new byte can be written to data bits are shifted out on each of the subsequent clocks. the TX Buffer register. When the block is enabled, this status Following the eighth bit, if parity is enabled, the parity bit is bit is immediately asserted.
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Page 380: Receiver Timing
Digital Blocks 17.3.10 Receiver Timing Enable/Disable Operation. As soon as the block is config- up-count. The block clock is derived from the MSb of this ured for Receiver and before enabling, the primary output is counter (corresponding to a count of four), which serves to connected to the data input (RXD). - Page 381 Digital Blocks Clock Generation and Start Detection. The input clock count at the eight times rate. If the RXD input is still logic 0 selection is a free running, eight times over-sampling clock. after three samples of the input clock, the status RXACTIVE This clock is used by the clock divider circuit to generate the is asserted, which initiates a reception.
- Page 382 Digital Blocks This resynchronization process (forcing the state back to Status Generation. There are five status bits in a Receiver idle) occurs regardless of the value of the STOP bit sample. block: RX Reg Full, RX Active, Framing Error, Overrun, and It is important to reset as soon as possible, so that maximum Parity Error.
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Page 383: Dsm Timing
Digital Blocks Status Clear On Read. Refer to the SPIM subsection in “SPIM Timing” on page 371. Figure 17-39. Status Timing for Receiver All status, except Overrun, is set synchronously with the STOP bit sample point. STOP CCLK STATE IDLE START BIT0 BIT1... -
Page 384: Section E: Analog System
Section E: Analog System ® The configurable Analog System section discusses the analog components of the PSoC device and the registers associated with those components. Note that the analog output drivers are described in the PSoC Core section, Analog Output Drivers chapter on page 79, because they are part of the core input and output signals. - Page 385 Analog System Block Diagram for CY8C28x23 Devices Analog System Block Diagram for CY8C28x33 Devices P0[7] All GPIO P0[5] P0[7] P0[6] P0[3] P0[5] P0[4] P0[6] P0[1] P0[3] P0[2] P2[3] P0[4] P0[1] P0[0] P2[1] P0[2] P2[3] P2[6] P0[0] P2[1] P2[4] P2[6] P2[4] Array Input Configuration Array Input Configuration...
- Page 386 Analog System Block Diagram for CY8C28x43 Devices All GPIO P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] P2[6] P2[3] P2[4] P2[1] P2[2] P2[0] Array Input Configuration ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI3[1:0] Block Array ACC00 ACC01 ACC02 ACC03 ASC10 ASD11 ASC12 ASD13 ASD20 ASC21 ASD22...
- Page 387 Analog System Block Diagram for CY8C28x45 and CY8C28x52 Devices All GPIO P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] P2[6] P2[3] P2[4] P2[1] P2[2] P2[0] Array Input Configuration ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI3[1:0] ACI4[1:0] ACI5[1:0] Block Array ACC00 ACC01 ACC02 ACC03 ACE00 ACE01 ASC10...
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Page 388: Interpreting The Analog Documentation
Interpreting the Analog Defining the Analog Blocks Documentation There are three analog PSoC block types: Continuous Time (CT) blocks, and Type C and Type D Switch Capacitor (SC) Information in this section covers all PSoC devices with a blocks. CT blocks provide continuous time analog functions. base part number of CY8C28xxx. -
Page 389: Analog Functionality
Analog Functionality The following is a sampling of the functions that operate within the capability of the analog PSoC blocks, using one analog PSoC block, multiple analog blocks, a combination of more than one type of analog block, or a combination of analog and digital PSoC blocks. -
Page 390: Analog Register Summary
Analog Register Summary The following table lists all the PSoC registers for the analog system in address order (Add. column) within their system resource configuration. The bits that are grayed out are reserved bits. If these bits are written, they should always be written with a value of ‘0’. - Page 391 Summary Table of the Analog Registers (continued) Analog Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Cols. 0,74h ACC01CR3 4, 2 AGND_PD RTopMux1 LPCMPEN CMOUT INSAMP EXGAIN RW : 00 0,75h ACC01CR0 4, 2...
- Page 392 Summary Table of the Analog Registers (continued) Analog Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Cols. 0,9Eh ASC23CR2 AnalogBus CompBus AutoZero CCap[4:0] RW : 00 0,9Fh ASC23CR3 ARefMux[1:0] FSW1 FSW0 BMuxSC[1:0]...
- Page 393 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
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Page 394: Analog Interface
18. Analog Interface This chapter explains the Analog Interface and its associated registers. The analog system interface is a collection of system level interfaces to the analog array and analog reference block. For a complete table of the analog interface registers, refer to ®... -
Page 395: Analog Data Bus Interface
Analog Interface 18.1.1 Analog Data Bus Interface logic functions for those inputs. The LUT A and B inputs for each column comparator output is shown in the following The Analog Data Bus Interface isolates the analog array and table. analog system interface registers from the CPU system data bus, to reduce bus loading. -
Page 396: Column Clock Synchronization
Analog Interface The settings for the digital block selection are located in reg- 18.1.4 Decimator and Incremental ADC ister CLK_CR1 and the register CLK_CR2. Interface The timing for analog column clock generation is shown in The Decimator and Incremental ADC Interface provides Figure 18-2. -
Page 397: Analog Modulator Interface (Mod Bits)
Analog Interface The ICLKS bits, which are split between the DEC_CR0 and Figure 18-4. Synchronized Write to a DAC Register DEC_CR1 registers, are used to select a source for the Stall is released here. incremental gating signal. The four IGEN bits are used to CPUCLK independently enable the gating function on a column-by- (Generated) -
Page 398: Application Description
Analog Interface Figure 18-5. SAR Hardware Accelerator System Analog Data Bus Data Bus Read Switched Capacitor Block Micro SAR Accelerator DAC Register Input Mux Accelerator Latch Comparator Bus Outputs CBUS Analog from Other Driver Input Columns PHI1 or PHI2 As shown in Figure 18-5, the SAR accelerator hardware is The SAR hardware is designed to process six bits of a result... - Page 399 Analog Interface The programming for the DAC6 block is as follows: initializes this register to ‘6’. When these bits are any value other than ‘0’, an IOR command to an SC block is assumed to be part of a SAR sequence. CR0: mov reg[ASC10CR0], a0h // Full Feedback, ACap Value = >...
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Page 400: Sar Timing
Analog Interface Table 18-4. SAR Sequence Example Comparator Step Current ACap VDac VSum New ACap Comment Bus (CMP) 100000 2.75 110000 Keep the sign bit and set bit 4. 110000 1.875 2.4375 101000 Overshoot , clear bit 4, set bit 3. 101000 2.1875 2.59375... -
Page 401: Register Definitions
Analog Interface register is written with the new value within a few CPU positive edge of PHI1 to the start of the I/O write is 4.5 clocks after PHI1. clocks, which at 24 MHz is 189 ns. If the analog clock is run- ning at 1 MHz, this allows over 300 ns for the DAC output The rising edge of PHI1 is also the optimal time to write the and comparator to settle. -
Page 402: Cmp_Cr0 Register
Analog Interface 18.3.2 CMP_CR0 Register Add. Name Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,64h CMP_CR0 COMP[3:0] AINT[3:0] # : 00 COMP[1:0] AINT[1:0] #: Access is bit specific. Refer to the Register Details chapter on page 125. -
Page 403: Asy_Cr Register
Analog Interface 18.3.3 ASY_CR Register Add. Name Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,65h ASY_CR 4, 2 SARCNT[2:0] SARSIGN SARCOL[1:0] SYNCEN RW : 00 The Analog Synchronization Control Register (ASY_CR) is Bit 3: SARSIGN. -
Page 404: Cmp_Cr1 Register
Analog Interface 18.3.4 CMP_CR1 Register Add. Name Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access CLDIS[3] CLDIS[2] CLDIS[1] CLDIS[0] 0,66h CMP_CR1 RW : 00 CLDIS[1] CLDIS[0] CLK1X[1] CLK1X[0] The Analog Comparator Bus Register 1 (CMP_CR1) is used Bits 1 and 0: CLK1X[1:0]. -
Page 405: Dec_Cr1 Register
Analog Interface 18.3.6 DEC_CR1 Register Address Name Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access IDEC ICLKS3 ICLKS2 ICLKS1 DCLKS3 DCLKS2 DCLKS1 RW : 00 0,E7h DEC_CR1 IDEC ICLKS3 ICLKS2 ICLKS1 DCLKS3 DCLKS2... -
Page 406: Clk_Cr1 Register
Analog Interface 18.3.8 CLK_CR1 Register Add. Name Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,61h CLK_CR1 4, 2 SHDIS ACLK1[2:0] ACLK0[2:0] RW : 00 The Analog Clock Source Control Register 1 (CLK_CR1) is The following are the exceptions: 1) If the ClockPhase bit in used to select the clock source for an individual analog col- ASCxx_CR0 (for the SC block in question) is set to ‘1’, then... -
Page 407: Cmp_Go_En Register
Analog Interface 18.3.10 CMP_GO_EN Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,64h CMP_GO_EN GOO5 GOO1 SEL1[1:0] GOO4 GOO0 SEL0[1:0] RW : 00 The Comparator Bus to Global Outputs Enable Register Bit 3: GOO4. -
Page 408: Amd_Cr1 Register
Analog Interface 18.3.12 AMD_CR1 Register Add. Name Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access AMOD3[2:0] AMOD1[2:0] 1,66h AMD_CR1 RW : 00 AMOD1[2:0] The Analog Modulation Control Register 1 (AMD_CR1) is one broadcast bus. -
Page 409: Clk_Cr2 Register
Analog Interface 18.3.15 CLK_CR2 Register Add. Name Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,69h CLK_CR2 ACLK1R ACLK0R RW : 00 The Analog Clock Source Control Register 2 (CLK_CR2), in Bit 0: ACLK0R. -
Page 410: Analog Array
19. Analog Array This chapter presents the Analog Array, which has no registers directly associated with it. This chapter is important because it ® discusses the block and column level interconnects that exist in the analog PSoC array. 19.1 Architectural Description Figure 19-1. -
Page 411: Nmux Connections
Analog Array 19.1.1 NMux Connections The NMux is an 8-to-1 mux which determines the source for The numbers in Figure 19-2, which are associated with each the inverting (also called negative) input of Continuous Time arrow, are the corresponding NMux select line values for the PSoC blocks. -
Page 412: Pmux Connections
Analog Array 19.1.2 PMux Connections The PMux is an 8-to-1 mux which determines the source for The numbers in Figure 19-3, which are associated with each the non-inverting (also called positive) input of Continuous arrow, are the corresponding PMux select line values for the Time PSoC blocks. -
Page 413: Rbotmux Connections
Analog Array 19.1.3 RBotMux Connections The RBotMux connections in Figure 19-4 are the mux inputs Mux bits (ACC0xCR0 bits 1 and 0) and the INSAMP bit for the bottom of the resistor string, see Figure 22-1 on (ACC0xCR3 bit 1). For example, the RBotMux selects a page 426. -
Page 414: Amux Connections
Analog Array 19.1.4 AMux Connections The AMux connections in Figure 19-5 are the mux inputs for The numbers in Figure 19-5, which are associated with each controlling both the A and C capacitor branches. The high arrow, are the corresponding AMux select line values for the order bit, ACMux[2], selects one of two inputs for the C data in the ACMux portion of the register. -
Page 415: Cmux Connections
Analog Array 19.1.5 CMux Connections The CMux connections in Figure 19-6 are the mux inputs for The CMux connections are described in detail in the controlling the C capacitor branches. The high order bit, ASCxxCR1 register on page 162, bits ACMux[2:0]. The ACMux[2], selects one of two inputs for the C branch, which numbers in the figure, which are associated with each arrow, is used to control both the AMux and CMux. -
Page 416: Bmux Sc/Sd Connections
Analog Array 19.1.6 BMux SC/SD Connections The BMux SC/SD connections in Figure 19-7 are the mux data in the BMux portion of the register. The call out names inputs for controlling the B capacitor branches. (See in the figure show nets selected for each BMux value. Figure 23-1 on page 432 Figure 23-2 on page 433.) The... -
Page 417: Analog Comparator Bus
Analog Array 19.1.7 Analog Comparator Bus Each analog column has a dedicated comparator bus asso- ciated with it. Every analog PSoC block has a comparator output that can drive out on this bus. However, the compara- tor output from only one analog block in a column can be actively driving the comparator bus for that column at any one time. -
Page 418: Analog Input Configuration
20. Analog Input Configuration This chapter discusses the Analog Input Configuration and its associated registers. For a complete table of analog input con- ® figuration registers, refer to the “Summary Table of the Analog Registers” on page 389. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 125. -
Page 419: Six Column Analog Input Configuration
Analog Input Configuration 20.1.1 Six Column Analog Input Configuration The six column analog input configuration is detailed in Figure 20-2, along with the analog driver and pin specifics. Figure 20-2. Six Column PSoC Analog Pin Block Diagram P0[7] P0[6] P0[4] P0[5] P0[3] P0[2]... -
Page 420: Register Definitions
Analog Input Configuration 20.2 Register Definitions The following registers are associated with Analog Input Configuration and are listed in address order. Each register descrip- tion has an associated register table showing the bit structure for that register. For a complete table of the analog input config- uration registers, refer to the “Summary Table of the Analog Registers”... -
Page 421: Abf_Cr0 Register
Analog Input Configuration 20.2.2 ABF_CR0 Register Add. Name Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access ACol1Mux ACol2Mux ABUF1EN ABUF2EN ABUF0EN ABUF3EN Bypass 1,62h ABF_CR0 RW : 00 ACol1Mux ABUF1EN ABUF0EN Bypass The Analog Output Buffer Control Register 0 (ABF_CR0) -
Page 422: Analog Reference
21. Analog Reference This chapter discusses the Analog Reference generator and its associated register. The reference generator establishes a ® set of three internally fixed reference voltages for AGND, RefHi, and RefLo. For PSoC devices with one analog column, a fixed analog ground (AGND) of Vdd/2 is supplied. -
Page 423: Register Definitions
Analog Reference 21.2 Register Definitions The following register is associated with the Analog Reference. For a complete table of all analog registers, refer to the “Sum- mary Table of the Analog Registers” on page 389. The register description below has an associated register table showing the bit structure. Depending on how many analog col- umns your PSoC device has (see the Cols. - Page 424 Analog Reference Table 21-2. REF[2:0]: AGND, RefHI, and RefLO Operating Parameters for 4 and 2 Column PSoC Devices AGND RefHI RefLO Notes [2:0] Source Voltage Source Voltage Source Voltage 2.5 V 3.8 V 1.2 V 5.0 V System 000b Vdd/2 Vdd/2 + Vbg Vdd/2 –...
- Page 425 Analog Reference CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
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Page 426: Continuous Time Psoc ® Block
® 22. Continuous Time PSoC Block ® This chapter discusses the Analog Continuous Time PSoC Block and its associated registers. This block supports program- mable gain or attenuation opamp circuits; instrumentation amplifiers, using two CT blocks (differential gain); and modest response-time analog comparators. -
Page 427: Register Definitions
® Continuous Time PSoC Block Figure 22-1. Analog Continuous Time Block Diagram TestMux LPCMPEN RefHi RefLo AGND Gain ABUS AnalogBus CompCap PMuxOut CBUS Latch Block Inputs CBUS Driver Port Input Transparent, PHI1 or PHI2 ABUS GOUT AGND PMux RefHi RTopMux1, NMux RTopMux Block Inputs... -
Page 428: Accxxcr3 Register
® Continuous Time PSoC Block 22.2.1 ACCxxCR3 Register Add. Name Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,70h ACC00CR3 4, 2 AGND_PD RTopMux1 LPCMPEN CMOUT INSAMP EXGAIN RW : 00 0,74h ACC01CR3 4, 2... - Page 429 ® Continuous Time PSoC Block Figure 22-3. Three-Opamp Instrumentation Amplifier 1st CT Block PHI1 PHI1 PHI2 CMOUT PHI2 ABUS INSAMP PHI1 INSAMP CMOUT PHI2 ABUS SC Block PHI1 Type C or D 2nd CT Block GAIN = Bit 0: EXGAIN. The continuous time block’s resistor tap is Figure 22-4.
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Page 430: Accxxcr0 Register
® Continuous Time PSoC Block 22.2.2 ACCxxCR0 Register Add. Name Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,71h ACC00CR0 4, 2 RTapMux[3:0] Gain RTopMux RBotMux[1:0] RW : 00 0,75h ACC01CR0 4, 2 RTapMux[3:0]... -
Page 431: Accxxcr2 Register
® Continuous Time PSoC Block 22.2.4 ACCxxCR2 Register Add. Name Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,73h ACC00CR2 4, 2 CPhase CLatch CompCap TMUXEN TestMux[1:0] PWR[1:0] RW : 00 0,77h ACC01CR2 4, 2... -
Page 432: Switched Capacitor Psoc ® Block
® 23. Switched Capacitor PSoC Block This chapter presents the Analog Switched Capacitor Block and its associated registers. The analog Switched Capacitor (SC) ® blocks are built around a low offset, low noise operational amplifier. For a complete table of the Switched Capacitor PSoC Block registers, refer to the “Summary Table of the Analog Registers”... - Page 433 ® Switched Capacitor PSoC Block Figure 23-1. Analog Switch Cap Type C PSoC Blocks *AutoZero BQTA FCap 16,32 0,1,…,30,31 C +!AutoZero) * FSW1 C Inputs * FSW0 ACMux ACap 0,1,…,30,31 C +AutoZero A Inputs RefHi ...
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Page 434: Application Description
® Switched Capacitor PSoC Block Figure 23-2. Analog Switch Cap Type D PSoC Blocks *AutoZero FCap 16,32 0,1,…,30,31 C +!AutoZero) BQTA * FSW1 * FSW0 A Mux ACap 0,1,…,30,31 C +AutoZero A Inputs RefHi ... -
Page 435: Register Definitions
® Switched Capacitor PSoC Block 23.3 Register Definitions The following registers are associated with the Switched Capacitor (SC) PSoC Block and are listed in address order. Each register description has an associated register table showing the bit structure for that register. For a complete table of SC PSoC Block registers, refer to the “Summary Table of the Analog Registers”... -
Page 436: Ascxxcr0 Register
® Switched Capacitor PSoC Block Analog Switch Cap Type C PSoC Block Control Registers In the tables below, an “x” before the comma in the address field (in the “Add.” column) indicates that the register exists in both register banks. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m = row index and n = column index. -
Page 437: Ascxxcr1 Register
® Switched Capacitor PSoC Block 23.3.2 ASCxxCR1 Register Add. Name Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,81h ASC10CR1 4, 2 ACMux[2:0] BCap[4:0] RW : 00 0,89h ASC12CR1 ACMux[2:0] BCap[4:0] RW : 00 0,95h... -
Page 438: Ascxxcr3 Register
® Switched Capacitor PSoC Block 23.3.4 ASCxxCR3 Register Add. Name Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,83h ASC10CR3 4, 2 ARefMux[1:0] FSW1 FSW0 BMuxSC[1:0] PWR[1:0] RW : 00 0,8Bh ASC12CR3 ARefMux[1:0]... -
Page 439: Asdxxcr0 Register
® Switched Capacitor PSoC Block Analog Switch Cap Type D PSoC Block Control Registers In the tables below, an “x” before the comma in the address field (in the “Add.” column) indicates that the register exists in both register banks. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m = row index and n = column index. -
Page 440: Asdxxcr1 Register
® Switched Capacitor PSoC Block 23.3.6 ASDxxCR1 Register Add. Name Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,85h ASD11CR1 4, 2 AMux[2:0] BCap[4:0] RW : 00 0,8Dh ASD13CR1 AMux[2:0] BCap[4:0] RW : 00 0,91h... -
Page 441: Asdxxcr3 Register
® Switched Capacitor PSoC Block 23.3.8 ASDxxCR3 Register Add. Name Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,87h ASD11CR3 4, 2 ARefMux[1:0] FSW1 FSW0 BMuxSD PWR[1:0] RW : 00 0,8Fh ASD13CR3 ARefMux[1:0]... -
Page 442: Two Column Limited Analog System
24. Two Column Limited Analog System ® This chapter explains the Two Column Limited Analog System PSoC devices and their associated registers. It details the entire analog system for two column limited functionality, including the analog interface, analog array, analog input configura- tion, analog reference, CT and SC blocks. -
Page 443: Analog Comparator Bus Interface
Two Column Limited Analog System 24.1.1.1 Analog Comparator Bus Interface Table 24-2. RDIxLTx Register 0h: 0000: FALSE Each analog column has a dedicated comparator bus asso- 1h: 0001: A .AND. B ciated with it. In the CY8C28xxx, PSoC devices, only the 2h: 0010: A .AND. - Page 444 Two Column Limited Analog System Figure 24-2. Single Slope ADC Block Diagram PWM output controls the ramp on time and discharge off time. Counter Synchronized PWM is gated with analog Dedicated comparator to ADC PWM To Column INT enable the Counter. Falling edge of selected PWM is routed to column interrupt to signal end-of-conversion.
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Page 445: Pwm Adc Interface
Two Column Limited Analog System 24.1.1.4 PWM ADC Interface 24.1.1.5 Analog Modulator Interface (Mod Bits) The analog interface provides hardware support and signal routing for analog-to-digital (ADC) conversion functions, The Analog Modulator Interface provides a selection of sig- specifically the single slope ADC. The control signals for this nals that are routed to either of the two analog array modula- interface are split between three registers: DEC_CR0, tion control signals. -
Page 446: Analog Array
Two Column Limited Analog System 24.1.2 Analog Array Figure 24-4. Array of Limited Analog PSoC Block The analog array is designed to allow moving between fami- 2 Column CY8C28x13 lies without modifying projects, except for resource limita- PSoC Device tions. The CY8C28x13 PSoC devices have limited analog array functionality. -
Page 447: Pmux Connections
Two Column Limited Analog System 24.1.2.2 PMux Connections The PMux is an 8-to-1 mux which determines the source for the non-inverting (also called positive) input of CT PSoC blocks (ACE00 and ACE01). More details on the CT PSoC blocks are available in this chapter, in the section titled “Continuous Time PSoC Block”... - Page 448 Two Column Limited Analog System Figure 24-7. Limited Two Column Analog Interconnect ColumnInterrupt COMP0 Decimator CBSRC Blocks AINT0 (ACE_ADCx_CR) (ACE_CMP_CR0) CompBusOutput0 IGEN0 (DEC_CR0) LUT0 (ACE_ALT_CR0) (ACE_CMP_GI_EN) CLDIS0 (ACE_CMP_CR1) GIO4 Sync GIO0 Sync ACE00 PMux NMux ACE00CR1 CompBus ACE00CR2 ASE10 1 = Open SHEN ENADC LOREN...
- Page 449 Two Column Limited Analog System Figure 24-8. Two Column Limited Analog Pin Block Diagram for the CY8C28xxx (28-Pin and 44-Pin Part) 28 Pin Part P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0] P2[7] P2[6] P2[5]...
- Page 450 Two Column Limited Analog System Figure 24-9. Two Column Limited Analog Pin Block Diagram for the CY8C28xxx P0[7] P0[6] 8 Pin Part P0[5] P0[4] P0[3] P0[2] P0[1] P0[0] 16 and Higher Pin Part Array Input Configuration ACI4[1:0] ACI5[1:0] ACM4 ACM5 ACE0MUX ACE1MUX Array...
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Page 451: Analog Reference
Two Column Limited Analog System 24.1.4 Analog Reference 24.1.5 Continuous Time PSoC Block The PSoC device is a single supply part, with no negative The CY8C28xxx Continuous Time blocks (Type ACE) are voltage available or applicable. The limited analog columns built around a low power, low offset amplifier. - Page 452 Two Column Limited Analog System 1. The continuous time (CT) blocks of the limited analog column in the CY8C28xxx PSoC devices differ from other PSoC devices in the following ways: ❐ The CT amplifier can only be configured as unity gain or open loop (comparator).
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Page 453: Register Definitions
Two Column Limited Analog System 24.3 Register Definitions The following registers are associated with the CY8C28xxx PSoC devices and are listed in address order within their system resource configuration. For a complete table of all analog system registers for all other PSoC devices, refer to the “Summary Table of the Analog Registers”... -
Page 454: Dec_Cr0 Register
Two Column Limited Analog System Analog Interface Registers 24.3.2 DEC_CR0 Register Add. Name Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,E6h DEC_CR0 4, 2 ACC_IGEN[3:0] ICLKS[0] ACE_IGEN[1:0] DCLKS0 RW : 00 The Decimator Control Register 0 (DEC_CR0) contains con- Bits 2 and 1: ACE_IGEN[1:0]. -
Page 455: Adcx_Tr Register
Two Column Limited Analog System 24.3.4 ADCx_TR Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,E5h ADC0_TR CAPVAL_[7:0] RW : 00 1,E6h ADC1_TR CAPVAL_[7:0] RW : 00 The ADC Column 0 and Column 1 Trim Register is accomplished by matching the ramp time to the desired (ADCx_TR) controls a combination of capacitor and current full-scale conversion period, which is dependent on clock... -
Page 456: Ace_Cmp_Cr0 Register
Two Column Limited Analog System 24.3.7 ACE_CMP_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,76h COMP[5:4] AINT[5:4] RW : 00 ACE_CMP_CR0 The Analog Type-E Comparator Bus 0 Register is used to Bits 1 and 0: AINT[5:4]. -
Page 457: Ace_Alt_Cr0 Register
Two Column Limited Analog System 24.3.10 ACE_ALT_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,7Ah LUT5[3:0] LUT4[3:0] RW : 00 ACE_ALT_CR0 The Analog LUT Control Register is used to select the logic Table 24-1 shows the available functions, where the A input function. -
Page 458: 1,7Eh Ace00Cr2
Two Column Limited Analog System 24.3.13 ACExxCR2 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,7Eh ACE00CR2 FullRange RW : 00 1,8Eh * ACE01CR2 FullRange RW : 00 The Analog Continuous Time Type E Block Control Register Bit 0: PWR. -
Page 459: Ace_Pwm_Cr
Two Column Limited Analog System 24.3.16 ACE_PWM_CR Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,85h HIGH[2:0] LOW[1:0] PWMEN RW : 00 ACE_PWM_CR The ADC PWM Control Register controls the parameters for When this bit is enabled, the following two scenarios can the dedicated ADC PWM. -
Page 460: Ace_Clk_Cr0
Two Column Limited Analog System 24.3.18 ACE_CLK_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,89h AColumn5[1:0] AColumn4[1:0] RW : 00 ACE_CLK_CR0 The Type-E Analog Column Clock Control Register 0 is There are four selections for each clock: VC1, VC2, ACLK0, used to select the clock source for an individual analog col- and ACLK1. - Page 461 Two Column Limited Analog System CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
- Page 462 Section F: System Resources ® The System Resources section discusses the system resources that are available for the PSoC device and the registers associated with those resources. This section encompasses the following chapters: ■ Digital Clocks on page 465 ■ Internal Voltage Reference on page 511 ■...
- Page 463 System Resources Register Summary The following table lists all the PSoC registers for the system resources, in address order, within their system resource config- uration. The bits that are grayed out are reserved bits. If these bits are written, they should always be written with a value of ‘0’.
- Page 464 Summary Table of the System Resource Registers (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,9Ah DEC_CR5 DSCLK[3:0] RW : 00 1,9Dh DEC3_CR0 GOOO GOOE DATA_IN[2:0] RW : 00 1,D4h DEC0_CR Mode[1:0]...
- Page 465 Summary Table of the System Resource Registers (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 10-BIT SAR ADC CONTROLLER REGISTERS (page 541) 0,6Ah SADC_DH Data High[7:0] R : 00 0,6Bh SADC_DL Data Low[7:0]...
- Page 466 25. Digital Clocks This chapter discusses the Digital Clocks and their associated registers. It serves as an overview of the clocking options ® available in the PSoC devices. For detailed information on specific oscillators, see the individual oscillator chapters in the ®...
- Page 467 Digital Clocks Figure 25-1. Overview of PSoC Clock Sources P1[4] SYSCLKX2 Disable (EXTCLK Input) PLL Lock Enable IMO Trim Register OSC_CR2[0] OSC_CR0[6] IMO_TR[7:0] Clock SYSCLKX2 Doubler Internal Main Oscillator Phase OSC_CR2[2] (IMO) Locked SYSCLK Loop EXTCLK (PLL) Clock Divider CPU_SCR1[4] OSC_CR0[2:0] Slow IMO Option CPUCLK...
- Page 468 Digital Clocks 25.1.3 32.768 kHz Crystal Oscillator Figure 25-2. Operation of the Clock Doubler 21 ns Nominal The PSoC may be configured to use an external crystal. The crystal oscillator is discussed in detail in the chapter “Exter- nal Crystal Oscillator (ECO)” on page Extenal Clock 25.1.4 External Clock...
- Page 469 Digital Clocks Figure 25-3. Switch from IMO to the External Clock with a CPU Clock Divider of Two or Greater Extenal Clock SYSCLK CPUCLK IOW_ EXTCLK bit IMO is External clock is deselected selected Figure 25-4. Switch from IMO to External Clock with the CPU Running with a CPU Clock Divider of One External Clock SYSCLK CPUCLK...
- Page 470 Digital Clocks 25.2 Register Definitions The following registers are associated with the Digital Clocks and are listed in address order. Each register description has an associated register table showing the bit structure for that register. For a complete table of digital clock registers, refer to the “Summary Table of the System Resource Registers”...
- Page 471 Digital Clocks 25.2.3 OSC_GO_EN Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,DDh SLPINT SYSCLKX2 SYSCLK CLK24M CLK32K RW : 00 OSC_GO_EN Oscillator Global Outputs Enable Register Bit 6: VC3. This bit enables the driving of the VC3 clock (OSC_GO_EN) is used to enable tri-state buffers that con- onto GOE[6].
- Page 472 Digital Clocks 25.2.4 OSC_CR4 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,DEh OSC_CR4 VC3 Input Select[1:0] RW : 00 The Oscillator Control Register 4 (OSC_CR4) selects the It is important to remember that even though the VC3 divider input clock to variable clock 3 (VC3).
- Page 473 Digital Clocks 25.2.5 OSC_CR3 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,DFh OSC_CR3 VC3 Divider[7:0] RW : 00 The Oscillator Control Register 3 (OSC_CR3) selects the The VC3 clock net can generate a system interrupt. After the divider value for variable clock 3 (VC3).
- Page 474 Digital Clocks 25.2.6 OSC_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,E0h OSC_CR0 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed[2:0] RW : 00 The Oscillator Control Register 0 (OSC_CR0) is used to the CPU speed circuit;...
- Page 475 Digital Clocks 25.2.7 OSC_CR1 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,E1h OSC_CR1 VC1 Divider[3:0] VC2 Divider[3:0] RW : 00 The Oscillator Control Register 1 (OSC_CR1) selects the Table 25-7.
- Page 476 Digital Clocks 25.2.8 OSC_CR2 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access SLP_EXTE SYSCLKX2 1,E2h OSC_CR2 PLLGAIN WDR32_SE EXTCLKEN RSVD RW : 00 The Oscillator Control Register 2 (OSC_CR2) is used to Bit 2: EXTCLKEN.
- Page 477 Digital Clocks CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
- Page 478 26. Multiply Accumulate (MAC) This chapter presents the Multiply Accumulate (MAC) and its associated registers. The MAC block is a fast 8-bit multiplier or a fast 8-bit multiplier with 32-bit accumulate. For a complete table of the MAC registers, refer to the “Summary Table of the ®...
- Page 479 Multiply Accumulate (MAC) 26.2 Application Description 26.2.2 Accumulation After Multiplication Accumulation of products is a feature that is implemented on 26.2.1 Multiplication with No top of simple multiplication. When using the MAC to accu- mulate the products of successive multiplications, two 8-bit Accumulation signed values are used for input.
- Page 480 Multiply Accumulate (MAC) 26.3.1 MULx_X Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,E8h MUL0_X Data[7:0] W : XX LEGEND X The value after power on reset is unknown. The Multiply Input X Register (MULx_X) is one of two multi- plier in the PSoC MAC.
- Page 481 Multiply Accumulate (MAC) 26.3.4 MULx_DL Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,EBh MUL0_DL Data[7:0] R : XX LEGEND X The value after power on reset is unknown. The Multiply Result Low Byte Register (MULx_DL) holds the MUL1_DL)) registers hold the least significant byte of the least significant byte of the 16-bit product.
- Page 482 Multiply Accumulate (MAC) 26.3.7 MACx_CL0/ACCx_DR3 Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access MAC0_CL0/ 0,EEh Data[7:0] RW : 00 ACC0_DR3 The Accumulator Data Register 3 (MACx_CL0/ACCx_DR3) all 32-bits of the accumulator are reset to zero. When this is an accumulator clear register and the fourth byte of the address is read, the accumulator's data register 3 is read.
- Page 483 Multiply Accumulate (MAC) CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
- Page 484 27. Decimator ® This chapter explains the PSoC Type 2 Decimator blocks, and their associated registers. The decimator blocks are a hard- ware assist for digital signal processing applications. The decimator may be used for delta-sigma analog to digital converters and incremental analog to digital converters.
- Page 485 Decimator Figure 27-2. Type 2 Decimator Custom Data Path TYPE 2 DECIMATOR ACCUMULATION DIFFERENTIATION 17-Bit Full 17-Bit Full 17-Bit Full ADDR ADDR ADDR DIFF DIFF REG 0 REG 1 8 DB (17 bit) (17 bit) 3x17 (17 bit) DIFF DCLK DCLK RESULT DCLK...
- Page 486 Decimator 27.1.1.1 Dedicated Data/Clock Input Selections for Single Decimator Row Each decimator accepts eight data input sources and eight clock input sources. Figure 27-4. Data/Clock Input Sources DATA_INx[2:0] DATA_INx[2:0] GOOEx ACE0_CMPO DATA_INx[2:0] ACCx_CMPO ACE1_CMPO DATA_INx[2:0] GOO[2x] ACE0_CMPO DATA_INx[2:0] ROW0LUTOx ACCx_CMPO ACE1_CMPO DATA_INx[2:0] DECDx...
- Page 487 Decimator The clocks are generated as shown in Figure 27-5. Note that there is an exception on clock generation: When ACCx_CMPO is the data input, the decimator's clocks are directly derived from the ACCx block; that is, the clock generator is bypassed. The final clocks are all zeros when the DECx_EN is zero, regardless of the clock source setting.
- Page 488 Decimator Table 27-5. Digital Block Output Selection D/ICLKS Selection D/ICLKS Selection D/ICLKS Selection D/ICLKS Selection 0000b DB02(FO2) 0100b DB00(FO0) 1000b DB22(FO10) 1100b DB20(FO8) 0001b DB12(FO6) 0101b DB10(FO4) 1001b DB32(FO14) 1101b DB30(FO12) 0010b DB01(FO1) 0110b DB03(FO3) 1010b DB21(FO9) 1110b DB23(FO11) 0011b DB11(FO5) 0111b DB13(FO7)
- Page 489 Decimator 27.2 Register Definitions The following registers are associated with the Decimator and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The bits that are grayed out in the tables are reserved bits and are not detailed in the register description that follows.
- Page 490 Decimator 27.2.3 DEC_CR0 Register Add. Name Cols. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,E6h DEC_CR0 4, 2 ACC_IGEN[3:0] ICLKS[0] ACE_IGEN[1:0] DCLKS0 RW : 00 The Decimator Control Register 0 (DEC_CR0) contains con- Bits 2 and 1: ACE_IGEN[1:0].
- Page 491 Decimator 27.2.5 DECx_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,91h DEC0_CR0 GOOO GOOE DATA_IN[2:0] RW : 00 1,95h DEC1_CR0 GOOO GOOE DATA_IN[2:0] RW : 00 1,99h DEC2_CR0 GOOO GOOE...
- Page 492 Decimator 27.2.7 DEC_CR4 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,96h DEC_CR4 DEC3_EN CLK_IN3[2:0] DEC2_EN CLK_IN2[2:0] RW : 00 The control bits in DEC_CR4 define the decimator clock Bit 3: DEC2_EN.
- Page 493 Decimator 27.2.9 DECx_CR Registers Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,D4h DEC0_CR Mode[1:0] Data Out Shift[1:0] Data Format Decimation Rate[2:0] RW : 00 1,D5h DEC1_CR Mode[1:0] Data Out Shift[1:0] Data Format Decimation Rate[2:0] RW : 00...
- Page 494 28. I This chapter explains the I C™ block and its associated registers. The I C communications block is a serial processor designed to implement a complete I C slave or master. For a complete table of the I C registers, refer to the “Summary Table ®...
- Page 495 Figure 28-1. Block Diagram with Two I C Blocks 28.1.2 Basic I C Data Transfer ® Figure 28-2 shows the basic form of data transfers on the PSoC I2C bus with a 7-bit address format. (For a more detailed description, see the NXP I C-bus™...
- Page 496 Figure 28-3. Slave Operation Master may transmit another byte or STOP. M8C writes M8C issues ACK/ (ACK) to An interrupt is generated NACK command Slave Transmitter/Reciever ACK = OK to I2C_SCR on byte complete. The with a write to the receive more register.
- Page 497 28.2.2 Master Operation To prepare for a Master mode transaction, the PSoC device Slave mode. The Start will be pending and eventually must determine if the bus is free. This is done by polling the occur at a later time when the bus becomes free. When BusBusy status.
- Page 498 28.3 Register Definitions The following registers are associated with I C and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.
- Page 499 28.3.2 I2Cx_CFG Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Enable Enable X,xxh I2Cx_CFG PSelect Bus Error IE Stop IE Clock Rate[1:0] RW : 00 Master Slave LEGEND Xx An “x”...
- Page 500 Bits 3 and 2: Clock Rate[1:0]. These bits offer a selection Figure 28-4 for a description of the interaction between the of three sampling and bit rates. All block clocking is based Master/Slave Enable bits. Block enable will be synchronized on the SYSCLK input, which is nominally 24 MHz (unless to the SYSCLK clock input (see “Timing Diagrams”...
- Page 501 28.3.3 I2Cx_SCR Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Stop Byte 0,xxh I2Cx_SCR Bus Error Lost Arb Address Transmit # : 00 Status Complete LEGEND # Access is bit specific. Refer to Table 28-5 for detailed bit descriptions.
- Page 502 Bit 6: Lost Arb. This bit is set when I C bus contention is will write a NAK indication to this register. No further inter- detected, during a Master mode transfer. Contention will rupts will occur, until the next address is received. If the occur when a master is writing a ‘1’...
- Page 503 firmware has set the Start or Restart bits in the the received ACK). In Receive mode, the bit is set after the I2C_MSCR register. eight bits of data are received. When this bit is set, an inter- rupt is generated at these data sampling points, which are Slave Transmitter: associated with the SCL input clock rising (see details in the ‘0’: ACK.
- Page 504 Bit 1: Restart Gen. This bit is only used at the end of a ister. The Address status is also set, indicating that master transfer (as noted in Other Cases 1 and 2 of the Start the block has been addressed as a slave. The firm- Gen bit).
- Page 505 28.4 PSoC Device Distinctions The CY8C28x03, CY8C28x23, CY8C28x43, and CY8C28x45 have two I C blocks. The rest of the CY8C28xxx devices have only one. 28.5 Timing Diagrams 28.5.1 Clock Generation Figure 28-5 illustrates the I C input clocking scheme. The SYSCLK pin is an input into a four-stage ripple divider that provides the baud rate selections.
- Page 506 28.5.2 Basic Input/Output Timing Figure 28-6 illustrates basic input output timing that is valid for both 16 times sampling and 32 times sampling. For 16 times sampling, N = 4; and for 32 times sampling, N = 12. N is derived from the half-bit rate sampling of eight and 16 clocks, respec- tively, minus the input latency of three (count of 4 and 12 correspond to 5 and 13 clocks).
- Page 507 Figure 28-9. Bus Error Interrupt Timing Misplaced Start CLOCK SDA_IN (Synchronized) START DETECT BUS ERROR and INTERRUPT Misplaced Stop CLOCK SDA_IN (Synchronized) STOP DETECT BUS ERROR and INTERRUPT 28.5.4 Master Start Timing When firmware writes the Start Gen command, hardware resynchronizes this bit to SYSCLK, to ensure a minimum of a full SYSCLK of setup time to the next clock edge.
- Page 508 Figure 28-11. Start Timing with a Pending Start CLOCK SDA_IN (Synchronized) STOP START STOP/START DETECT BUS BUSY SCL_OUT 8 Clocks 8 Clocks SDA_OUT OTHER MASTER SDA 7 Clocks / 4.7 s 6 Clocks / 4.0 s OTHER MASTER SCL Minimum Bus Free Minimum Start Hold Figure 28-12.
- Page 509 28.5.5 Master Restart Timing Figure 28-13 shows the Master Restart timing. After the ACK/NAK bit, the clock is held low for a half bit time (8/16 clocks cor- responding to the 16 or 32 times sampling rates), during which time the data is allowed to go high, then a valid start is gener- ated in the following 3 half bit times as shown.
- Page 510 28.5.7 Master/Slave Stall Timing When a Byte Complete interrupt occurs, the PSoC device firmware must respond with a write to the I2C_SCR register to con- tinue the transfer (or terminate the transfer). The interrupt occurs two clocks after the rising edge of SCL_IN (see “Status Tim- ing”...
- Page 511 28.5.9 Master Clock Synchronization Figure 28-17 shows the timing associated with Master Clock Synchronization. Clock synchronization is always operational, even if it is the only master on the bus. In which case, it is synchronizing to its own clock. In the wired AND bus, an SCL output of ‘0’...
- Page 512 29. Internal Voltage Reference This chapter discusses the Internal Voltage Reference and its associated register. The internal voltage reference provides an ® absolute value of 1.3 V to a variety of subsystems in the PSoC device. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page...
- Page 513 Internal Voltage Reference CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
- Page 514 30. System Resets ® This chapter discusses the System Resets and their associated registers. PSoC devices support several types of resets. The various resets are designed to provide error-free operation during power up for any voltage ramping profile, to allow for user-supplied external reset and to provide recovery from errant code operation.
- Page 515 System Resets 30.3 Register Definitions The following registers are associated with the PSoC System Resets and are listed in address order. Each register descrip- tion has an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.
- Page 516 System Resets 30.3.2 CPU_SCR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,FFh CPU_SCR0 GIES WDRS PORS Sleep STOP # : XX LEGEND Access is bit specific. Refer to register detail for additional information. XX The reset value is 10h after POR/XRES and 20h after a watchdog reset.
- Page 517 System Resets 30.4 Timing Diagrams 30.4.1 Power On Reset During XRES (XRES = 1), the IMO is powered off for low power during start-up. After XRES deasserts, the IMO is A Power on Reset (POR) is triggered whenever the supply started (see Figure 30-4).
- Page 518 System Resets Figure 30-4. Key Signals During POR and XRES POR (IPOR followed by PPOR): Reset while POR is high (IMO off), then 511(+) cycles (IMO on), and then the CPU reset is released. XRES is the same, with N=8. CLK32 IPOR PPOR...
- Page 519 System Resets 30.4.4 Reset Details Timing and functionality details are summarized in Table 30-1. Figure 30-4 shows some of the relevant signals for IPOR, PPOR, and XRES, while Figure 30-3 shows signaling for WDR and IRES. Table 30-1. Details of Functionality for Various Resets Item IPOR (Part of POR) PPOR (Part of POR)
- Page 520 31. Switch Mode Pump (SMP) This chapter explains the Switch Mode Pump (SMP) and its associated register. Using only a few external components, the SMP will pump a battery voltage up to a configurable stable operating voltage. Refer to the table titled “Availability of System ®...
- Page 521 PSoC Application Note 2097 on the web at http:// mines the ripple and hold time at the output voltage. A typi- www.cypress.com/psoc. cal capacitor value is 10 F. Inductor. The inductor value determines how much load Diode. Schottky diodes are recommended because they current can be supplied by the SMP.
- Page 522 Switch Mode Pump (SMP) 31.3 Register Definitions The following register is associated with the Switch Mode Pump (SMP). The register description below has an associated reg- ister table showing the bit structure of the register. The bit in the table that is grayed out is a reserved bit and is not detailed in the register description.
- Page 523 Switch Mode Pump (SMP) CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
- Page 524 32. POR and LVD This chapter briefly discusses the POR and LVD circuits and their associated registers. For a complete table of the POR and LVD registers, refer to the “Summary Table of the System Resource Registers” on page 462. For a quick reference of all ®...
- Page 525 POR and LVD The three valid settings for these bits are: ister are reset, forcing the CPU speed to 3 MHz or EXTCLK / 8. ■ 00b (2.9 V operation) ■ 01b (4.4 V operation) Bits 2 to 0: VM[2:0]. These bits set the Vdd level at which ■...
- Page 526 33. I/O Analog Multiplexer ® This chapter explains the chip-wide I/O Analog Multiplexer for the CY8C28xxx PSoC device and its associated registers. For a complete table of the I/O Analog Multiplexer registers, refer to the “Summary Table of the System Resource Registers” on page 462.
- Page 527 I/O Analog Multiplexer Figure 33-3. Dual Channel IDAC (IDAC0_D) (IDAC1_D) On/Off On/Off switch switch ICEN (IDAC_CR1) iunit iunit Left Right (AMuxBus0) (AMuxBus1) IDAC IDAC Left Right ioutL ioutR Therefore this IDAC block supports two different operation 33.3 Application Description modes, depending on ‘ICEN’ bit setting. The analog mux circuitry enables a variety of unique appli- Table 33-1.
- Page 528 I/O Analog Multiplexer gration capacitor. Although the CY8C28x43 devices have an measured in sequence, using the same integration capaci- analog mux bus, it does not have the IDACs or the pre- tor. charge switching circuitry. Therefore, these devices do not A pin used as the integration capacitor is not switched dur- support capacitive sensing applications.
- Page 529 I/O Analog Multiplexer 33.3.2 Chip-Wide Analog Input connects these pins together, with approximately 400 ohms of resistance between each pin and the analog mux bus. As The analog bus forms a multiplexer across many I/O pins. long as the clock choice in the AMUX_CFGx registers is set This allows any of these pins to be brought into the analog to the fixed '0' case, the switches will be static, controlled system for processing, as shown in...
- Page 530 I/O Analog Multiplexer 33.4.2 IDAC1_D Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,FCh IDAC1_D IDAC1[7:0] RW : 00 The Analog Mux right (AMuxBus1) DAC Data Register Bits 7 to 0: IDAC1[7:0]. The 8-bit value in this register sets (IDAC1_D) specifies the 8-bit multiplying factor that deter- the current driven onto the analog mux bus when the current mines the output DAC current.
- Page 531 I/O Analog Multiplexer 33.4.5 AMUX_CLK Register Address Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,AFh AMUX_CLK CLKTOR CLKTOL CLK1SYNC[1:0] CLK0SYNC[1:0] RW : 00 The Analog Mux Clock Register (AMUX_CLK) is used to rising edge.
- Page 532 I/O Analog Multiplexer 33.4.7 IDAC_MODE Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,E7h IDAC_MODE IDAC1_MD[3:0] IDAC0_MD[3:0] RW : 00 This register controls the selection of the IDAC ON/OFF 0100b to 0111b: DECD[0:3], 4 decimators' data inputs Control.
- Page 533 I/O Analog Multiplexer CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
- Page 534 34. Real Time Clock (RTC) This chapter covers the configuration and use of the real time clock (RTC) block and its associated registers. For a complete table of the related registers, refer to “Summary Table of the System Resource Registers” on page 462.
- Page 535 Real Time Clock (RTC) 34.1.4 General Timer period. When used as a general timer, the programmed time period can be from (65536*VC1) to (24*60*60)*(65536*VC1) As shown in Figure 34-1, there are two clock sources for by setting different start values of RTC_H, RTC_M, and counter65536.
- Page 536 Real Time Clock (RTC) 34.2.4 RTC_CR Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access SYNCRD_ 1,A7h RTC_CR INT_EN CLKSE INT_SEL[1:0] RT_EN RW : 00 Bit 5: INT_EN. RTC interrupt enable. Bit 1: SYNCRD_EN.
- Page 537 Real Time Clock (RTC) CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
- Page 538 35. 10-Bit SAR ADC Controller This chapter covers the configuration and use of the 10-bit SAR ADC controller and its associated registers. For a complete table of the 10-bit SAR ADC controller registers, refer to “Summary Table of the System Resource Registers” on page 462.
- Page 539 10-Bit SAR ADC Controller 35.1.2 Voltage Doubler Clock Generation 35.1.4 SAR Algorithm and Data Process There is a voltage doubler in the ADC comparator. Enable it In IDLE mode, the ADC data stays 0. It starts data conver- when chip power is less than 3 V. You can use SYSCLK sion from MSB to LSB in each ADC clock after the sample directly, or SYSCLK/4.
- Page 540 10-Bit SAR ADC Controller 35.1.5 A-D-C Operation Mode ADC comparator requires four A-D-C operation modes to achieve the best performance. Each mode has different control sig- nal timing, as listed in the following figures. Figure 35-4. A-D-C Operation Mode 0 (Default Mode) ADC_CLK SOLSB=1 WEAKREF=0...
- Page 541 10-Bit SAR ADC Controller 35.1.6 ‘Ready’ Bit, ‘Ongoing’ Bit and 35.2 Application Description Interrupt 35.2.1 ADC Sample Rate and Clock In SADC_CR0, two status bits are used to reflect ADC sta- Selection tus. The first is the ‘Ready’ bit, which is set when the ADC data register receives new data.
- Page 542 10-Bit SAR ADC Controller 35.3 Register Definitions 35.3.1 SADC_DH Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,6Ah SADC_DH Data High [7:0] R : 00 SADC_DH is the high byte of ADC data. 10-bit SAR ADC tified mode.
- Page 543 10-Bit SAR ADC Controller 35.3.4 SADC_TSCR1 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,72h SADC_TSCR1 TS_CMPH_SEL[2:0] TS_CMPL_SEL[2:0] RW : 00 This register is used to select the digital block for high chan- Bit 2 to 0: TS_CMPL_SEL[3:0].
- Page 544 10-Bit SAR ADC Controller 35.3.7 SADC_CR0 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access START/ 1,A8h SADC_CR0 ADC_CHS[3:0] READY ADC_EN RW : 00 ONGOING Bits 6 to 3: ADC_CHS[3:0]: ADC input channel selection. Bit 1: START/ONGOING.
- Page 545 10-Bit SAR ADC Controller 35.3.9 SADC_CR2 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access VDB_CLKS 1,AAh SADC_CR2 REFSEL BUFEN VDBEN FREERUN RW : 00 The 10-bit SAR ADC controller only exists in the Bit 5: VDBEN.
- Page 546 Section H: Glossary The Glossary section explains the terminology used in this technical reference manual. Glossary terms are characterized in bold, italic font throughout the text of this manual. accumulator In a CPU, a register in which intermediate results are stored. Without an accumulator, it is neces- sary to write the result of each calculation (addition, subtraction, shift, and so on.) to main mem- ory and read them back.
- Page 547 See Boolean Algebra . API (Application Pro- A series of software routines that comprise an interface between a computer application and gramming Interface) lower-level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. array An array, also known as a vector or list, is one of the simplest data structures in computer pro- gramming.
- Page 548 A single digit of a binary number. Therefore, a bit may only have a value of ‘0’ or ‘1’. A group of 8 ® bits is called a byte. Because the PSoC devices's M8C is an 8-bit microcontroller, the PSoC platform’s native data chunk size is a byte.
- Page 549 capture To extract information automatically through the use of software or hardware, as opposed to hand-entering of data into a computer file. chaining Connecting two or more 8-bit digital blocks to form 16-, 24-, and even 32-bit functions. Chaining allows certain signals such as Compare, Carry, Enable, Capture, and Gate to be produced from one block to another.
- Page 550 debugger A hardware and software system that allows the user to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band A period of time when neither of two or more signals are in their active state or in transition.
- Page 551 firmware The software that is embedded in a hardware device and executed by the CPU. The software may be executed by the end user, but it may not be modified. flag Any of various types of indicators used for identification of a condition or event (for example, a character that signals the termination of a transmission).
- Page 552 hexadecimal A base 16 numeral system (often abbreviated and called hex), usually written using the symbols 0-9 and A-F. It is a useful system in computers because there is an easy mapping from four bits to a single hex digit. Thus, one can represent every byte as two consecutive hexadecimal digits. Compare the binary, hex, and decimal representations: 0000b = 0001b =...
- Page 553 interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service rou- A block of code that normal code execution is diverted to when the M8C receives a hardware tine (ISR) interrupt.
- Page 554 An 8-bit Harvard Architecture microprocessor. The microprocessor coordinates all activity inside a PSoC device by interfacing to the Flash, SRAM, and register space. macro A programming language macro is an abstraction, whereby a certain textual pattern is replaced according to a defined set of rules. The interpreter or compiler automatically replaces the macro instance with the macro contents when an instance of the macro is encountered.
- Page 555 multiplexer (mux) 1. A logic function that uses a binary value, or address, to select between a number of inputs and conveys the data from the selected input to the output. 2. A technique which allows different input (or output) signals to use the same lines at different times, controlled by an external signal.
- Page 556 PSoC blocks See analog blocks and digital blocks . PSoC Designer™ The software for designing with Cypress’s Programmable System-on-Chip technology. pulse A rapid change in some characteristic of a signal (for example, phase or frequency), from a baseline value to a higher or lower value, followed by a rapid return to the baseline value.
- Page 557 revision ID A unique identifier of a PSoC device. ripple divider An asynchronous ripple counter constructed of flip-flops. The clock is fed to the first stage of the counter. An n-bit binary counter consisting of n flip-flops that can count in binary from 0 to 2 –...
- Page 558 skew The difference in arrival time of bits transmitted at the same time, in parallel transmission. slave device A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface.
- Page 559 The connection between two blocks of a device created by connecting several blocks/compo- nents in a series, such as a shift register or resistive voltage divider. terminal count The state at which a counter is counted down to zero. threshold The minimum value of a signal that can be detected by the system or sensor under consider- ation.
- Page 560 watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU will reset after a specified period of time. waveform The representation of a signal as a plot of amplitude versus time. See Boolean Algebra . CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No.
- Page 561 CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G...
- Page 562 Index Numerics ACK bit 195 ACMux bits 162 10-bit SAR ADC controller 537 AColxMux bits 80, 238, 255 ADC Clock Generation 537 acronyms 28 ADC FSM 538 ADC Clock Generation A-D-C Operation Mode 539 10-bit SAR ADC controller 537 ADC Sample Rate 540 architecture 537 ADC FSM Clock Selection 540...
- Page 563 AMUXCFG1 register 420, 529 architecture 421 in two column limited analog system 450 AMX_IN register 145, 250, 419 register definitions 422 for two column limited analog system 454 analog single slope ADC in two column limited Analog 0 bit analog system 442 in INT_CLR0 register 200 in INT_MSK0 register 208 analog synchronization interface 396...
- Page 564 bank 1 registers 218 rates for I2C 499 register mapping table 111, 113, 115, 117, 119, 121, ClockPhase bit in ASCxxCR0 register 161 basic paging in RAM paging 57 in ASDxxCR0 register 165 BCap bits 162, 166 clocks digital, See digital clocks BCD Code Counter CMOUT bit 156 real time clock 533...
- Page 565 register definitions 351 DEC_CR1 register 213, 267, 268, 270, 404, 453, timing 370 crosspoint switch in IO analog multiplexer 528 DEC_CR4 register 269 CT, See continuous time block decimator 483 architecture 483 CUR_PP register 60, 189 configurations 483 current page pointer in RAM paging 58 register definitions 488 type 2 block 483 decimator and incremental ADC interface 395...
- Page 566 internal main oscillator 465 external digital clock 467 register definitions 469 external reset 516 system clocking signals 465 digital IO, GPIO 73 digital system architecture 311 FCap bit characteristics 311 in ASCxxCR0 register 161 overview 22 in ASDxxCR0 register 165 register naming conventions 312 Flash register summary 312...
- Page 567 48-pin global interconnect 321 incremental ADC interface 395 56-pin global interconnect 322 index memory page pointer in RAM paging 59 architecture 317 input for digital blocks register definitions 322 clock resynchronization 336 global IO in GPIO 73 multiplexers 336 Global Select bits 129 INSAMP bit 156 GOExEN bit 186, 187 instruction amplifiers 427...
- Page 568 numeric naming conventions 27 KILL Interrupt Generation for digital blocks timing 365 KILL_INT bit 228, 232 On-Chip Debug (OCD) parts 34 KILL_INV bit 228 Ongoing bit KILL_MD bit 228 10-bit SAR ADC controller 540 OSC_CR0 register 90, 94, 102, 296, 473 OSC_CR1 register 297, 474 OSC_CR2 register 82, 91, 95, 103, 298, 475 look-up table (LUT) function 394, 442...
- Page 569 power consumption, system resets 518 architecture 533 BCD Code Counter 533 power on reset 516 General Timer 534 product upgrades 26 reading RTC data 533 ProtectBlock function in SROM 52 register definitions 534 PRTxDM0 register 77, 218 writing RTC data 533 PRTxDM1 register 77, 219 receiver for digital blocks PRTxDM2 register 77, 130...
- Page 570 Restart Gen bit 198 source instructions direct 44 RIx bits 179 immediate 43 RIxSYN bits 180 indexed 44 row digital interconnect 327 indirect post increment 47 architecture 327 SPI Complete bit 140, 141 register definitions 329 SPI for digital blocks timing diagram 334 master function 344 RTapMux bits 157...
- Page 571 SYNCEN bit 150 TX Complete bit 143 SYSCLKX2DIS bit 95, 298 TX Reg Empty bit 140–143 system resets 513 type 2 decimator block 483 architecture 513 functional details 518 power consumption 518 power on reset 516 UART function 335 register definitions 514 units of measure 27 timing diagrams 516 upgrades 26...
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