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Cypress WICED CYW43903 Manual

™ ieee 802.11 a/b/g/n soc with an embedded applications processor
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Summary of Contents for Cypress WICED CYW43903

  • Page 1 Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio.
  • Page 2 WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor The Cypress CYW43903 embedded wireless system-on-a-chip (SoC) is uniquely suited for Internet-of-Things applications. It sup- ports all rates specified in the IEEE 802.11 b/g/n specifications.The device includes an ARM Cortex-based applications processor, a single stream IEEE 802.11n MAC/baseband/radio, a power amplifier (PA), and a receive low-noise amplifier (LNA).
  • Page 3 RF Switch Controls 1 x 1, IEEE 802.11n PHY Always-On Domain 2.4 GHz Radio 37.4 MHz Crystal REG_ON AXI-to-AXI Bridge 2.4 GHz HIB_REG_ON_IN Switch PS RAM SR_Eng VBAT CSC = Cypress Serial Control. An I C‐compatible interface. WRF_PAOUT_2G WRF_RFIN_2G Document Number: 002-14826 Rev. *H Page 2 of 65...
  • Page 4 5. Applications Subsystem External Interfaces 17 13.3 Electrostatic Discharge Specifications ....41 5.1 GPIO ..............17 13.4 Recommended Operating Conditions and DC 5.2 Cypress Serial Control ........17 Characteristics ...........41 5.3 JTAG and ARM Serial Wire Debug ....17 13.5 Power Supply Segments ........43 5.4 PWM ..............
  • Page 5 PRELIMINARY CYW43903 19. Thermal Information ........61 15.5 BBPLL LDO ............53 19.1 Package Thermal Characteristics ......61 16. System Power Consumption ......54 19.2 Junction Temperature Estimation and PSI 16.1 WLAN Current Consumption ......54 Versus THETA 16.1.1 2.4 GHz Mode ........54 JC .............
  • Page 6 1. Overview 1.1 Introduction The Cypress CYW43903 is a single-chip device that provides the highest level of integration for an embedded system-on-a-chip with integrated IEEE 802.11 b/g/n MAC/baseband/radio and a separate ARM Cortex-R4 applications processor. It provides a small form- factor solution with minimal external components to drive down cost for mass volumes and allows for an embedded system with flexibility in size, form, and function.
  • Page 7 ■ Six dedicated PWM outputs. ■ 17 GPIOs. ■ IEEE 802.11 b/g/n 1×1 2.4 GHz radio. ■ Single- and dual-antenna support. ■ 1.Cypress Serial Control (CSC) is an I C-compatible interface. Document Number: 002-14826 Rev. *H Page 6 of 65...
  • Page 8 PRELIMINARY CYW43903 1.2 Standards Compliance The CYW43903 supports the following standards: IEEE 802.11n ■ IEEE 802.11b ■ IEEE 802.11g ■ IEEE 802.11d ■ IEEE 802.11h ■ IEEE 802.11i ■ Security: ■ ❐ WPA Personal ❐ WPA2 Personal ❐ ❐ WMM-PS (U-APSD) ❐...
  • Page 9 PRELIMINARY CYW43903 2. Power Supplies and Power Management 2.1 Power Supply Topology One core buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW43903. All regulators are programmable via the PMU. These blocks simplify power supply design for application and WLAN functions in embedded designs.
  • Page 10 PRELIMINARY CYW43903 Figure 3. Typical Power Topology (Page 1 of 2) WLRF TX Mixer and PA (not always) 1.2V CYW43903 1.2V Cap-less WLRF LOGEN LNLDO Cap-less 1.2V WLRF LNA LNLDO VBAT 1.2V Cap-less Operational: 2.3V to 4.8V WLRF AFE and TIA VCOLDO Performance: 3.0V to 4.8V 1.2V...
  • Page 11 PRELIMINARY CYW43903 Figure 4. Typical Power Topology (Page 2 of 2) CYW43903 2.5V and 3.3V 450 to 800 mA WLRF PA 3.3V VBAT LDO3P3 WLRF Pad VDDIO_RF WL OTP 3.3V 2.5V Cap-less WL RF RX, TX, NMOS, Mini-PMU LDOs LNLDO 2.5V Cap-less 2.5V WL RF VCO...
  • Page 12 PRELIMINARY CYW43903 2.3 Power Management The CYW43903 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages.
  • Page 13 PRELIMINARY CYW43903 During each clock cycle, the PMU sequencer performs the following actions: Computes the required resource set based on requests and the resource dependency table. ■ Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit of the resource ■...
  • Page 14 Table Note: Although the fractional-N synthesizer can support alternative reference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensive system testing. Contact Cypress for further details. Document Number: 002-14826 Rev. *H Page 13 of 65...
  • Page 15 PRELIMINARY CYW43903 3.2 External Frequency Reference As an alternative to a crystal, an external precision frequency reference can be used, provided that it meets the phase noise require- ments listed in Table If used, the external clock should be connected to the WRF_XTAL_XON pin through an external 1000 pF coupling capacitor, as shown Figure 6.
  • Page 16 PRELIMINARY CYW43903 3.3 External 32.768 kHz Low-Power Oscillator The CYW43903 uses a secondary low frequency clock for low-power-mode timing. Either the internal low-precision LPO or an external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process, voltage, and temperature, which is adequate for some applications.
  • Page 17 PRELIMINARY CYW43903 4. Applications Subsystem 4.1 Overview The Applications subsystem contains the general use CPU, memory, the standalone DMA core, the cryptography core, and the majority of the external interfaces. 4.2 Applications CPU and Memory Subsystem This subsystem has an integrated 32-bit ARM Cortex-R4 processor with an internal 32 KB D-cache and an internal 32 KB I-cache. The ARM Cortex-R4 is a low-power processor that features a low gate count, low interrupt latency, and low-cost debugging capabil- ities.
  • Page 18 The CYW43903 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB assembly testing during manufacturing. In addition, the JTAG interface allows Cypress to assist customers by using proprietary debug and character- ization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins by means of test points or a header on all PCB designs.
  • Page 19 PRELIMINARY CYW43903 5.4 PWM The CYW43903   provides up to six independent pulse width modulation (PWM) channels. The following features apply to the PWM channels: Each channel is a square wave generator with a programmable duty cycle. ■ Each channel generates its duty cycle by dividing down the input clock. ■...
  • Page 20 The SPI hardware block supports a hold time of 25ns and a maximum clock frequency of 40MHz. If a SPI slave does not support the above mode or requires a hold time greater than 25ns, a bit banging software SPI driver should be used. Cypress's WICED SDK provides and example of such a driver.
  • Page 21 The initial state of all bits in an unprogrammed OTP memory device is 0. After any bit is programmed to a 1, it cannot be reprogrammed to 0. The entire OTP memory array can be programmed in a single write-cycle using a utility provided with the Cypress WLAN manufacturing test tools.
  • Page 22 PRELIMINARY CYW43903 6.4 System Boot Sequence The following general sequence occurs after a CYW43903 is powered on: 1. Either REG_ON or HIB_REG_ON_IN is asserted. Note: For HIB_REG_ON_IN to function as intended, HIB_REG_ON_OUT must be connected to REG_ON. 2. The core LDO (CLDO) and LDO3P3 outputs stabilize. 3.
  • Page 23 PRELIMINARY CYW43903 7. Wireless LAN Subsystem 7.1 WLAN CPU and Memory Subsystem The CYW43903 WLAN section includes an integrated 32-bit ARM Cortex-R4 processor with internal RAM and ROM. The ARM Cortex- R4 is a low-power processor that features a low gate count, a small interrupt latency, and low-cost debug capabilities. It is intended for deeply embedded applications that require fast interrupt response features.
  • Page 24 PRELIMINARY CYW43903 Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges. ■ Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification. ■ Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon transmission time ■...
  • Page 25 PRELIMINARY CYW43903 7.2.4 RXE The receive engine (RXE) constitutes the receive data path of the MAC. It interfaces with the DMA engine to drain the received frames from the RXFIFO. It transfers bytes across the MAC-PHY interface and interfaces with the WEP module to decrypt frames. The decrypted data is stored in the RXFIFO.
  • Page 26 PRELIMINARY CYW43903 ™ 7.3 IEEE 802.11 b/g/n PHY The CYW43903 WLAN digital PHY complies with IEEE 802.11b/g/n single-stream specifications to provide wireless LAN connectivity supporting data rates from 1 Mbps to 72 Mbps for low-power, high-performance, handheld applications. The PHY has been designed to work in the presence of interference, radio nonlinearity, and various other impairments. It incorporates optimized implementations of filters, FFTs, and Viterbi-decoder algorithms.
  • Page 27 PRELIMINARY CYW43903 8. WLAN Radio Subsystem The CYW43903 includes an integrated WLAN RF transceiver that has been optimized for use in 2.4 GHz Wireless LAN systems. It has been designed to provide low-power, low-cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band.
  • Page 28 PRELIMINARY CYW43903 9. Pinout and Signal Descriptions 9.1 Ball Map Figure 11. 151-Ball WLBGA Map—Top View with Balls Facing Down RF_SW_ RF_SW_ LDO_ LDO_ VDDIO PWR_GND NC_J12 NC_H12 GPIO_3 GPIO_6 VOUT_3P3 SR_PVSS CTRL_8 CTRL_7 VDDBAT5V VDD1P5 VDDBAT5V RF_SW_ RF_SW_ VOUT_ SRSTN VSSC VSSC...
  • Page 29 PRELIMINARY CYW43903 9.2 Ball List Table 7 contains the 151-ball WLBGA net names. Table 7. WLBGA Net Names Ball Net Name Ball Net Name VSSC GPIO_15 GPIO_8 GPIO_14 VSSC SFL_IO0 VOUT_LNLDO SFL_CLK LDO_VDDBAT5V SFL_CS GPIO_0 UART0_CTS GPIO_9 VDDIO VSSC VDDC GPIO_7 REG_ON SPI0_CS...
  • Page 30 PRELIMINARY CYW43903 Ball Net Name Ball Net Name VSSC AVSS VDDC LPO_XTAL_IN NC_H12 RF_SW_CTRL_0 VDDC RF_SW_CTRL_5 HIB_XTALOUT VSSC HIB_LPO_SELMODE RF_SW_CTRL_8 VSSC WRF_AFE_GND VSSC WRF_AFE_GND VDDIO WRF_AFE_VDD1P35 VSSC WRF_SYNTH_VDD1P2 NC_J10 WRF_XTAL_VDD1P35 NC_J11 WRF_AFE_GND NC_J12 AVDD1P2 VSSC RF_SW_CTRL_3 VSSC NC_N10 HIB_REG_ON_IN RF_SW_CTRL_9 VSSC VDDIO VDDC...
  • Page 31 (I/O = bidirectional, I = input, and O = output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any. Table 8. Signal Descriptions Ball Number Signal Name Type Description Cypress Serial Control (CSC) Interfaces CSC master clock. C0_CLK CSC serial data C0_SDATA Clocks WRF_XTAL_XOP XTAL oscillator input.
  • Page 32 PRELIMINARY CYW43903 Table 8. Signal Descriptions (Cont.) Ball Number Signal Name Type Description Hibernation Block, Power-Down/Power-Up, and Reset REG_ON Used by PMU to power up or power down the internal CYW43903 regulators used by the WLAN and APP sections. Also, when deasserted, this pin holds the WLAN and APP sections in reset.
  • Page 33 PRELIMINARY CYW43903 Table 8. Signal Descriptions (Cont.) Ball Number Signal Name Type Description – PWM4 Pulse width modulation bit 4 – PWM5 Pulse width modulation bit 5 RF Signal Interface (WLAN) WRF_RFIN_2G 2.4 GHz WLAN receiver input RF_GND_P3 RF ground WRF_PAOUT_2G 2.4 GHz WLAN PA output RF_GND_P2...
  • Page 34 PRELIMINARY CYW43903 Table 8. Signal Descriptions (Cont.) Ball Number Signal Name Type Description LDO_VDD1P5 LNLDO input LDO_VDDBAT5V LDO VBAT WRF_XTAL_VDD1P35 XTAL LDO input (1.35V) WRF_XTAL_VDD1P2 XTAL LDO output (1.2V) VOUT_LNLDO Terminate with 2.2 μF capacitor to GND VOUT_CLDO Output of core LDO VOUT_3P3 LDO 3.3V output VOUT_CLDO_SENSE...
  • Page 35 PRELIMINARY CYW43903 10. GPIO Signals and Strapping Options 10.1 Overview This section describes GPIO signals and strapping options. The pins are sampled at power-on reset (POR) to determine various operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative function specified in Table 10.
  • Page 36 PRELIMINARY CYW43903 10.4 Alternate GPIO Signal Functions Table 10 provides the alternate signal functions of the GPIO signals. Table 10. Alternate GPIO Signal Functions HOLD/PDLOW/ GPIO Default JTAG_SEL Default Pull PDHIGH Strap Comments GPIO_0 – – No pull HOLD – 8 mA GPIO_1 –...
  • Page 37 PRELIMINARY CYW43903 11. Pin Multiplexing Table 11 shows the pin multiplexing functions. Table 11. Pin Multiplexing Function GPIO_0 GPIO_0 UART0_RXD PWM0 SPI1_MISO PWM2 GPIO_12 GPIO_8 – PWM4 – C1_SDATA GPIO_1 GPIO_1 UART0_TXD PWM1 SPI1_CLK PWM3 GPIO_13 GPIO_9 – PWM5 – C1_CLK GPIO_2 GPIO_2...
  • Page 38 PRELIMINARY CYW43903 Table 11. Pin Multiplexing Function RF_SW_ RF_SW_ UART_ – – – – – – – – SECI_IN CTRL_8 CTRL_8 DBG_RX RF_SW_ RF_SW_ UART_ – – – – – – – – SECI_OUT CTRL_9 CTRL_9 DBG_TX SPI0_MISO SPI0_MISO GPIO_17 GPIO_24 –...
  • Page 39 PRELIMINARY CYW43903 12. I/O States Table 12 provides I/O state information for the signals listed. The following notations are used in Table I: Input signal ■ O: Output signal ■ I/O: Input/Output signal ■ PU = Pulled up ■ PD = Pulled down ■...
  • Page 40 PRELIMINARY CYW43903 Table 12. I/O States Out-of-Reset; Before Low Power State/Sleep (All Power-down Software Download Ball Name Keeper Active Mode Power Present) (REG_ON Held Low) (REG_ON High) Power Rail GPIO_6 Input/Output; PU, PD, or Input/Output; PU, PD, or NoPull High-Z, NoPull Input;...
  • Page 41 PRELIMINARY CYW43903 13. Electrical Characteristics Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. 13.1 Absolute Maximum Ratings Caution! The absolute maximum ratings in Table 13 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration.
  • Page 42 PRELIMINARY CYW43903 13.2 Environmental Ratings The environmental ratings are shown in Table Table 14. Environmental Ratings Characteristic Value Units Conditions/Comments Ambient temperature (T –30 to +85 °C Functional operation Storage temperature –40 to +125 °C – Relative humidity Less than 60 Storage Less than 85 Operation...
  • Page 43 PRELIMINARY CYW43903 Table 16. Recommended Operating Conditions and DC Characteristics (Cont.) Value Parameter Symbol Minimum Typical Maximum Unit Other Digital I/O Pins For VDDIO = 1.8V: Input high voltage 0.65 × VDDIO – – Input low voltage – – 0.35 × VDDIO Output high voltage @ 2 mA VDDIO –...
  • Page 44 PRELIMINARY CYW43903 13.5 Power Supply Segments The digital I/O's are placed in physical segments. The supply voltage for each segment can be independently selected. Table 17 shows the power supply segments and the I/O pins associated with each segment. Table 17. Power Supply Segments Power Supply Segment Pins VDDIO...
  • Page 45 PRELIMINARY CYW43903 14. WLAN RF Specifications 14.1 Introduction The CYW43903 includes an integrated direct conversion radio that supports the 2.4 GHz band. This section describes the RF characteristics of the 2.4 GHz radio. Note: Values in this section of the data sheet are design goals and are subject to change based on device characterization results. Unless otherwise stated, limit values apply for the conditions specified in Table 14, “Environmental Ratings,”...
  • Page 46 PRELIMINARY CYW43903 14.3 WLAN 2.4 GHz Receiver Performance Specifications Note: The specification shown in Table 20 apply at the chip ports, unless otherwise defined. Table 20. WLAN 2.4 GHz Receiver Performance Specifications Parameter Condition/Notes Minimum Typical Maximum Unit Frequency range –...
  • Page 47 PRELIMINARY CYW43903 Table 20. WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit Adjacent channel rejection-DSSS Desired and interfering signal 30 MHz apart (Difference between interfering 1 Mbps DSSS –74 dBm – – and desired signal at 8% PER for 1024 octet PSDU with desired 2 Mbps DSSS –74 dBm...
  • Page 48 PRELIMINARY CYW43903 14.4 WLAN 2.4 GHz Transmitter Performance Specifications Note: Unless otherwise noted, the values shown in Table 21 apply at the chip ports. Table 21. WLAN 2.4 GHz Transmitter Performance Specifications Parameter Condition/Notes Minimum Typical Maximum Unit Frequency range –...
  • Page 49 PRELIMINARY CYW43903 14.5 General Spurious Emissions Specifications This section provides the TX and RX spurious emissions specifications for the WLAN 2.4 GHz band. The recommended spectrum analyzer settings for the spurious emissions specifications are provided in Table Table 22. Recommended Spectrum Analyzer Settings Parameter Setting Resolution bandwidth (RBW)
  • Page 50 PRELIMINARY CYW43903 15. Internal Regulator Electrical Specifications 15.1 Core Buck Switching Regulator Note: Values in this data sheet are design goals and are subject to change based on device characterization results. Note: Functional operation is not guaranteed outside of the specification limits provided in this section. Table 25.
  • Page 51 PRELIMINARY CYW43903 15.2 3.3V LDO (LDO3P3) Table 26. LDO3P3 Specifications Specification Notes Min. Typ. Max. Units Input supply voltage, V Min. = V + 0.2V = 3.5V dropout voltage requirement must be met under maximum load for performance specifications. Output current –...
  • Page 52 PRELIMINARY CYW43903 15.3 CLDO Table 27. CLDO Specifications Specification Notes Min. Typ. Max. Units Input supply voltage, V Min. = 1.2 + 0.15V = 1.35V dropout voltage requirement must be met 1.35 under maximum load. Output current – – Output voltage, V Programmable in 10 mV steps.
  • Page 53 PRELIMINARY CYW43903 15.4 LNLDO Table 28. LNLDO Specifications Specification Notes Min. Typ. Max. Units Input supply voltage, Vin Min. V + 0.15V = 1.35V (where V = 1.2V)dropout voltage 1.35 requirement must be met under maximum load. Output current – –...
  • Page 54 PRELIMINARY CYW43903 15.5 BBPLL LDO Table 29. BBPLL LDO Specifications Parameter Conditions and Comments Min. Typ. Max. Units Input supply voltage, V Min. V + 0.15V = 1.35V (for V = 1.2V). 1.35 The dropout voltage requirement must be met under maximum load.
  • Page 55 PRELIMINARY CYW43903 16. System Power Consumption Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Note: Unless otherwise stated, these values apply for the conditions specified in Table 16, “Recommended Operating Conditions and Characteristics,”.
  • Page 56 PRELIMINARY CYW43903 17. SPI Flash Characteristics 17.1 SPI Flash Timing 17.1.1 Read-Register Timing Figure 13 shows the SPI flash extended and quad read-register timing. Note: Regarding Figure 13: All Read Register commands except Read Lock Register are supported. A Read Nonvolatile Configuration Register operation will output data starting from the least significant byte.
  • Page 57 PRELIMINARY CYW43903 17.1.2 Write-Register Timing Figure 14 shows the SPI flash extended and quad write-register timing. Note: Regarding Figure 1. All write-register commands except Write Lock Register are supported. 2. The waveform must be extended for each protocol: to 23 for extended and five for quad. 3.
  • Page 58 PRELIMINARY CYW43903 17.1.3 Memory Fast-Read Timing Figure 15 shows the SPI flash extended and quad memory fast-read timing. Note: Regarding Figure 1. 24-bit addressing is used, so A[MAX] = A[23] and A[MIN] = A[0]. 2. For an extended SPI protocol, C = 7 + (A[MAX] + 1).
  • Page 59 PRELIMINARY CYW43903 17.1.4 Memory-Write Timing Figure 16 shows the SPI flash extended and quad memory-write (Page Program) timing. Note: Regarding Figure 1. For an extended SPI protocol, C = 7 + (A[MAX] + 1). 2. For a quad SPI protocol, C = 1 + (A[MAX] + 1)/4.
  • Page 60 PRELIMINARY CYW43903 17.1.5 SPI Flash Parameters The combination of Figure 17 Table 31 provide the SPI flash timing parameters. Figure 17. SPI Flash Timing Parameters Diagram T_DVCH Clock (C) T_CHDX Data in (D (DQ1 in Serial [Extended] mode) (DQ[3:0] in Quad mode) T_CLQX Data out (D (DQ0 in Serial [Extended] mode)
  • Page 61 PRELIMINARY CYW43903 18. Power-Up Sequence and Timing 18.1 Sequencing of Reset and Regulator Control Signals The CYW43903 has two signals that allow the host to control power consumption by enabling or disabling the internal regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the signals for various operational states (see Figure 18 Figure...
  • Page 62 PRELIMINARY CYW43903 19. Thermal Information 19.1 Package Thermal Characteristics Table 32. Package Thermal Characteristics Characteristic WLBGA  31.72 (°C/W) (value in still air)  3.95 (°C/W)  2.16 (°C/W)  (°C/W)  (°C/W) 9.28 Maximum Junction Temperature T (°C) 113.9 Maximum power dissipation (W) 1.38 1.
  • Page 63 PRELIMINARY CYW43903 20. Mechanical Information Figure 20. WLBGA Package Document Number: 002-14826 Rev. *H Page 62 of 65...
  • Page 64 (https://community.cypress.com/) 22.3 Errata 1. The RTC block has been deprecated from this datasheet in revision *A and later. This block is used by Cypress for internal testing/validation/verification and is not intended for customers to use. 2. The details of the SPI hardware blocks was not available in revision *E and 5.7 SPI...
  • Page 65 Figure 1 on page Figure 2 on page Features on page Applica- tions CPU and Memory Subsystem on page Updated “Broadcom Serial Control (BSC)” to “Cypress Serial Control (BSC)” throughout the 5986964 12/11/2017 document. Added VBAT in Figure 1 on page...
  • Page 66 “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device.

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