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Cypress enCoRe V CY7C643 Series Technical Reference Manual

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enCoRe™ V CY7C643xx,
enCoRe™ V LV CY7C604xx
Technical Reference Manual (TRM)
Document No. 001-32519 Rev *H
November 19, 2018
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
www.cypress.com

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  • Page 1 V CY7C643xx, enCoRe™ V LV CY7C604xx Technical Reference Manual (TRM) Document No. 001-32519 Rev *H November 19, 2018 Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 www.cypress.com...
  • Page 2 Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products.

  • Page 3: Table Of Contents

    Contents Section A: Overview Pin Information Pinouts............................15 1.1.1 CY7C60413 enCoRe V LV 16-Pin Part Pinout ............15 1.1.2 CY7C60445 enCoRe V LV 32-Pin Part Pinout16 1.1.3 CY7C64345, CY7C64343, enCoRe V 32-Pin Part Pinout ........17 1.1.4 CY8C20646A/AS/LCY8C20666A/AS/L CY7C64355, CY7C64356 enCoRe V 48-Pin Part Pinout18 1.1.5 CY7C60455, CY7C60456 enCoRe V LV 48-Pin Part Pinout.........19 1.1.6...
  • Page 4 Contents 4.1.6 Index Memory Page Pointer ..................40 Register Definitions.........................41 4.2.1 TMP_DRx Registers .....................41 4.2.2 CUR_PP Register ....................41 4.2.3 STK_PP Register ....................42 4.2.4 IDX_PP Register ....................42 4.2.5 MVR_PP Register ....................42 4.2.6 MVW_PP Register ....................43 4.2.7 Related Registers ....................43 Interrupt Controller Architectural Description......................44 5.1.1 Posted versus Pending Interrupts................45 Application Overview ......................45...
  • Page 5 Contents 7.4.4 Typical ADC Operation Procedure.................66 Internal Main Oscillator (IMO) Architectural Description......................67 Application Overview ......................67 8.2.1 Trimming the IMO ....................67 8.2.2 Engaging Slow IMO ....................67 Register Definitions.........................68 8.3.1 IMO_TR Register ....................68 8.3.2 IMO_TR1 Register ....................68 8.3.3 CPU_SCR1 Register .....................69 8.3.4 OSC_CR2 Register....................69 8.3.5 Related Registers ....................69...
  • Page 6 Contents 11.3.3 SLP_CFG2 Register .....................83 11.3.4 SLP_CFG3 Register .....................83 11.3.5 Related Registers ....................83 11.4 Timing Diagrams........................84 11.4.1 Sleep Sequence.....................84 11.4.2 Wakeup Sequence....................85 11.4.3 Bandgap Refresh ....................85 11.4.4 Watchdog Timer.....................86 11.5 ..............................86 12. Regulated I/O 12.1 Architectural Description......................87 12.1.1 Bias Generator.......................88 12.1.2 Charge Pump......................88 12.1.3...
  • Page 7 Contents 15.4.3 Status Timing .......................112 15.4.4 Slave Stall Timing....................113 16. System Resets 16.1 Architectural Description.......................114 16.2 Pin Behavior During Reset ....................114 16.2.1 GPIO Behavior on Power Up ................114 16.2.2 Powerup External Reset Behavior ...............115 16.2.3 GPIO Behavior on External Reset ...............115 16.3 Register Definitions.......................116 16.3.1 CPU_SCR1 Register ...................116...
  • Page 8 Contents 20.2 Application Description ......................141 20.2.1 USB SIE.......................141 20.2.2 USB SRAM ......................142 20.2.3 Oscillator Lock .....................144 20.2.4 Transceiver ......................144 20.2.5 USB Suspend ......................145 20.2.6 Regulator ......................145 20.3 Register Definitions.......................147 20.3.1 USB_SOF0 Register....................147 20.3.2 USB_CR0 Register ....................147 20.3.3 USBIO_CR0 Register ..................148 20.3.4 USBIO_CR1 Register ..................148 20.3.5...

  • Page 9: Section A: Overview

    For the most up-to-date ordering, pinout, packaging, or electrical specification information, refer to the enCoRe V device’s datasheet. For the most current technical reference manual information and newest product documentation, go to the Cypress web site at http://www.cypress.com >> Documentation.
  • Page 10 Top-Level Architecture enCoRe block diagram next page illustrates top-level architecture CY8C20X46A/46AS/96A/46L/96LCY7C643xx and CY7C604xx devices. Each major grouping in the diagram is covered in this manual in its own section: enCoRe V Core and System Resources. Banding these two main areas together is the communica- tion network of the system bus.
  • Page 11 enCoRe V Core Top-Level Block Diagram 1 .8 /2 .5 /3 V P W R S Y S P o r t 4 P o rt 3 P o r t 2 P o rt 1 P o r t 0 L D O (R e g u la to r) P S o C C O R E...
  • Page 12 Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for enCoRe V development. Go to the Cypress Online Store at http://www.cypress.com under Order >> USB Kits.
  • Page 13 Documentation Conventions Numeric Naming Hexadecimal numbers are represented with all letters in There are only four distinguishing font types used in this uppercase with an appended lowercase ‘h’ (for example, manual, besides those found in the headings. ‘14h’ or ‘3Ah’) and hexadecimal numbers may also be rep- The first is the use of italics when referencing a docu- ■...
  • Page 14 Acronyms Acronyms (continued) Acronym Description This table lists the acronyms that are used in this manual. PPOR precision power-on-reset pseudo random sequence Acronyms PSSDC power system sleep duty cycle Acronym Description random access memory ABUS analog output bus RETI return from interrupt alternating current relaxation oscillator analog-to-digital converter...

  • Page 15: Pin Information

    This chapter lists, describes, and illustrates all pins and pinout configurations for the CY8C20X46A/46AS/96A/46L/ 96LCY7C643xx and CY7C604xx enCoRe V devices. For up-to-date ordering, pinout, and packaging information, refer to the individual enCoRe V device’s datasheet or go to http://www.cypress.com. Pinouts TheCY8C20X46A/46AS/96A/46L/96LCY7C643xx and CY7C604xx enCoRe V devices are available in a variety of packages.

  • Page 16: Cy7C60445 Encore V Lv 32-Pin Part Pinout16

    Pin Information 1.1.2 CY7C60445 enCoRe V LV 32-Pin Part Pinout Table 1-2. 32-Pin QFN Part Pinout CY7C60445 enCoRe V LV Devices Name Description P0[1] Integrating input P2[7] P0[1] P0[0] P2[5] XTAL Out P2[7] P2[6] P2[3] XTAL In P2[5] P2[4] P2[1] P2[3] P2[2] P3[3]...

  • Page 17: Cy7C64345, Cy7C64343, Encore V 32-Pin Part Pinout

    Pin Information 1.1.3 CY7C64345, CY7C64343, enCoRe V 32-Pin Part Pinout Table 1-3. 32-Pin QFN Part Pinout CY7C64345, CY7C64343 enCoRe V Devices Name Description P0[1] P2[5] XTAL Out P2[3] XTAL In P2[1] P0[1] P0[0] IOHR P1[7] I2C SCL, SPI SS P2[5] P2[6] IOHR P1[5]...

  • Page 18: Cy8C20646A/As/Lcy8C20666A/As/L

    Pin Information 1.1.4 CY8C20646A/AS/LCY8C20666A/AS/L CY7C64355, CY7C64356 enCoRe V 48-Pin Part Pinout Table 1-4. 48-Pin Part Pinout CY7C64355, CY7C64356 enCoRe VDevices Name Description No connection P2[7] P2[6] P2[5] XTAL Out P2[7] P2[4] P2[3] XTAL In P2[5] P2[2] P2[1] P2[3] P2[0] P2[1] P4[2] P4[3] P4[3]...

  • Page 19: Cy7C60455, Cy7C60456 Encore V Lv 48-Pin Part Pinout

    Pin Information 1.1.5 CY7C60455, CY7C60456 enCoRe V LV 48-Pin Part Pinout Table 1-5. 48-Pin Part Pinout CY7C60455, CY7C60456 enCoRe V LV Devices Name Description No connection P2[7] P2[6] P2[5] XTAL Out P2[7] P2[4] P2[3] XTAL In P2[5] P2[1] P2[2] P4[3] P2[3] P2[0] P4[1]...
  • Page 20 Pin Information 1.1.6 CY8C20066A, CY8CTMG200-00LTXI, CY8CTMG200A-00LTXI PSoC, CY7C64300 enCoRe V and CY7C60400 enCoRe V LV OCD 48-Pin Part Pinout The 48-pin QFN part is for on-chip debugging (OCD). Note that this part is only used for in-circuit debugging. It is NOT avail- able for production.

  • Page 21: 32-Pin Qfn (With Usb)

    Pin Information 1.1.7 32-Pin QFN (with USB) Table 1-7. Pin Definitions – CY8C20496A/L PSoC Device CY8C20496A/L PSoC Device Type Digital Analog Name Description P0[1] Integrating Input P2[5] XTAL Out P2[3] XTAL In P0[1] P0[0] P2[5] P2[6] P2[1] P2[3] P2[4] IOHR P1[7] C SCL, SPI SS P2[1]...

  • Page 22: 48-Pin Ssop

    Pin Information 1.1.8 48-Pin SSOP Table 1-8. Pin Definitions – CY8C20536A, CY8C20546A, and CY8C20566A PSoC Device CY8C20536A, CY8C20546A, and CY8C20566A PSoC Device P0[7] P0[5] P0[7] P0[6] P0[3] P0[4] P0[5] 0[1] P0[2] P0[3] Integrating Input P2[7] P0[0] P0[1] Integrating Input P2[5] P2[6] P2[7] P2[3]...

  • Page 23: Section B: Encore V Core

    Section B: enCoRe V Core The enCoRe V Core section discusses the core components of an enCoRe V device with a base part number of CY7C643xx and CY7C604xx and the registers associated with those components. The core section covers the heart of the enCoRe V device, which includes the M8C microcontroller;...
  • Page 24 Core Register Summary This table lists all the enCoRe V registers for the CPU core in address order within their system resource configuration. The grayed out bits are reserved bits. If you write these bits, always write them with a value of ‘0’. For the core registers, the first ‘x’...
  • Page 25 Summary Table of the Core Registers (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access P1_LOW_ SPICLK_ON 1,DCh IO_CFG1 StrongP Range[1:0] REG_EN IOINT RW : 00 THRS _P10 INTERNAL MAIN OSCILLATOR (IMO) REGISTER (page 68) 1,E8h IMO_TR Trim[7:0]...

  • Page 26: Cpu Core (M8C)

    For additional information concerning the M8C instruction set, refer to the PSoC Designer Assembly Language User Guide available at http://www.cypress.com. For a quick reference of all enCoRe V regis- ters in address order, refer to the Register Reference chapter on page 163.

  • Page 27: Instruction Set Summary

    (in numeric and mnemonic order, respectively), and serves as a quick reference. If more information is needed, the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (visit http://www.cypress.com). Table 2-1. Instruction Set Summary Sorted Numerically by Opcode...
  • Page 28 CPU Core (M8C) Table 2-2. Instruction Set Summary Sorted Alphabetically by Mnemonic Instruction Format Flags Instruction Format Flags Instruction Format Flags ADC A, expr C, Z 76 7 INC [expr] C, Z POP X ADC A, [expr] C, Z INC [X+expr] C, Z POP A ADC A, [X+expr]...

  • Page 29: Instruction Formats

    CPU Core (M8C) Instruction Formats 2.5.2 Two-Byte Instructions The majority of M8C instructions are two bytes in length. The M8C has a total of seven instruction formats that use While these instructions are divided into categories identical instruction lengths of one, two, and three bytes. All instruc- to the one-byte instructions, this does not provide a useful tion bytes are taken from the program memory (flash), using distinction between the three two-byte instruction formats...

  • Page 30: Three-Byte Instructions

    CPU Core (M8C) 2.5.3 Three-Byte Instructions The second three-byte instruction format, shown in the sec- ond row of Table 2-5, is used by the following two address- The three-byte instruction formats are the second most ing modes: prevalent instruction formats. These instructions need three Destination Direct Source Immediate (ADD [7], 5) ■...

  • Page 31: Register Definitions

    CPU Core (M8C) Register Definitions The following register is associated with the CPU Core (M8C). The register description has an associated register table show- ing the bit structure. The bits that are grayed out in the table are reserved bits and are not detailed in the register description that follows.

  • Page 32: Supervisory Rom (Srom)

    3. Supervisory ROM (SROM) This chapter discusses the Supervisory ROM (SROM) functions. For a quick reference of all enCoRe V registers in address order, refer to the Register Reference chapter on page 163. Architectural Description The SROM holds code that boots a enCoRe V device, cali- Table 3-1.

  • Page 33: Additional Srom Feature

    Supervisory ROM (SROM) program to jump directly into the setup code and not acci- starts over. If this condition occurs, the internal reset status dentally run into it. bit (IRESS) is set in the CPU_SCR1 register. halt In devices with more than 256 bytes of SRAM, no SRAM is SSCOP: mov [KEY1], 3ah modified by the SWBootReset function in SRAM pages mov X, SP...
  • Page 34 Supervisory ROM (SROM) of flash and has two hundred fifty-six 128-byte blocks. Valid Table 3-5. SRAM Map Post SWBootReset (00h) block IDs are 00h to FFh. Table 3-6. Flash Memory Organization Address Number of 0x00 0x00 0x00 enCoRe V Amount of Amount of Number of 0x0_...
  • Page 35 Supervisory ROM (SROM) An MVI A, [expr] instruction is used to move data from In this table, note that all protection is removed by EraseAll. SRAM into flash. Therefore, use the MVI read pointer Table 3-10. Protect Block Modes (MVR_PP register) to specify which SRAM page from which data is pulled.
  • Page 36 Supervisory ROM (SROM) Table 3-14. Flash Tables with Assigned Values Table Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Silicon ID High Byte Expected Numbers = Table 0 Reserved # Bits Used to Encode = Max Values (including 0) = Bits Targeted = IMO 24 MHz...

  • Page 37: Register Definitions

    Supervisory ROM (SROM) spec). The function performs a three-step process. In the first step, 128 bytes of data are moved from SRAM to the flash. In the second step, flash is programmed with the data. In the final step, the flash data is compared against the input data values, thus verifying that the write was successful.

  • Page 38: Ram Paging

    4. RAM Paging This chapter explains the enCoRe V device’s use of RAM Paging and its associated registers. For a complete table of the RAM paging registers, refer to the Summary Table of the Core Registers on page 24. For a quick reference of all enCoRe V registers in address order, refer to the Register Reference chapter on page 163.

  • Page 39: Interrupts

    RAM Paging to the PSoC Designer Assembly Language User Guide for An MVI instruction performs three memory operations. Both more information on all M8C instructions. forms of the MVI instruction access an address in SRAM that holds the data pointer (a memory read 1st access), Stack memory accesses are a special case.

  • Page 40: Index Memory

    RAM Paging 4.1.6 Index Memory Page Pointer After reset, the PgMode bits are set to 00b. In this mode, index memory accesses are forced to SRAM Page 0, just as The Source Indexed and Destination Indexed addressing they are in a enCoRe V device with only 256 bytes of modes to SRAM are treated as a unique addressing mode SRAM.

  • Page 41: Register Definitions

    RAM Paging Register Definitions The following registers are associated with RAM Paging and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.

  • Page 42: Stk_Pp Register

    RAM Paging 4.2.3 STK_PP Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,D1h STK_PP Page Bits[2:0] RW : 0 The Stack Page Pointer Register (STK_PP) is used to set the STK_PP value after the stack grows, the program must the effective SRAM page for stack memory accesses in a ensure that the STK_PP value is restored when needed.

  • Page 43: Mvw_Pp Register

    RAM Paging 4.2.6 MVW_PP Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,D5h MVW_PP Page Bits[2:0] RW : 0 The MVI Write Page Pointer Register (MVW_PP) sets the address that is written by the instruction is determined by effective SRAM page for MVI write memory accesses in a the value of the least significant bits in this register.

  • Page 44: Interrupt Controller

    5. Interrupt Controller This chapter presents the Interrupt Controller and its associated registers. The interrupt controller provides a mechanism for a hardware resource in enCoRe V devices to change program execution to a new address without regard to the current task being performed by the code being executed.

  • Page 45: Posted Versus Pending Interrupts

    Interrupt Controller 7. Execution resumes at the next instruction, after the For example, if a block has a posted interrupt when it is instruction that occurred before the interrupt. However, if enabled and then disabled, the posted interrupt remains. there are more pending interrupts, the subsequent inter- Therefore, it is good practice to use the INT_CLR register to rupts are processed before the next normal program clear posted interrupts before enabling or re-enabling a...

  • Page 46: Register Definitions

    Interrupt Controller Register Definitions The following registers are associated with the Interrupt Controller and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.

  • Page 47: Int_Clr1 Register

    Interrupt Controller 5.3.2 INT_CLR1 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,DBh INT_CLR1 Endpoint3 Endpoint2 Endpoint1 Endpoint0 USB SOF USB Bus Rst Timer2 Timer1 RW : 00 This register enables the individual interrupt sources' ability Bit 4: Endpoint0.

  • Page 48: Int_Clr2 Register

    Interrupt Controller 5.3.3 INT_CLR2 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,DCh INT_CLR2 USB_WAKE Endpoint8 Endpoint7 Endpoint6 Endpoint5 Endpoint4 RW : 00 This register enables the individual interrupt sources' ability Write 1 AND ENSWINT = 1.

  • Page 49: Int_Msk0 Register

    Interrupt Controller 5.3.4 INT_MSK0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,E0h INT_MSK0 Sleep GPIO Timer0 Reserved Reserved V Monitor RW : 00 The Interrupt Mask Register (INT_MSK0) enables the indi- Bit 7: I2C.

  • Page 50: Int_Msk2 Register

    Interrupt Controller 5.3.6 INT_MSK2 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,DEh INT_MSK2 USB Wakeup Endpoint8 Endpoint7 Endpoint6 Endpoint5 Endpoint4 RW : 00 This register is used to enable the individual sources' ability Bit 2: Endpoint6.

  • Page 51: Int_Vc Register

    Interrupt Controller 5.3.8 INT_VC Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,E2h INT_VC Pending Interrupt[7:0] RC : 00 Legend Clearable register or bits. The Interrupt Vector Clear Register (INT_VC) returns the Reading the INT_VC register has limited usefulness.

  • Page 52: General-Purpose I/O (Gpio)

    6. General-Purpose I/O (GPIO) This chapter discusses the general-purpose I/O (GPIO) and its associated registers, which is the circuit responsible for inter- facing to the I/O pins of a enCoRe V device. The GPIO blocks provide the interface between the M8C core and the outside world.

  • Page 53: General Description

    General-Purpose I/O (GPIO) 6.1.1 General Description port, any bits that are currently driven low externally are read as a 0. These zeros are then written back to the port. The GPIO contains input buffers, output drivers, and config- When this happens, the pin goes into a strong 0 state; there- uration logic for connecting the enCoRe V device to the out- fore, if the external low drive condition ends in the system, side world.

  • Page 54: Gpio Block Interrupts

    General-Purpose I/O (GPIO) strong drive mode. Refer to the device datasheet for the dif- The Interrupt mode is changed so that the current pin ■ ferent current sourcing specifications of Port 0. state does not create an interrupt. After one of these conditions is met, the INTO releases. At 6.1.6 GPIO Block Interrupts this point, another GPIO pin (or this pin again) can assert its...

  • Page 55: Data Bypass

    General-Purpose I/O (GPIO) 6.1.7 Data Bypass Figure 6-3 assumes that the GIE is set, GPIO interrupt mask is set, and that the IOINT bit was set to high. The Change GPIO pins are configured to either output data through CPU Interrupt mode relies on the value of an internal read regis- writes to the PRTxDR registers or to bypass the port's data ter to determine if the pin state changed.

  • Page 56: Register Definitions

    General-Purpose I/O (GPIO) Register Definitions The following registers are associated with the general-purpose I/O (GPIO) and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.

  • Page 57: Prtxdmx Registers

    General-Purpose I/O (GPIO) 6.2.3 PRTxDMx Registers Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,xxh PRTxDM0 Drive Mode 0[7:0] RW : 00 1,xxh PRTxDM1 Drive Mode 1[7:0] RW : FF Legend xx An “x”...

  • Page 58: Io_Cfg1 Register

    General-Purpose I/O (GPIO) 6.2.4 IO_CFG1 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access P1_LOW_ SPICLK_ 1,DCh IO_CFG1 StrongP Range[1:0] REG_EN IOINT RW : 00 THRS ON_P10 The Input/Output Configuration Register 1 (IO_CFG1) con- Bit 3 P1_LOW_THRS.

  • Page 59: Analog-To-Digital Converter (Adc)

    7. Analog-to-Digital Converter (ADC) This chapter discusses the Analog-to-Digital Converter (ADC) and its associated registers. For a complete table of the ADC registers, refer to the Core Register Summary on page 24. For a quick reference of all enCoRe V registers in address order, refer to the Register Reference chapter on page 163.

  • Page 60: Brief Overview Of Adc Components And Registers

    Analog-to-Digital Converter (ADC) Brief Overview of ADC Components and Registers 7.2.2 This section provides an overview of the functions of the ADC block and the application interface. The ADC is a part of the temperature control block. 7.2.1 Interface Command/Status Block The ADC in enCoRe V can be connected to the Tempera- ture Sensor Core or the Analog Mux Bus as shown in The Interface command and status block provides the appli-...
  • Page 61 Analog-to-Digital Converter (ADC) Modulator Control Register 0 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access MOD_CR0 MOD_EN Reserved TIMER_EN RW : 00 This is the Control Register 0 for the modulator in the ADC Bits 6 to 1: MOD_CR0[6:1].
  • Page 62 Analog-to-Digital Converter (ADC) Temperature Sensor Control Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access TS_CR0 Reserved TS_EN RW : 00 This is the Control Register for the temperature sensor. Bit 0: Temperature Sensor Enable.
  • Page 63 Analog-to-Digital Converter (ADC) Comparator Control Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access CMP_CR0 Reserved Comparator Control bits RW : 00 This register controls the comparator and its inputs. Bits 7 to 4: CMP_CR0[7:4].

  • Page 64: Adc Register Definitions - Application Interface

    Analog-to-Digital Converter (ADC) ADC Register Definitions - Application Interface The following two registers are associated with the Analog to Digital Converter (ADC) interface and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.

  • Page 65: Application Overview

    Analog-to-Digital Converter (ADC) Application Overview As shown in Figure 7-3, the Temperature Sensor/ADC contains one read/write data port and one read only status port. Reads from the status port return terminal conditions. The application processor/controller presents the data port with a stream of bytes formatted to implement the desired commands.

  • Page 66: Typical Adc Operation Procedure

    Analog-to-Digital Converter (ADC) 7.4.4 Typical ADC Operation Procedure The ADC registers in the temperature sensor block are to be controlled using the command interface as per details pro- vided in Section 7.4. The following steps with the register values as shown in Table 7-2 configure the ADC for 12 MHz, 10-bit conversion.

  • Page 67: Internal Main Oscillator (Imo)

    8. Internal Main Oscillator (IMO) This chapter presents the Internal Main Oscillator (IMO) and its associated registers. The IMO produces clock signals of 6, 12, and 24 MHz. For a complete table of the IMO registers, refer to the Summary Table of the Core Registers on page 24.

  • Page 68: Register Definitions

    Internal Main Oscillator (IMO) Register Definitions The following registers are associated with the Internal Main Oscillator (IMO). The register descriptions have associated reg- ister tables showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.

  • Page 69: Cpu_Scr1 Register

    Internal Main Oscillator (IMO) 8.3.3 CPU_SCR1 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,FEh CPU_SCR1 IRESS SLIMO[1:0] IRAMDIS # : 0 Legend x An “x” before the comma in the address field indicates that this register can be read or written to no matter what bank is used. # Access is bit specific.

  • Page 70: Clocking Strategy

    Internal Main Oscillator (IMO) Clocking Strategy Block Pin List No clocks are needed for this block integration in the chip. Table 8-4. IMO Signals Name Type Direction Description Usage Guidelines General vpwr Supply Input Power Supply Oscillator clock frequency is adjusted to it operating fre- vgnd Supply Input...

  • Page 71: Operating Condition Requirements

    Internal Main Oscillator (IMO) 8.17 Operating Condition Requirements Table 8-5. IMO Operating Condition Requirements Specification Units Operating Description Condition 8.18 DC Specifications Table 8-6. DC IMO Specifications Block Specification Design Target Simulation Results BR4 Char Units DC Param. Description Corner, Actual Temp., Vdd 8.19...

  • Page 72: Internal Low-Speed Oscillator (Ilo)

    9. Internal Low-speed Oscillator (ILO) This chapter briefly explains the Internal Low-speed Oscillator (ILO) and its associated register. The Internal Low-speed Oscillator produces a 32-kHz or 1-kHz clock. For a quick reference of all enCoRe V registers in address order, refer to the Register Reference chapter on page 163.

  • Page 73: Register Definitions

    Internal Low-speed Oscillator (ILO) Register Definitions The following register is associated with the Internal Low-speed Oscillator (ILO). The register description has an associated register table showing the bit structure. The bits in the table that are grayed out are reserved bits and are not detailed in the register description that follows.

  • Page 74: External Crystal Oscillator (Eco)

    10. External Crystal Oscillator (ECO) This chapter briefly explains the External Crystal Oscillator (ECO) and its associated registers. The 32.768-kHz external crys- tal oscillator circuit allows the user to replace the internal low-speed oscillator with a more precise time source. For a quick reference of all enCoRe V registers in address order, refer to the Register Reference chapter on page 163.

  • Page 75: Application Overview

    External Crystal Oscillator (ECO) Figure 10-2. State Transition Between ECO and ILO This transition is allowed only if the write once "ECO Exists" register bit is set. Set OSC_CR0[7] to activate Default POR State the ECO, then on the next sleep interrupt, ECO becomes the 32.768 kHz source.

  • Page 76: Register Definitions

    External Crystal Oscillator (ECO) 10.3 Register Definitions These registers are associated with the external crystal oscillator. 10.3.1 ECO_ENBUS Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,D2h ECO_ENBUS ECO_ENBUS[2:0] RW : 07 The ECO_ENBUS register is used to disable and enable the...

  • Page 77: Related Registers

    External Crystal Oscillator (ECO) freely switch between the ECO and ILO. It should be written For additional information, refer to the ECO_CFG register as early as possible after a POR or XRES event. on page 229 10.3.4 Related Registers OSC_CR0 Register, on page 101.

  • Page 78: 11. Sleep And Watchdog

    11. Sleep and Watchdog This chapter discusses the Sleep and Watchdog operations and their associated registers. For a complete table of the Sleep and Watchdog registers, refer to the Summary Table of the Core Registers on page 24. For a quick reference of all enCoRe V registers in address order, refer to the Register Reference chapter on page 163.

  • Page 79: Sleep Control Implementation Logic

    Sleep and Watchdog 11.1.1 Sleep Control Implementation Logic This section details the sleep mode logic implementation. Conditions for entering the sleep modes: Standby Mode: Set the SLEEP bit in the CPU_SCR0 register. This asserts the “sleep” signal for the sleep controller. ■...
  • Page 80 Sleep and Watchdog 1, 2, 3 Figure 11-2. Wakeup Sequence for the Device Interrupt ½ CPU clock 10 – 60 µs 3 – 20 µs 1 – 20 µs cycle Power good Regulator Enable Power switches Enable Bandgap Enable POR Enable IMO Enable SLEEP Sample Bandgap...

  • Page 81: Sleep Timer

    Sleep and Watchdog Note The T0, T1, and T2 mentioned in the SLP_CFG3 reg- Note 2 There is no need to enable the Global Interrupt ister with respect to Figure 11-2 on page 80 are defined as Enable (CPU_F register) to wake the system out of sleep follows: state.

  • Page 82: Register Definitions

    Sleep and Watchdog 11.3 Register Definitions The following registers are associated with Sleep and Watchdog operations and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The bits that are grayed out in the the following tables are reserved bits and are not detailed in the register descriptions.

  • Page 83: Slp_Cfg2 Register

    Sleep and Watchdog 11.3.3 SLP_CFG2 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,ECh SLP_CFG2 ALT_Buzz [1:0] I2C_ON LSO_OFF RW : 00 The Sleep Configuration Register (SLP_CFG2) holds the To ensure data retention in the 32-byte I2C buffer during configuration for I2C sleep, deep sleep, and buzz.

  • Page 84: Timing Diagrams

    Sleep and Watchdog 11.4 Timing Diagrams 11.4.1 Sleep Sequence The SLEEP bit in the CPU_SCR0 register, is an input into VDD brown out condition, the configurable buzz rate must the sleep logic circuit. This circuit is designed to sequence be frequent enough to capture the falling edge of VDD. If the the device into and out of the hardware sleep state.

  • Page 85: Wakeup Sequence

    Sleep and Watchdog 11.4.2 Wakeup Sequence 11.4.3 Bandgap Refresh When asleep, the only event that wakes the system is an During normal operation the bandgap circuit provides a volt- interrupt. The Global Interrupt Enable of the CPU Flag regis- age reference (VRef) to the system for use in the analog ter does not need to be set.

  • Page 86: Watchdog Timer

    Sleep and Watchdog 11.4.4 Watchdog Timer Figure 11-5. Watchdog Reset On device boot up, the Watchdog Timer (WDT) is initially CLK32K disabled. The PORS bit in the System Control register con- SLEEP INT trols the enabling of the WDT. Upon boot, the PORS bit is initially set to '1', indicating that either a POR or XRES event WD COUNT occurred.

  • Page 87: Regulated I/O

    Regulated I/O This chapter presents the architecture of the Regulated I/O and its functionality, along with voltage regulator information. There are no registers associated with the regulated I/O. For a quick reference of all enCoRe V registers in address order, refer to the Register Reference chapter on page 163.

  • Page 88: Bias Generator

    Regulated I/O 12.1.1 Bias Generator The bias generator generates gate bias to all pass transis- tors. This block mainly contains a charge pump an opamp along with a NMOS diode in a forward biased condition. 12.1.2 Charge Pump The Charge Pump gets clock information from the internal main oscillator and pumps the charge to forward bias the NMOS diode.

  • Page 89: Register Definitions

    Regulated I/O 12.3 Register Definitions The following registers are associated with the Regulated I/O and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.

  • Page 90: 13. I/O Analog Multiplexer

    13. I/O Analog Multiplexer This chapter explains the device-wide I/O Analog Multiplexer for the CY7C643xx and CY7C604xx enCoRe V devices and their associated registers. For a quick reference of all enCoRe V registers in address order, refer to the Register Reference chapter on page 163.

  • Page 91: Register Definitions

    I/O Analog Multiplexer 13.2 Register Definitions The following registers are only associated with the Analog Bus Mux in the CY7C643xx and CY7C604xx enCoRe V devices and are listed in address order. Each register description has an associated register table showing the bit structure for that register.

  • Page 92: Section C: System Resources

    Section C: System Resources This section discusses the system resources that are available for the enCoRe V devices and the registers associated with those resources. This section includes the following chapters: Digital Clocks on page POR and LVD on page 121.
  • Page 93 System Resources Register Summary The following table lists all the enCoRe V registers for the system resources, in address order, within their system resource configuration. The bits that are grayed out are reserved bits. If you write these bits, always write them with a value of ‘0’. Summary Table of the System Resource Registers Address Name...
  • Page 94 Summary Table of the System Resource Registers (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,64h PMAx_DR Data Byte[7:0] RW : 00 0,65h PMAx_DR Data Byte[7:0] RW : 00 0,66h PMAx_DR Data Byte[7:0]...
  • Page 95 Summary Table of the System Resource Registers (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Data Count 0,4Eh EPx_CNT0 Data Valid # : 0 Toggle BusActiv- Ena- 1,30h USB_CR1 RegEnable RW : 0...

  • Page 96: 14. Digital Clocks

    14. Digital Clocks This chapter discusses the Digital Clocks and their associated registers. It serves as an overview of the clocking options available in the enCoRe V devices. For detailed information on specific oscillators, see the individual oscillator chapters in the section called enCoRe V Core on page 23.

  • Page 97: External Clock

    Digital Clocks Figure 14-1. Overview of enCoRe V Clock Sources User should ensure that the external clock is glitch free. See device datasheet for the clock specifications. P1[4] IMO Trim Register In applications where XRES is used when in external clock (EXTCLK Input) IMO_TR[7:0] mode, care must be taken to switch the clock source to IMO...
  • Page 98 Digital Clocks Figure 14-2. Switch from IMO to the External Clock with a CPU Clock Divider of Two or Greater Extenal Clock SYSCLK CPUCLK IOW_ EXTCLK bit IMO is External clock is deselected. selected. Figure 14-3. Switch from IMO to External Clock with the CPU Running with a CPU Clock Divider of One External Clock SYSCLK CPUCLK...

  • Page 99: Register Definitions

    Digital Clocks 14.2 Register Definitions The following registers are associated with the Digital Clocks and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The bits in the tables that are grayed out throughout this manual are reserved bits and are not detailed in the register descriptions that follow.
  • Page 100 Digital Clocks Bit 0: P10EN Bit enables pin P1[0] to output the sleep inter- 1 - Output SLPINT to P1[0] rupt (SLPINT). For additional information, refer to the OUT_P1 on page 0 - No internal signal output to P1[0] 225. enCoRe™...

  • Page 101: Osc_Cr0 Register

    Digital Clocks 14.2.3 OSC_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,E0h OSC_CR0 X32ON Disable Buzz No Buzz Sleep[1:0] CPU Speed[2:0] RW : 01 The Oscillator Control Register 0 (OSC_CR0) configures The CPU frequency is changed with a write to the various features of internal clock sources and clock nets.

  • Page 102: Osc_Cr2 Register

    Digital Clocks 14.2.4 OSC_CR2 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,E2h OSC_CR2 CLK48MEN EXTCLKEN RSVD RW : 00 The Oscillator Control Register 2 (OSC_CR2) configures most device clocking functions. All external and internal sig- various features of internal clock sources and clock nets.

  • Page 103: I 2 C Slave

    15. I C Slave This chapter explains the I C Slave block and its associated registers. The I C communications block is a serial processor designed to implement a complete I C slave. For a complete table of the I C registers, refer to the Summary Table of the Sys- tem Resource Registers on page...

  • Page 104: Basic I 2 C Data Transfer

    C Slave Flexible data buffering schemes ■ Enhanced features of the I C Slave Enhanced module include: A “no bus stalling” operating mode Support for 7-bit hardware address compare ■ This block has a low-power bus monitoring mode. Figure 15-2. I C Slave Block Diagram I2C Core SDA_IN...

  • Page 105: Application Overview

    C Slave 15.2 Application Overview 15.2.1 Slave Operation address. It Issues an ACK or NACK command based upon that comparison. When Slave mode is enabled, it is continually listening on If there is an address match, the RW bit determines how the the bus for a Start condition.

  • Page 106: Register Definitions

    C Slave 15.3 Register Definitions The registers shown here are associated with I C slave and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The grayed out bits in the tables are reserved bits and are not detailed in the register descriptions that follow.

  • Page 107: I2C_Cfg Register

    C Slave 15.3.3 I2C_CFG Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,D6h I2C_CFG PSelect Stop IE Clock Rate[1:0] Enable RW : 00 Bit 4: Stop IE. Stop Interrupt Enable. When this bit is set, a The I C Configuration Register (I2C_CFG) is used to set the slave can interrupt upon Stop detection.
  • Page 108 C Slave The other option is to change the drive modes of the I pins to be other than open drain mode and then enable the C block. After enabling the I C block, wait for three I sample clocks, then configure the drive modes of the I pins to be in open drain mode.

  • Page 109: I2C_Scr Register

    C Slave 15.3.4 I2C_SCR Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Stop Byte 0,D7h I2C_SCR Bus Error Address Transmit # : 00 Status Complete Legend # Access is bit specific. The selections are shown in the following table: The I C Status and Control Register (I2C_SCR) is used by...

  • Page 110: I2C_Dr Register

    C Slave Bit 3: Address. clock in an acknowledge bit from the receiver. Upon the sub- sequent byte complete interrupt, firmware checks the value This bit is set when an address is received. This consists of of this bit. A ‘0’ is the ACK value and a ‘1’ is a NACK value. a Start or Restart, and an address byte.

  • Page 111: Timing Diagrams

    C Slave 15.4 Timing Diagrams 15.4.1 Clock Generation Figure 15-5 illustrates the I C input clocking scheme. The SYSCLK pin is an input into a three-stage ripple divider that pro- vides the baud rate selections. When the block is disabled, all internal state is held in a reset state. When the Enable bit in the I2C_CFG Register is set, the reset is synchronously released and the clock generation is enabled.

  • Page 112: Status Timing

    C Slave 15.4.3 Status Timing Figure 15-7 illustrates the interrupt timing for byte complete, Figure 15-8 shows the timing for Stop status. This bit is set which occurs on the positive edge of the ninth clock (byte + (and the interrupt occurs) two clocks after the synchronized ACK/NACK) in transmit mode and on the positive edge of and filtered SDA line transitions to a ‘1’, when the SCL line is the eighth clock in receive mode.

  • Page 113: Slave Stall Timing

    C Slave 15.4.4 Slave Stall Timing When a byte complete interrupt occurs, the enCoRe V device firmware must respond with a write to the I2C_SCR Register continue the transfer (or terminate the transfer). The interrupt occurs two clocks after the rising edge of SCL_IN (see Status Timing on page 112).

  • Page 114: 16. System Resets

    16. System Resets This chapter discusses the System Resets and their associated registers. enCoRe V devices support several types of resets. The various resets are designed to provide error-free operation during power up for any voltage ramping profile, to allow user- supplied external reset, and to provide recovery from errant code operation.

  • Page 115: Powerup External Reset Behavior

    System Resets 16.2.2 Powerup External Reset Behavior 16.2.3 GPIO Behavior on External Reset The device’s core runs on chip regulated supply, so there is During external reset (XRES=1), both P1[0] and P1[1] drive a time delay in powering up the core. A short XRES pulse at resistive low (0).

  • Page 116: Register Definitions

    System Resets 16.3 Register Definitions The following registers are associated with the enCoRe V System Resets and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.

  • Page 117: Cpu_Scr0 Register

    System Resets 16.3.2 CPU_SCR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,FFh CPU_SCR0 GIES WDRS PORS Sleep STOP # : XX Legend Access is bit specific. Refer to register detail for additional information. XX The reset value is 10h after POR/XRES and 20h after a watchdog reset.

  • Page 118: Timing Diagrams

    System Resets 16.4 Timing Diagrams 16.4.1 Power-On-Reset higher voltage than specified. For this reason, avoid shifting key AC52h while in reset. A power-on-reset (POR) is triggered whenever the supply During XRES (XRES=1), the IMO is powered off for low voltage is below the POR trip point. POR ends when the power during startup.
  • Page 119 System Resets Figure 16-4. Key Signals During POR and XRES POR (IPOR followed by PPOR): Reset while POR is high (IMO off), then 511(+) cycles (IMO on), and then the CPU reset is released. XRES is the same, with N=8. CLK32 IPOR PPOR...

  • Page 120: Reset Details

    System Resets 16.4.4 Reset Details Timing and functionality details are summarized in Table 16-1. Figure 16-4 on page 119 shows some of the relevant signals for IPOR, PPOR, XRES, and WDR. Table 16-1. Reset Functionality Item IPOR (Part of POR) PPOR (Part of POR) XRES While PPOR=1, plus...

  • Page 121: 17. Por And Lvd

    17. POR and LVD This chapter briefly discusses the power-on-reset (POR) and low-voltage detect (LVD) circuits and their associated registers. For a complete table of the POR registers, refer to the Summary Table of the System Resource Registers on page 93.

  • Page 122: Register Definitions

    POR and LVD 17.2 Register Definitions The following registers are associated with the POR and LVD, and are listed in address order. The following register descrip- tions have an associated register table showing the bit structure. The bits that are grayed out in the register tables are reserved bits and are not detailed in the register descriptions that follow.

  • Page 123: 18. Spi

    18. SPI This chapter presents the Serial Peripheral Interconnect (SPI) and its associated registers. For a complete table of the SPI registers, see the Summary Table of the System Resource Registers on page 93. For a quick reference of all enCoRe V reg- isters in address order, refer to the Register Reference chapter on page 163.

  • Page 124: Spi Master Function

    18.1.1.1 SPI Protocol Signal Definitions 18.1.2.2 Block Interrupt The SPI protocol signal definitions are located in Table 18-1. The SPIM block has a selection of two interrupt sources: The use of the SS_ signal varies according to the capability interrupt on TX Reg Empty (default) or interrupt on SPI of the slave device.

  • Page 125: Input Synchronization

    18.1.4 Input Synchronization 18.1.3.2 Block Interrupt The SPIS block has a selection of two interrupt sources: All pin inputs are double synchronized to SYSCLK by Interrupt on TX Reg Empty (default) or interrupt on SPI default. Synchronization can be bypassed by setting the Complete (same selection as the SPIM).

  • Page 126: Spi_Rxr Register

    18.2.2 SPI_RXR Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,2Ah SPI_RXR Data[7:0] R : 00 The SPI Receive Data Register (SPI_RXR) is the SPI’s Bits 7 to 0: Data[7:0]. These bits encompass the SPI receive data register.

  • Page 127: Spi_Cr Register

    Control Register 18.2.3 SPI_CR Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access TX Reg Clock Clock 0,2Bh SPI_CR LSb First Overrun RX Reg Full Enable # : 00 Complete Empty Phase...

  • Page 128: Spi_Cfg Register

    Configuration Register The configuration block contains 1 register. This register must not be changed while the block is enabled. Note that the SPI Configuration register is located in bank 1 of the enCoRe V device’s memory map. 18.2.4 SPI_CFG Register Address Name Bit 7...

  • Page 129: Timing Diagrams

    18.3 Timing Diagrams 18.3.1 SPI Mode Timing Figure 18-3 shows the SPI modes that are typically defined as 0, 1, 2, or 3. These mode numbers are an encoding of two con- trol bits: Clock Phase and Clock Polarity. Clock Phase indicates the relationship of the clock to the data. When the clock phase is '0', it means that the data is registered as an input on the leading edge of the clock and the next data is output on the trailing edge of the clock.

  • Page 130: Spim Timing

    18.3.2 SPIM Timing Enable/Disable Operation. As soon as the block is config- When the Enable bit in the SPI_CR register is set, the reset ured for SPIM, the primary output is the MSb or LSb of the is synchronously released and the clock generation is Shift register, depending on the LSb First configuration in bit enabled.
  • Page 131 Normal Operation. Typical timing for an SPIM transfer is After the last bit is output, if TX Buffer data is available with shown in Figure 18-5 Figure 18-6. The user initially one-half clock setup time to the next clock, a new byte trans- writes a byte to transmit when TX Reg Empty status is true.
  • Page 132 Figure 18-6. Typical SPIM Timing in Mode 2 and 3 Last bit of received Shifter is loaded data is valid on this with the next Shifter is loaded Setup time Free running, edge and is latched byte. with the first byte. for the TX internal bit rate into RX Buffer.
  • Page 133 Figure 18-7. SPI Status Timing for Modes 0 and 1 SS Forced Low Transfer in Progress SCLK (Mode 0) SCLK (Mode 1) SS Toggled on a Message Basis Transfer in Progress Transfer in Progress SCLK (Mode 0) SCLK (Mode 1) SS Toggled on Each Byte Transfer in Progress Transfer in Progress...

  • Page 134: Spis Timing

    18.3.3 SPIS Timing Enable/Disable Operation. As soon as the block is config- When the block is disabled, the MISO output reverts to its ured for SPI Slave and before enabling, the MISO output is idle 1 state. All internal state is reset (including CR0 status) set to idle at logic 1.
  • Page 135 Figure 18-10. Typical SPIS Timing in Modes 2 and 3 Shifter is loaded with Last bit of received data is valid Shifter is first byte (by leading on this edge and is latched into loaded with First edge of the SCLK ). the RX Buffer register.
  • Page 136 Figure 18-11 illustrates TX data loading in modes 0 and 1. A transfer in progress is defined to be from the falling edge of SS_ to the point at which the RX Buffer register is loaded with the received byte. This means that to send a byte in the next trans- fer, it must be loaded into the TX Buffer register before the falling edge of SS_.

  • Page 137: 19. Programmable Timer

    19. Programmable Timer This chapter presents the Programmable Timer and its associated registers. For a complete table of the programmable timer registers, refer to the Summary Table of the System Resource Registers on page 93. For a quick reference of all enCoRe V registers in address order, refer to the Register Reference chapter on page 163.
  • Page 138 Programmable Timer Figure 19-2. Continuous Operation Example PTDATA1 0003h PTDATA0 Clock Start One Shot Count TC Period TC Period Figure 19-3. One-Shot Operation Example PTDATA1 0003h PTDATA0 Clock Start One Shot Count TC Period enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H...

  • Page 139: Register Definitions

    Programmable Timer 19.2 Register Definitions The following registers are associated with the Programmable Timer and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.

  • Page 140: Pt2_Cfg Register

    Programmable Timer 19.2.3 PT2_CFG Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,B6h PT2_CFG CLKSEL One Shot START RW : 0 Programmable Timer Configuration Register tinuous mode, the timer reloads the count value each time (PT2_CFG) configures the enCoRe V’s programmable upon completion of its count cycle and repeats.

  • Page 141: 20. Full-Speed Usb

    20. Full-Speed USB This chapter explains the Full-Speed USB (Universal Serial Bus) resource and its associated registers. For a quick reference of all enCoRe V registers in address order, refer to the Register Reference chapter on page 163. USB is only available on cer- tain devices.

  • Page 142: Usb Sram

    Full-Speed USB Table 20-1. Mode Encoding for Control and Non-Control Endpoints Mode Encoding SETUP Comments Disable 0000 Ignore Ignore Ignore Ignore all USB traffic to this endpoint. NAK IN/OUT 0001 Accept NAK IN and OUT token. Status OUT Only 0010 Accept STALL Check...
  • Page 143 Full-Speed USB The PMA's purpose is to manage the potentially conflicting The M8C may also service another channel and come back SRAM access requests from the M8C and the USB SIE. to the channel being serviced by the previous steps. To From a performance standpoint, the PMA guarantees that a determine the next address that is used when data is written continuous stream of move instructions (see ahead), are...

  • Page 144: Oscillator Lock

    Full-Speed USB 20.2.3 Oscillator Lock For a USB IN transaction, the USB SIE is reading data from the PMA and sending the data to the USB host. The follow- The enCoRe V device can operate without using any exter- ing steps must be used to set up a PMA channel for a USB nal components, such as a crystal, and still achieve the IN transaction.

  • Page 145: Usb Suspend

    Full-Speed USB 20.2.5 USB Suspend of frame registers (USB_SOFx). These registers are reset after the device comes out of sleep. Loss of USB activity, while the USB VBus is still asserted, An alternative is to simply disconnect from the USB bus indicates that the device must enter USB Suspend mode.
  • Page 146 Full-Speed USB Figure 20-2. Transceiver and Regulator Block Diagram VOLTAGE PS2 Pull Up REGULATOR 3.3V 1.5K TRANSMITTER RECEIVERS RSE0 enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H...

  • Page 147: Register Definitions

    Full-Speed USB 20.3 Register Definitions The following registers are related to Full-Speed USB in the enCoRe V device. For a complete table of the Full-Speed USB registers, refer to the Registers table Summary Table of the System Resource Registers on page 93.

  • Page 148: Usbio_Cr0 Register

    Full-Speed USB 20.3.3 USBIO_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,34h USBIO_CR0 TSE0 # : 0 The USB I/O Control Register 0 (USBIO_CR0) is used for Bit 6: TSE0.

  • Page 149: Ep0_Cr Register

    Full-Speed USB 20.3.5 EP0_CR Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Setup ACKed 0,36h EP0_CR IN Received Mode[3:0] # : 00 Received Received Transaction The Endpoint Control Register (EP0_CR) is used to config- Bit 6: IN Received.

  • Page 150: Ep0_Cnt Register

    Full-Speed USB 20.3.6 EP0_CNT Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,37h EP0_CNT Data Toggle Data Valid Byte Count[3:0] # : 00 The Endpoint 0 Count Register (EP0_CNT) is used to con- Bit 6: Data Valid.

  • Page 151: Epx_Cnt1 Register

    Full-Speed USB 20.3.8 EPx_CNT1 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,41h EP1_CNT1 Data Count[7:0] RW : 00 0,43h EP2_CNT1 Data Count[7:0] RW : 00 0,45h EP3_CNT1 Data Count[7:0] RW : 00 0,47h...

  • Page 152: Epx_Cnt0 Register

    Full-Speed USB 20.3.9 EPx_CNT0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,40h EP1_CNT0 Data Toggle Data Valid Count MSB # : 0 0,42h EP2_CNT0 Data Toggle Data Valid Count MSB # : 0 0,44h...

  • Page 153: Epx_Cr0 Register

    Full-Speed USB 20.3.10 EPx_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,54h EP1_CR0 Stall NAK_INT_EN ACKed Tx Mode[3:0] # : 00 1,55h EP2_CR0 Stall NAK_INT_EN ACKed Tx Mode[3:0] # : 00 1,56h...

  • Page 154: Pmax_Wa Register

    Full-Speed USB 20.3.11 PMAx_WA Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,34h PMA0_WA Write Address[7:0] RW : 00 1,35h PMA1_WA Write Address[7:0] RW : 00 1,36h PMA2_WA Write Address[7:0] RW : 00 1,37h...

  • Page 155: Pmax_Dr Register

    Full-Speed USB 20.3.12 PMAx_DR Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,58h PMA0_DR Data Byte[7:0] RW : 00 0,59h PMA1_DR Data Byte[7:0] RW : 00 0,5Ah PMA2_DR Data Byte[7:0] RW : 00 0,5Bh...

  • Page 156: Pmax_Ra Register

    Full-Speed USB 20.3.13 PMAx_RA Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,3Ch PMA0_RA Read Address[7:0] RW : 00 1,3Dh PMA1_RA Read Address[7:0] RW : 00 1,3Eh PMA2_RA Read Address[7:0] RW : 00 1,3Fh...

  • Page 157: Usb_Cr1 Register

    Full-Speed USB 20.3.14 USB_CR1 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,30h USB_CR1 BusActivity EnableLock RegEnable # : 0 The USB Control Register 1 (USB_CR1) is used to config- Bit 1: EnableLock.

  • Page 158: Imo_Tr1 Register

    Full-Speed USB 20.3.16 IMO_TR1 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,FAh IMO_TR1 Fine Trim[2:0] RW : 00 INTERNAL Register – The Internal Main Oscillator Trim Bits 2 to 0: Fine Trim[2:0]. These bits provide a fine tuning Register 1 (IMO_TR1) fine tunes the IMO frequency.

  • Page 159: Section D: Registers

    Section D: Registers The Registers section discusses the registers of the enCoRe V device. It lists all the registers in mapping tables, in address order. For easy reference, each register is linked to the page of a detailed description located in the next chapter. This section includes the following chapter: Register Reference chapter on page 163.
  • Page 160 Register Map Bank 0 Table: User Space PRT0DR EP1_CNT0 PRT0IE EP1_CNT1 EP2_CNT0 EP2_CNT1 PRT1DR EP3_CNT0 PRT1IE EP3_CNT1 EP4_CNT0 EP4_CNT1 PRT2DR EP5_CNT0 I2C_XCFG PRT2IE EP5_CNT1 EP6_CNT0 I2C_ADDR EP6_CNT1 PRT3DR EP7_CNT0 PRT3IE EP7_CNT1 EP8_CNT0 EP8_CNT1 PRT4DR CUR_PP PRT4IE STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR PMA0_DR...
  • Page 161 EP0_DR6 CPU_SCR1 EP0_DR7 CPU_SCR0 Gray fields are reserved. # Access is bit specific. Register Map Bank 1 Table: Configuration Space PRT0DM0 PMA4_RA PRT0DM1 PMA5_RA PMA6_RA PMA7_RA PRT1DM0 PMA8_WA PRT1DM1 PMA9_WA PMA10_WA PMA11_WA PRT2DM0 PMA12_WA PRT2DM1 PMA13_WA PMA14_WA PMA15_WA PRT3DM0 PMA8_RA PRT3DM1 PMA9_RA PMA10_RA...
  • Page 162 PMA2_WA PMA3_WA CPU_F PMA4_WA PMA5_WA PMA6_WA IMO_TR1 PMA7_WA PMA0_RA PMA1_RA USB_MISC_CR PMA2_RA PMA3_RA Gray fields are reserved # Access is bit specific. enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H...

  • Page 163: 21. Register Reference

    21. Register Reference This chapter is a reference for all the enCoRe V device registers in address order, for Bank 0 and Bank 1. The most detailed descriptions of the enCoRe V registers are in the Register Definitions section of each chapter. The registers that are in both banks are incorporated with the Bank 0 registers, designated with an ‘x’, rather than a ‘0’...

  • Page 164: Bank 0 Registers

    0,00h 21.3 Bank 0 Registers The following registers are all in bank 0 and are listed in address order. An ‘x’ before the comma in the register’s address indi- cates that the register can be accessed in Bank 0 and Bank 1, independent of the XIO bit in the CPU_F register. Registers that are in both Bank 0 and Bank 1 are listed in address order in Bank 0.
  • Page 165 0,01h 21.3.2 PRTxIE Port Interrupt Enable Registers Individual Register Names and Addresses: 0,01h PRT0IE : 0,01h PRT1IE : 0,05h PRT2IE : 0,09h PRT3IE : 0,0Dh PRT4IE : 0,11h Access : POR RW : 00 Interrupt Enables[7:0] Bit Name These registers enable or disable interrupts from individual GPIO pins. The upper nibble of the PRT4IE register returns the last data bus value when read and must be masked off before using this information.
  • Page 166 0,29h 21.3.3 SPI_TXR SPI Transmit Data Register Individual Register Names and Addresses: 0,29h SPI_TXR : 0,29h Access : POR W : 00 Bit Name Data[7:0] This register is the SPI’s transmit data register. For additional information, refer to the Register Definitions on page 125 in the SPI chapter.
  • Page 167 0,2Ah 21.3.4 SPI_RXR SPI Receive Data Register Individual Register Names and Addresses: 0,2Ah SPI_RXR : 0,2Ah Access : POR R : 00 Bit Name Data[7:0] This register is the SPI’s receive data register. For additional information, refer to the Register Definitions on page 125 in the SPI chapter.
  • Page 168 0,2Bh 21.3.5 SPI_CR SPI Control Register Individual Register Names and Addresses: 0,2Bh SPI_CR : 0,2Bh Access : POR RW : 0 R : 0 R : 0 R : 1 R : 0 RW : 0 RW : 0 RW : 0 Bit Name LSb First Overrun...
  • Page 169 0,31h 21.3.6 USB_SOF0 USB Start-of-Frame Register 0 Individual Register Names and Addresses: 0,31h USB_SOF0 : 0,31h Access : POR R : 00 Bit Name Frame Number[7:0] This register is a USB Start-of-Frame register 0. For additional information, refer to the Register Definitions on page 147 in the Full-Speed USB chapter.
  • Page 170 0,32h 21.3.7 USB_SOF1 USB Start-of-Frame Register 1 Individual Register Names and Addresses: 0,32h USB_SOF1 : 0,32h Access : POR R : 0 Bit Name Frame Number[10:8] This register is a USB Start-of-Frame register 1. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits must always be written with a value of ‘0’.
  • Page 171 0,33h 21.3.8 USB_CR0 USB Control Register 0 Individual Register Names and Addresses: 0,33h USB_CR0 : 0,33h Access : POR RW : 0 RW : 00 Bit Name USB Enable Device Address[6:0] This register is a USB control register 0. The USB_MISC_CR register on page 220 must be set correctly for the bits in this register to function as described here.
  • Page 172 0,34h 21.3.9 USBIO_CR0 USB I/O Control Register 0 Individual Register Names and Addresses: 0,34h USBIO_CR0 : 0,34h Access : POR RW : 0 RW : 0 RW : 0 R : 0 Bit Name TSE0 This register is a USBIO manual control register 0. This register is used to manually control or read the USB differential state of the D+ and D–...
  • Page 173 0,35h 21.3.10 USBIO_CR1 USB I/O Control Register 1 Individual Register Names and Addresses: 0,35h USBIO_CR1 : 0,35h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 R : 1 R : 1 Bit Name IOMode...
  • Page 174 0,36h 21.3.11 EP0_CR Endpoint 0 Control Register Individual Register Names and Addresses: 0,36h EP0_CR : 0,36h Access : POR RC : 0 RC : 0 RC : 0 RC : 0 RW : 0 Bit Name Setup ACKed Mode[3:0] IN Received OUT Received Received Transaction...
  • Page 175 0,37h 21.3.12 EP0_CNT Endpoint 0 Count Register Individual Register Names and Addresses: 0,37h EP0_CNT : 0,37h Access : POR RW : 0 RC : 0 RW : 0 Bit Name Data Toggle Data Valid Byte Count[3:0] The Endpoint 0 Count register (EP0_CNT) configures endpoint 0. In the table, note that reserved bits are grayed table cells and are not described in the bit description section.
  • Page 176 0,38h 21.3.13 EP0_DRx Endpoint 0 Data Registers Individual Register Names and Addresses: 0,38h EP0_DR0 : 0,38h EP0_DR1 : 0,39h EP0_DR2 : 0,3Ah EP0_DR3 : 0,3Bh EP0_DR4 : 0,3Ch EP0_DR5 : 0,3Dh EP0_DR6 : 0,3Eh EP0_DR7 : 0,3Fh Access : POR RW : 00 Data Byte[7:0] Bit Name...
  • Page 177 0,40h 21.3.14 EPx_CNT0 Endpoint Count 0 Registers Individual Register Names and Addresses: 0,40h EP1_CNT0 : 0,40h EP2_CNT0 : 0,42h EP3_CNT0 : 0,44h EP4_CNT0 : 0,46h EP5_CNT0 : 0,48h EP6_CNT0 : 0,4Ah EP7_CNT0 : 0,4Ch EP8_CNT0 : 0,4Eh Access : POR RW : 0 RC : 0 # : 0...
  • Page 178 0,41h 21.3.15 EPx_CNT1 Endpoint Count 1 Registers Individual Register Names and Addresses: 0,41h EP1_CNT1 : 0,41h EP2_CNT1 : 0,43h EP3_CNT1 : 0,45h EP4_CNT1 : 0,47h EP5_CNT1 : 0,49h EP6_CNT1 : 0,4Bh EP7_CNT1 : 0,4Dh EP8_CNT1 : 0,4Fh Access : POR RW : 00 Data Count[7:0] Bit Name...
  • Page 179 0,58h 21.3.16 PMAx_DR PSoC Memory Arbiter Data Registers Individual Register Names and Addresses: 0,58h PMA0_DR : 0,58h PMA1_DR : 0,59h PMA2_DR : 0,5Ah PMA3_DR : 0,5Bh PMA4_DR : 0,5Ch PMA5_DR : 0,5Dh PMA6_DR : 0,5Eh PMA7_DR : 0,5Fh PMA8_DR : 0,64h PMA9_DR : 0,65h PMA10_DR : 0,66h PMA11_DR : 0,67h...
  • Page 180 0,79h 21.3.17 CMP_MUX Comparator Multiplexer Register Individual Register Names and Addresses: 0,79h CMP_MUX : 0,79h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name INP1[1:0] INN1[1:0] INP0[1:0] INN0[1:0] This register contains control bits for input selection of comparators 0 and 1. For additional information, refer to the Register Definitions on page 111 in the Comparators chapter .
  • Page 181 0,B0h 21.3.18 PT0_CFG Programmable Timer 0 Configuration Register Individual Register Names and Addresses: 0,B0h PT0_CFG : 0,B0h Access : POR RW : 0 RW : 0 RW : 0 Bit Name CLKSEL One Shot START This register configures the programmable timer 0. In the table, note that reserved bits are grayed table cells and are not described in the bit description section.
  • Page 182 0,B1h 21.3.19 PTx_DATA1 Programmable Timers Data Register 1 Individual Register Names and Addresses: 0,B1h PT0_DATA1 : 0,B1h PT1_DATA1 : 0,B4h PT2_DATA1 : 0,B7h Access : POR RW : 00 Bit Name DATA[7:0] These registers hold the eight bits of the programmable timer’s count value for the device. For additional information, refer to the Register Definitions on page 139 in the Programmable Timer chapter .
  • Page 183 0,B2h 21.3.20 PTx_DATA0 Programmable Timers Data Register 0 Individual Register Names and Addresses: 0,B2h PT0_DATA0 : 0,B2h PT1_DATA0 : 0,B5h PT2_DATA0 : 0,B8h Access : POR RW : 00 Bit Name DATA[7:0] These registers provide the programmable timer with its lower eight bits of the count value. For additional information, refer to the Register Definitions on page 139 in the Programmable Timer chapter .
  • Page 184 0,B3h 21.3.21 PT1_CFG Programmable Timer 1 Configuration Register Individual Register Names and Addresses: 0,B3h PT1_CFG : 0,B3h Access : POR RW : 0 RW : 0 RW : 0 Bit Name CLKSEL One Shot START This register configures the programmable timer 1. In the table, note that reserved bits are grayed table cells and are not described in the bit description section.
  • Page 185 0,B6h 21.3.22 PT2_CFG Programmable Timer 2 Configuration Register Individual Register Names and Addresses: 0,B6h PT2_CFG : 0,B6h Access : POR RW : 0 RW : 0 RW : 0 Bit Name CLKSEL One Shot START This register configures the programmable timer 2. In the table, note that reserved bits are grayed table cells and are not described in the bit description section.
  • Page 186 0,C8h 21.3.23 I2C_XCFG C Extended Configuration Register Individual Register Names and Addresses: 0,C8h I2C_XCFG: 0,C8h Access : POR RW : 0 Bit Name HW Addr En This register configures enhanced features. The Enable bit (bit 0) of the I2C_CFG (0,D6h) register should be set to ‘1’ for the I2C enhanced features to work.
  • Page 187 0,CAh 21.3.24 I2C_ADDR C Slave Address Register Individual Register Names and Addresses: 0,CAh 0,D0h I2C_ADDR : 0,CAh Access : POR RW : 00 Bit Name Slave Address[6:0] This register holds the slave’s 7-bit address. When hardware address compare mode is not enabled in the I2C_XCFG register, this register is not in use.
  • Page 188 0,D0h 21.3.25 CUR_PP Current Page Pointer Register Individual Register Names and Addresses: 0,D0h CUR_PP : 0,D0h Access : POR RW : 0 Bit Name Page Bits[2:0] This register is used to set the effective SRAM page for normal memory accesses in a multi-SRAM page enCoRe V device. It is only used when a device has more than one SRAM page.
  • Page 189 0,D1h 21.3.26 STK_PP Stack Page Pointer Register Individual Register Names and Addresses: 0,D1h STK_PP : 0,D1h Access : POR RW : 0 Bit Name Page Bits[2:0] This register is used to set the effective SRAM page for stack memory accesses in a multi-SRAM page enCoRe V device. It is only used when a device has more than one SRAM page.
  • Page 190 0,D3h 21.3.27 IDX_PP Indexed Memory Access Page Pointer Register Individual Register Names and Addresses: 0,D3h IDX_PP : 0,D3h Access : POR RW : 0 Bit Name Page Bits[2:0] This register is used to set the effective SRAM page for indexed memory accesses in a multi-SRAM page enCoRe V device. This register is only used when a device has more than one page of SRAM.
  • Page 191 0,D4h 21.3.28 MVR_PP MVI Read Page Pointer Register Individual Register Names and Addresses: 0,D4h MVR_PP : 0,D4h Access : POR RW : 0 Bit Name Page Bits[2:0] This register is used to set the effective SRAM page for MVI read memory accesses in a multi-SRAM page enCoRe V device. This register is only used when a device has more than one page of SRAM.
  • Page 192 0,D5h 21.3.29 MVW_PP MVI Write Page Pointer Register Individual Register Names and Addresses: 0,D5h MVW_PP : 0,D5h Access : POR RW : 0 Bit Name Page Bits[2:0] This register is used to set the effective SRAM page for MVI write memory accesses in a multi-SRAM page enCoRe V device. This register is only used when a device has more than one page of SRAM.
  • Page 193 0,D6h 21.3.30 I2C_CFG C Configuration Register Individual Register Names and Addresses: 0,D6h I2C_CFG : 0,D6h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name PSelect Stop IE Clock Rate[1:0] Enable This register is used to set the basic operating modes, baud rate, and interrupt selection. In the table, note that reserved bits are grayed table cells and are not described in the bit description section.
  • Page 194 0,D7h 21.3.31 I2C_SCR C Status and Control Register Individual Register Names and Addresses: 0,D7h I2C_SCR : 0,D7h Access : POR RC : 0 RC : 0 RW : 0 RC : 0 RW : 0 RC : 0 RC : 0 Bit Name Bus Error Stop Status...
  • Page 195 0,D8h 21.3.32 I2C_DR C Data Register Individual Register Names and Addresses: 0,D8h I2C_DR : 0,D8h Access : POR RW : 00 Bit Name Data[7:0] This register provides read/write access to the Shift register. This register is read only for received data and write only for transmitted data. For additional information, refer to the Register Definitions on page 106 in the I2C Slave chapter .
  • Page 196 0,DAh 21.3.33 INT_CLR0 Interrupt Clear Register 0 Individual Register Names and Addresses: 0,DAh INT_CLR0 : 0,DAh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name Sleep...
  • Page 197 0,DAh 21.3.33 INT_CLR0 (continued) Timer0 Read 0 No posted interrupt for Timer. Read 1 Posted interrupt present for Timer. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect. Write 1 AND ENSWINT = 1 Post an interrupt for Timer.
  • Page 198 0,DBh 21.3.34 INT_CLR1 Interrupt Clear Register 1 Individual Register Names and Addresses: 0,DBh INT_CLR1 : 0,DBh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name Endpoint3...
  • Page 199 0,DBh 21.3.34 INT_CLR1 (continued) Endpoint0 Read 0 No posted interrupt for USB Endpoint0. Read 1 Posted interrupt present for USB Endpoint0. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect.
  • Page 200 0,DCh 21.3.35 INT_CLR2 Interrupt Clear Register 2 Individual Register Names and Addresses: 0,DCh INT_CLR2 : 0,DCh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name USB_WAKE Endpoint8 Endpoint7 Endpoint6...
  • Page 201 0,DCh 21.3.35 INT_CLR2 (continued) Endpoint7 Read 0 No posted interrupt for USB Endpoint7. Read 1 Posted interrupt present for USB Endpoint7. Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect.
  • Page 202 0,DEh 21.3.36 INT_MSK2 Interrupt Mask Register 2 Individual Register Names and Addresses: 0,DEh INT_MSK2 : 0,DEh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name USB Wakeup Endpoint8 Endpoint7 Endpoint6...
  • Page 203 0,DFh 21.3.37 INT_MSK1 Interrupt Mask Register 1 Individual Register Names and Addresses: 0,DFh INT_MSK1 : 0,DFh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 USB Bus Bit Name...
  • Page 204 0,E0h 21.3.38 INT_MSK0 Interrupt Mask Register 0 Individual Register Names and Addresses: 0,E0h INT_MSK0 : 0,E0h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name Sleep...
  • Page 205 0,E1h 21.3.39 INT_SW_EN Interrupt Software Enable Register Individual Register Names and Addresses: 0,E1h INT_SW_EN : 0,E1h Access : POR RW : 0 Bit Name ENSWINT This register is used to enable software interrupts. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits must always be written with a value of ‘0’.
  • Page 206 0,E2h 21.3.40 INT_VC Interrupt Vector Clear Register Individual Register Names and Addresses: 0,E2h INT_VC : 0,E2h Access : POR RC : 00 Bit Name Pending Interrupt[7:0] This register returns the next pending interrupt and clears all pending interrupts when written. For additional information, refer to the Register Definitions on page 46 in the Interrupt Controller chapter.
  • Page 207 0,E3h 21.3.41 RES_WDT Reset Watchdog Timer Register Individual Register Names and Addresses: 0,E3h RES_WDT : 0,E3h Access : POR W : 00 Bit Name WDSL_Clear[7:0] This register is used to clear the watchdog timer alone, or clear both the watchdog timer and the sleep timer together. For additional information, refer to the Register Definitions on page 82 in the Sleep and Watchdog chapter.
  • Page 208 x,F7h 21.3.42 CPU_F M8C Flag Register Individual Register Names and Addresses: x,F7h CPU_F : x,F7h Access : POR RL : 0 RL : 0 RL : 0 RL : 0 RL : 0 RL : 0 Bit Name PgMode[1:0] BINC Carry Zero This register provides read access to the M8C flags.
  • Page 209 x,F7h 21.3.42 CPU_F (continued) Zero Set by the M8C CPU Core to indicate whether there was a zero result in the previous logical/arithme- tic operation. Not equal to zero. Equal to zero. M8C does not process any interrupts. Interrupt processing enabled. enCoRe™...
  • Page 210 x,FEh 21.3.43 CPU_SCR1 System Status and Control Register 1 Individual Register Names and Addresses: x,FEh CPU_SCR1: x,FEh Access : POR R : 0 RW : 0 RW : 0 Bit Name IRESS SLIMO[1:0] IRAMDIS This register is used to convey the status and control of events related to internal resets and watchdog reset. In the table, note that reserved bits are grayed table cells and are not described in the bit description section.
  • Page 211 x,FFh 21.3.44 CPU_SCR0 System Status and Control Register 0 Individual Register Names and Addresses: x,FFh CPU_SCR0 : x,FFh Access : POR R : 0 RC : 0 RC : 1 RW : 0 RW : 0 Bit Name GIES WDRS PORS Sleep STOP...

  • Page 212: Bank 1 Registers

    1,00h 21.4 Bank 1 Registers The following registers are all in bank 1 and are listed in address order. Registers that are in both Bank 0 and Bank 1 are listed in address order in the section titled Bank 0 Registers on page 164.
  • Page 213 1,01h 21.4.2 PRTxDM1 Port Drive Mode Bit Registers 1 Individual Register Names and Addresses: 1,01h PRT0DM1 : 1,01h PRT1DM1 : 1,05h PRT2DM1 : 1,09h PRT3DM1 : 1,0Dh PRT4DM1 : 1,11h Access : POR RW : FF Drive Mode 1[7:0] Bit Name This register is one of three registers where the combined value determines the unique drive mode of each bit in a GPIO port.
  • Page 214 1,29h 21.4.3 SPI_CFG SPI Configuration Register Individual Register Names and Addresses: 1,29h SPI_CFG : 1,29h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name Clock Sel [2:0] Bypass SS_EN_ Int Sel...
  • Page 215 1,30h 21.4.4 USB_CR1 USB Control Register 1 Individual Register Names and Addresses: 1,30h USB_CR1 : 1,30h Access : POR RC : 0 RW : 0 RW : 0 Bit Name BusActivity EnableLock RegEnable This register is used to configure the internal regulator and the oscillator tuning capability. This register is only used by the CY8C20XX6A/AS/LCY7C64215 enCoRe V devices.
  • Page 216 1,34h 21.4.5 PMAx_WA PSoC Memory Arbiter Write Address Registers Individual Register Names and Addresses: 1,34h PMA0_WA : 1,34h PMA1_WA : 1,35h PMA2_WA : 1,36h PMA3_WA : 1,37h PMA4_WA : 1,38h PMA5_WA : 1,39h PMA6_WA : 1,3Ah PMA7_WA : 1,3Bh PMA8_WA : 1,44H PMA9_WA : 1,45H PMA10_WA : 1,46H...
  • Page 217 1,3Ch 21.4.6 PMAx_RA PSoC Memory Arbiter Read Address Registers Individual Register Names and Addresses: 1,3Ch PMA0_RA : 1,3Ch PMA1_RA : 1,3Dh PMA2_RA : 1,3Eh PMA3_RA : 1,3Fh PMA4_RA : 1,40h PMA5_RA : 1,41h PMA6_RA : 1,42h PMA7_RA : 1,43h PMA8_RA : 1,4Ch PMA9_RA : 1,4Dh PMA10_RA : 1,4Eh PMA11_RA : 1,4Fh...
  • Page 218 1,54h 21.4.7 EPx_CR0 Endpoint Control Registers 0 Individual Register Names and Addresses: 1,54h EP1_CR0 : 1,54h EP2_CR0 : 1,55h EP3_CR0 : 1,56h EP4_CR0 : 1,57h EP5_CR0 : 1,58h EP6_CR0 : 1,59h EP7_CR0 : 1,5Ah EP7_CR0 : 1,5Bh Access : POR RW : 0 RW : 0 RC : 0...
  • Page 219 x,6Ch 21.4.8 TMP_DRx Temporary Data Registers Individual Register Names and Addresses: x,6Ch TMP_DR0 : x,6Ch TMP_DR1 : x,6Dh TMP_DR2 : x,6Eh TMP_DR3 : x,6Fh Access : POR RW : 00 Bit Name Data[7:0] These registers enhance the performance in multiple SRAM page enCoRe V devices. All bits in this register are reserved for enCoRe V devices with 256 bytes of SRAM.
  • Page 220 1,BDh 21.4.9 USB_MISC_CR USB Miscellaneous Control Register Individual Register Names and Addresses: 1,BDh USB_MISC_CR: 1,BDh Access : POR RW : 0 RW : 0 RW : 0 Bit Name USB_SE_EN USB_ON USB_CLK_ON The USB Miscellaneous Control Register controls the clocks to the USB block to make IMO work with better accuracy for the USB part and to disable the single-ended input of USBIO in the case of a non-USB part.
  • Page 221 1,D2h 21.4.10 ECO_ENBUS External Oscillator ENBUS Register Individual Register Names and Addresses: 1,D2h ECO_ENBUS : 1,D2h Access : POR RW : 7 Bit Name ECO_ENBUS[2:0] The ECO_ENBUS register is used to disable and enable the external crystal oscillator (ECO). In the table, note that reserved bits are grayed table cells and are not described in the bit description section.
  • Page 222 1,D3h 21.4.11 ECO_TRIM External Oscillator Trim Register Individual Register Names and Addresses: 1,D3h ECO_TRIM : 1,D3h Access : POR RW : 4 RW : 1 Bit Name ECO_XGM[2:0] ECO_LP[1:0] This register trims the external oscillator gain and power settings. These settings in this register should not be changed from their default state. In the table, note that reserved bits are grayed table cells and are not described in the bit description section.
  • Page 223 1,D8h 21.4.12 MUX_CRx Analog Mux Port Bit Enable Registers Individual Register Names and Addresses: 1,D8h MUX_CR0 : 1,D8h MUX_CR1 : 1,D9h MUX_CR2 : 1,DAh MUX_CR3 : 1,DBh MUX_CR4 : 1,DFh Access : POR RW : 00 ENABLE[7:0] Bit Name This register is used to control the connection between the analog mux bus and the corresponding pin. Port 4 is a 4-bit port, so the upper 4 bits of the MUX_CR4 register are reserved and return zeros when read.
  • Page 224 1,DCh 21.4.13 IO_CFG1 Input/Output Configuration Register 1 Individual Register Names and Addresses: 1,DCh IO_CFG1 : 1,DCh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name P1_LOW_ SPICLK_ StrongP Range[1:0]...
  • Page 225 1,DDh 21.4.14 OUT_P1 Output Override to Port 1 Register Individual Register Names and Addresses: 1,DDh OUT_P1: 1,DDh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name P16D P16EN RSVD RSVD RSVD P12EN RSVD P10EN This register enables specific internal signals to be output to Port 1 pins.
  • Page 226 1,DDh 21.4.14 OUT_P1 (continued) P10EN Bit enables pin P1[0] to output the sleep interrupt (SLPINT). No internal signal output to P1[0] Output SLPINT to P1[0] enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H...
  • Page 227 1,DEh 21.4.15 IO_CFG2 Input/Output Configuration Register 2 Individual Register Names and Addresses: 1,DEh IO_CFG2 : 1,DEh Access : POR RW : 0 RW : 0 Bit Name REG_LEVEL[2:0] REG_CLOCK[1:0] The Input/Output Configuration 2 Register (IO_CFG2) selects output regulated supply and clock rates. In the table, note that reserved bits are grayed table cells and are not described in the bit description section.
  • Page 228 1,E0h 21.4.16 OSC_CR0 Oscillator Control Register 0 Individual Register Names and Addresses: 1,E0h OSC_CR0: 1,E0h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 010b Bit Name X32ON Disable Buzz No Buzz Sleep[1:0] CPU Speed[2:0] This register is used to configure various features of internal clock sources and clock nets.
  • Page 229 1,E1h 21.4.17 ECO_CFG External Oscillator Trim Configuration Register Individual Register Names and Addresses: 1,E1h ECO_CFG : 1,E1h Access : POR RW : 0 RW : 0 RW : 0 Bit Name ECO_LPM ECO_EXW ECO_EX This register provides ECO status and control information. In the table, note that reserved bits are grayed table cells and are not described in the bit description section.
  • Page 230 1,E2h 21.4.18 OSC_CR2 Oscillator Control Register 2 Individual Register Names and Addresses: 1,E2h OSC_CR2 : 1,E2h Access : POR RW : 0 RW : 0 RW : 0 Bit Name CLK48MEN EXTCLKEN RSVD This register is used to configure various features of internal clock sources and clock nets. In the table, note that reserved bits are grayed table cells and are not described in the bit description section.
  • Page 231 1,E3h 21.4.19 VLT_CR Voltage Monitor Control Register Individual Register Names and Addresses: 1,E3h VLT_CR: 1,E3h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name HPOR PORLEV[1:0] LVDTBEN VM[2:0] This register is used to set the trip points for POR and LVD. In the table, note that reserved bits are grayed table cells and are not described in the bit description section.
  • Page 232 1,E4h 21.4.20 VLT_CMP Voltage Monitor Comparators Register Individual Register Names and Addresses: 1,E4h VLT_CMP : 1,E4h Access : POR R : 0 Bit Name This register reads the state of the internal supply voltage monitors. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits must always be written with a value of ‘0’.
  • Page 233 1,E8h 21.4.21 IMO_TR Internal Main Oscillator Trim Register Individual Register Names and Addresses: 1,E8h IMO_TR : 1,E8h Access : POR RW : 00 Bit Name Trim[7:0] This register is used to manually center the Internal Main Oscillator’s (IMO) output to a target frequency. It is strongly recommended that you do not alter this register’s values except to load factory trim settings when changing IMO range.
  • Page 234 1,E9h 21.4.22 ILO_TR Internal Low-speed Oscillator Trim Register Individual Register Names and Addresses: 1,E9h ILO_TR : 1,E9h Access : POR RW : 0 RW : 0 RW : 08 Bit Name PD_MODE ILOFREQ Freq Trim[3:0] This register sets the adjustment for the Internal Low-speed Oscillator (ILO). It is strongly recommended that you do not alter this register’s Freq Trim[3:0] values.
  • Page 235 1,EBh 21.4.23 SLP_CFG Sleep Configuration Register Individual Register Names and Addresses: 1,EBh SLP_CFG : 1,EBh Access : POR RW : 0 Bit Name PSSDC[1:0] This register sets up the sleep duty cycle. In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits must always be written with a value of ‘0’.
  • Page 236 1,ECh 21.4.24 SLP_CFG2 Sleep Configuration Register 2 Individual Register Names and Addresses: 1,ECh SLP_CFG2 : 1,ECh Access : POR RW : 0 RW : 0 RW : 0 Bit Name ALT_Buzz[1:0] I2C_ON LSO_OFF This register holds the configuration for I2C sleep, deep sleep, and buzz. In the table, note that reserved bits are grayed table cells and are not described in the bit description section.
  • Page 237 1,EDh 21.4.25 SLP_CFG3 Sleep Configuration Register 3 Individual Register Names and Addresses: 1,EDh SLP_CFG3 : 1,EDh Access : POR RW : 1 RW : 11 RW : 11 RW : 11 Bit Name DBL_TAPS T2TAP[1:0] T1TAP[1:0] T0TAP[1:0] This register holds the configuration of the wakeup sequence taps. It is strongly recommended to not alter this register setting .
  • Page 238 1,FAh 21.4.26 IMO_TR1 Internal Main Oscillator Trim Register 1 Individual Register Names and Addresses: 1,FAh IMO_TR1 : 1,FAh Access : POR W : 0 Bit Name FineTrim[2:0] This register is used to fine tune the IMO frequency. It is strongly recommended that the user not alter this register’s values. In the table, note that reserved bits are grayed table cells and are not described in the bit description section.

  • Page 239: Section E: Glossary

    Section E: Glossary The Glossary section explains the terminology used in this technical reference manual. Glossary terms are characterized in bold, italic font throughout the text of this manual. In a CPU, a register in which intermediate results are stored. Without an accumulator, it is neces- accumulator sary to write the result of each calculation (addition, subtraction, shift, and so on) to main mem- ory and read them back.
  • Page 240 An array, also known as a vector or list, is one of the simplest data structures in computer pro- array gramming. Arrays hold a fixed number of equally-sized data elements, generally of the same data type. Individual elements are accessed by index using a consecutive range of integers, as opposed to an associative array.
  • Page 241 1. A functional unit that performs a single function, such as an oscillator. block 2. A functional unit that may be configured to perform one of several functions, such as a digital block or an analog block. In mathematics and computer science, Boolean algebras or Boolean lattices, are algebraic Boolean Algebra structures which “capture the essence”...
  • Page 242 The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is clock sometimes used to synchronize different logic blocks. A circuit that is used to generate a clock signal. clock generator The logic gates constructed using MOS transistors connected in a complementary manner. CMOS CMOS is an acronym for complementary metal-oxide semiconductor.
  • Page 243 Pertaining to the pre-defined initial, original, or specific setting, condition, value, or action a sys- default value tem assumes, uses, or takes in the absence of instructions from the user. The device referred to in this manual is the enCoRe V chip, unless otherwise specified. device An unpackaged Integrated Circuit (IC), normally cut from a wafer.
  • Page 244 A group of flash ROM blocks where flash block numbers always begin with ‘0’ in an individual Flash bank flash bank. A flash bank also has its own block level protection information. The smallest amount of flash ROM space that may be programmed at one time and the smallest Flash block amount of flash space that may be protected.
  • Page 245 A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an inter-integrated circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics.
  • Page 246 A circuit that holds a signal to the last driven value, even when the signal becomes un-driven. keeper The time or delay that it takes for a signal to pass-through a given circuit or network. latency The binary digit, or bit, in a binary number that represents the least significant value (typically the least significant bit right-hand bit).
  • Page 247 A device that controls the timing for data exchanges between two devices. Or when devices are master device cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device .
  • Page 248 See Boolean Algebra . See Boolean Algebra . See Boolean Algebra . A circuit that may be crystal controlled and is used to generate a clock frequency. oscillator The electrical signal or signals which are produced by an analog or digital block. output The means of communication in which digital data is sent multiple bits at a time, with each simul- parallel...
  • Page 249 A set of rules. Particularly the rules that govern networked communications. protocol The software for Cypress’ Programmable System-on-Chip technology. PSoC Designer™ A rapid change in some characteristic of a signal (for example, phase or frequency) from a base- pulse line value to a higher or lower value, followed by a rapid return to the baseline value.
  • Page 250 1. Pertaining to a process in which all events occur one after the other. serial 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. To force a bit/register to a value of logic 1. The time it takes for an output signal or value to stabilize after the input has changed from one settling time value to another.
  • Page 251 The actual implementation (in hardware or software) of a function that can be considered to con- state machine sist of a set of states through which it sequences. A bit in a register that maintains its value past the time of the event that caused its transition has sticky passed.
  • Page 252 A name for a power net meaning “voltage drain.” The most positive power supply signal. Usually 5 or 3.3 volts. Not guaranteed to stay the same value or level when not in scope. volatile A name for a power net meaning “voltage source.” The most negative power supply signal. A timer that must be serviced periodically.
  • Page 253 Index switch operation 97 clocks digital, See digital clocks 32 kHz clock selection 72 CMP_MUX register 180 32-Pin Part Pinout 16 comparator in regulated IO 88 48-pin OCD part pinout 17 configuration register in SPI 48-Pin Part Pinout 18 SPI_CFG register 128 control register in SPI SPI_CR register 127 conventions, documentation...
  • Page 254 history 12 overview 9 help, getting Drive Mode 0 bits 212 development kits 12 Drive Mode 1 bits 213 support 12 upgrades 12 Enable bit 193 ENABLE bits I2C bit in MUX_CRx registers 223 in INT_CLR0 register 196 in SPI_CR register 168 in INT_MSK0 register 204 ENSWINT bit 50 I2C slave 103...
  • Page 255 latency and priority 45 P16D bit 225 posted vs pending interrupts 45 P16EN bit 225 register definitions 46 Page bits Interrupt Enables bits 165 in CUR_PP register 188 interrupt modes in GPIO 54 in IDX_PP register 190 interrupt table 45 in MVR_PP register 191 interrupts in RAM paging 39 in MVW_PP register 192...
  • Page 256 index memory page pointer 40 application overview 81 interrupts 39 architecture 78 MVI instructions 39 bandgap refresh 85 register definitions 41 register definitions 82 stack operations 38 sleep sequence 84 ReadBlock function in SROM 34 sleep timer 81 reference of all registers 163 timing diagrams 84 register conventions 13 wake up sequence 85...
  • Page 257 Calibrate0 function 36 USBIO_CR1 register 148 Calibrate1 function 36 EraseAll function 35 EraseBlock function 35 function descriptions 33 V Monitor bit ProtectBlock function 35 in INT_CLR0 register 197 ReadBlock function 34 in INT_MSK0 register 204 SWBootReset function 33 VLT_CMP register 122 TableRead function 35 VLT_CR register 122 WriteBlock function 34...

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