Cypress PSoC CY8C24533 Technical Reference Manual

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PSoC® CY8C24533, CY8C23533, CY8C23433 TRM

PSoC

CY8C24533, CY8C23533, CY8C23433

Technical Reference Manual (TRM)

Document # 001-20559 Rev. *D

January 19, 2017

Cypress Semiconductor

198 Champion Court

San Jose, CA 95134-1709

Phone (USA): 800.858.1810

Phone (Intnl.): 408.943.2600

http://www.cypress.com

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Page 1 PSoC® CY8C24533, CY8C23533, CY8C23433 TRM ® PSoC CY8C24533, CY8C23533, CY8C23433 Technical Reference Manual (TRM) Document # 001-20559 Rev. *D January 19, 2017 Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl.): 408.943.2600 http://www.cypress.com...
Page 2 Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products.
Page 3: Table Of Contents
Contents Overview Section A: Overview Pin Information ......................... 25 Section B: PSoC Core CPU Core (M8C) ......................35 Supervisory ROM (SROM) ....................45 RAM Paging ........................55 Interrupt Controller ......................61 General Purpose IO (GPIO) .................... 69 Analog Output Drivers ......................
Page 4 Contents Overview Section G: Glossary Index 401 Document # 001-20559 Rev. *D...
Page 5 Contents Section A: Overview Document Organization ........................17 Top-Level Architecture ........................18 PSoC Core ..........................18 Digital System ..........................18 Analog System ..........................18 System Resources ........................18 PSoC Device Characteristics ......................20 PSoC Device Distinctions ........................20 Getting Started ...........................21 Support ............................21 Product Upgrades ........................21 Development Kits ........................21 Document History ..........................21 Documentation Conventions ......................22 Register Conventions...
Page 6 Contents Overview 2.6.4 Destination Direct ....................... 41 2.6.5 Destination Indexed ....................41 2.6.6 Destination Direct Source Immediate ................. 41 2.6.7 Destination Indexed Source Immediate ..............42 2.6.8 Destination Direct Source Direct................. 42 2.6.9 Source Indirect Post Increment .................. 43 2.6.10 Destination Indirect Post Increment ................
Page 7 Contents Overview 5.3.2.2 INT_MSK0 Register ..................66 5.3.2.3 INT_MSK1 Register ..................66 5.3.3 INT_VC Register ......................66 5.3.4 CPU_F Register ......................67 General Purpose IO (GPIO) ....................69 Architectural Description......................69 6.1.1 Digital IO ........................69 6.1.2 Global IO ........................70 6.1.3 Analog Input .......................70 6.1.4 GPIO Block Interrupts ....................71 Register Definitions ........................72 6.2.1 PRTxDR Registers .....................72...
Page 8 Contents Overview 12.1.2 Sleep Timer ......................95 12.2 Application Description....................... 96 12.3 Register Definitions ........................97 12.3.1 INT_MSK0 Register ....................97 12.3.2 RES_WDT Register ....................97 12.3.3 CPU_SCR1 Register ....................98 12.3.4 CPU_SCR0 Register ....................99 12.3.5 OSC_CR0 Register ....................100 12.3.6 ILO_TR Register ......................101 12.3.7...
Page 9 Contents Overview 13.2.25 ACBxxCR3 .......................137 13.2.26 ACBxxCR0 .......................138 13.2.27 ACBxxCR1 .......................140 13.2.28 ACBxxCR2 .......................142 13.2.29 ASDxxCR0 .......................143 13.2.30 ASDxxCR1 .......................144 13.2.31 ASDxxCR2 .......................145 13.2.32 ASDxxCR3 .......................146 13.2.33 ASCxxCR0 .......................147 13.2.34 ASCxxCR1 .......................148 13.2.35 ASCxxCR2 .......................149 13.2.36 ASCxxCR3 .......................150 13.2.37 RDIxRI ........................151 13.2.38 RDIxSYN ........................152 13.2.39 RDIxIS ........................153 13.2.40 RDIxLT0 ........................154...
Page 10 Contents Overview 13.3.7 DxBxxOU .........................195 13.3.8 CLK_CR0 .........................197 13.3.9 CLK_CR1 .........................198 13.3.10 ABF_CR0 ......................199 13.3.11 AMD_CR0 ........................200 13.3.12 AMD_CR1 ........................201 13.3.13 ALT_CR0 .........................202 13.3.14 SARADC_TRS ......................203 13.3.15 SARADC_TRCL ......................204 13.3.16 SARADC_TRCH ......................205 13.3.17 SARADC_CR2 ......................206 13.3.18 SARADC_LCR ......................207 13.3.19 GDI_O_IN ........................208 13.3.20 GDI_E_IN ........................209 13.3.21 GDI_O_OU ......................210 13.3.22 GDI_E_OU .......................211...
Page 11 Contents Overview 16.2.5.2 RDIxRO1 Register ..................240 16.3 Timing Diagram ........................240 17. Digital Blocks ........................241 17.1 Architectural Description......................241 17.1.1 Input Multiplexers .....................242 17.1.2 Input Clock Resynchronization .................242 17.1.2.1 Clock Resynchronization Summary ............243 17.1.3 Output De-Multiplexers ....................243 17.1.4 Block Chaining Signals ....................243 17.1.5 Input Data Synchronization ..................243 17.1.6...
Page 12 Contents Overview 17.3 Timing Diagrams ........................262 17.3.1 Timer Timing ......................262 17.3.2 Counter Timing ......................263 17.3.3 Dead Band Timing ....................264 17.3.3.1 Changing the PWM Duty Cycle ..............264 17.3.3.2 Kill Operation ..................265 17.3.4 CRCPRS Timing ......................266 17.3.5 SPI Mode Timing .....................266 17.3.6 SPIM Timing ......................267 17.3.7 SPIS Timing ......................270...
Page 13 Contents Overview 19.1.2 PMux Connections General Overview ..............299 19.1.3 RBotMux Connections General Overview..............300 19.1.4 AMux Connections General Overview ..............301 19.1.5 CMux Connections General Overview ..............302 19.1.6 BMux SC/SD Connections General Overview ............303 19.1.7 Analog Comparator Bus ...................303 19.2 Temperature Sensing Capability .....................303 20.
Page 14 Contents Overview Section F: System Resources Top-Level System Resources Architecture ..................335 Interpreting the System Resources Documentation .................335 System Resources Register Summary ....................336 25. Digital Clocks ........................339 25.1 Architectural Description ......................339 25.1.1 Internal Main Oscillator ....................339 25.1.2 Internal Low Speed Oscillator ..................339 25.1.3 32.768 kHz Crystal Oscillator..................341 25.1.4...
Page 15 Contents Overview 28.3 Register Definitions .........................362 28.3.1 I2C_CFG Register ....................362 28.3.2 I2C_SCR Register ....................364 28.3.3 I2C_DR Register ......................366 28.3.4 I2C_MSCR Register ....................366 28.4 Timing Diagrams ........................368 28.4.1 Clock Generation ......................368 28.4.2 Basic Input/Output Timing ..................368 28.4.3 Status Timing ......................369 28.4.4 Master Start Timing ....................370 28.4.5 Master Restart Timing ....................371...
Page 16 Contents Overview Document # 001-20559 Rev. *D...
Page 17: Section A: Overview
Ordering, Pinout, Packaging, or Electrical Specification information, refer to the PSoC data sheet. For the most current technical reference manual information, refer to the addendum. To obtain the newest product documentation, go to the Cypress web site at http://www.cypress.com/psoc. This section encompasses the following chapter: ■...
Page 18: Top-Level Architecture
Section A: Overview Top-Level Architecture The PSoC block diagram on the next page illustrates the Analog System top-level architecture of the PSoC device. Each major The Analog System is composed of analog columns in a grouping in the diagram is covered in this manual in its own block array, analog references, analog input muxing, and section: PSoC Core, Digital System, Analog System, and analog drivers.
Page 19 Section A: Overview PSoC Top-Level Block Diagram Analog Port 2 Port 1 Port 0 Port 3 Drivers PSoC CORE System Bus Global Digital Interconnect Global Analog Interconnect SRAM SROM Flash 8K 256 Bytes CPU Core (M8C) Sleep and Interrupt Watchdog Controller Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO)
Page 20: Psoc Device Characteristics
Section A: Overview PSoC Device Characteristics The PSoC digital system has 1 digital row and the analog The following table lists the resources available for system has 2 analog columns, as described in the following CY8C24633, CY8C24533, CY8C23533, CY8C23433-spe- table. cific PSoC device groups.
Page 21: Getting Started
Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.onfulfillment.com/cypressstore.
Page 22: Documentation Conventions
Section A: Overview Documentation Conventions There are only four distinguishing font types used in this Units of Measure manual, besides those found in the headings. The following table lists the units of measure used in this ■ The first is the use of italics when referencing a docu- manual.
Page 23: Acronyms
Section A: Overview Acronyms Acronyms (continued) Acronym Description The following table lists the acronyms that are used in this program counter high manual. program counter low power down Acronyms PSoC® memory arbiter Acronym Description power on reset ABUS analog output bus PPOR precision power on reset alternating current...
Page 24 Section A: Overview Document # 001-20559 Rev. *D...
Page 25: Pin Information
Pinouts The PSoC CY8C24533, CY8C23533, CY8C23433CY8C24633 are available in 28-pin SSOP and 32-pin QFN and 56-pin SSOP OCDpackages. Refer to the following information for details. Every port pin (labeled with a “P”), except for Vss and Vdd, and XRES in the following tables and illustrations, is capable of Digital IO.
Page 26: 28-Pin Part Pinout
Pin Information 1.1.1 28-Pin Part Pinout The 28-pin part is for the CY8C24533 CY8C24633 PSoC device. Table 1-1. 28-Pin Part Pinout (SSOP) CY8C24533 CY8C24633 PSoC Device Description AIO, P0[7] IO, P0[5] P0[6], AIO, AnColMux and ADC IP P0[7] Analog Col Mux IP and ADC IO, P0[3] P0[4], AIO, AnColMux and ADC IP...
Page 27 Pin Information The 28-pin part is for the CY8C23433 PSoC device. Table 1-2. 28-Pin Part Pinout (SSOP) CY8C23433 28-Pin PSoC Device Description AIO, P0[7] IO, P0[5] P0[6], AIO, AnColMux and ADC IP P0[7] Analog Column Mux IP and IO, P0[3] P0[4], AIO, AnColMux and ADC IP ADC IP AIO, P0[1]...
Page 28: 32-Pin Part Pinout
Pin Information 1.1.2 32-Pin Part Pinout The 32-pin part is for the CY8C23533 PSoC device. Table 1-3. 32-Pin Part Pinout (QFN) Type CY8C23533 32-Pin PSoC Device Description Name Digital Analog P2[7] GPIO P2[5] GPIO P2[3] Direct Switched Capacitor Block Input P2[1] Direct Switched Capacitor Block Input GPIO, P2[7] P 0[2 ], A , I...
Page 29: 56-Pin Part Pinout
Pin Information 1.1.3 56-Pin Part Pinout The 56-pin OCD (On-Chip Debug) part is for the CY8C24633 (CY8C24033) PSoC device. Note OCD parts are only used for in-circuit debugging. OCD parts are NOT available for production. Table 1-4. 56-Pin OCD Part Pinout (SSOP) CY8C24033 OCD PSoC Device Name Description...
Page 30 Pin Information Document # 001-20559 Rev. *D...
Page 31: Section B: Psoc Core
Section B: PSoC Core The PSoC Core section discusses the core components of the PSoC devices: CY8C24533, CY8C23533, CY8C23433CY8C24533, and the registers associated with those components. This section encompasses the following chap- ters: ■ CPU Core (M8C) on page 35 ■...
Page 32: Core Register Summary
Section B: PSoC Core Core Register Summary The table below lists all the PSoC registers for the CPU core in address order within their system resource configuration. The bits that are grayed out are reserved bits. If these bits are written, they should always be written with a value of ‘0’. For the core registers, the first ‘x’...
Page 33 Section B: PSoC Core Summary Table of the Core Registers (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,01h PRT0DM Drive Mode 1[7:0] RW : FF 1,02h PRT0IC0 Interrupt Control 0[7:0] RW : 00 1,03h...
Page 34 Section B: PSoC Core Summary Table of the Core Registers (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access INTERNAL LOW SPEED OSCILLATOR (ILO) REGISTER (page ILO_TR 1,E9h Bias Trim[1:0] Freq Trim[3:0] W : 00 EXTERNAL CRYSTAL OSCILLATOR (ECO) REGISTERS (page...
Page 35: Cpu Core (M8C)
For additional information concerning the M8C instruction set, refer to the PSoC Designer Assembly Language User Guide available at the Cypress web site (http://www.cypress.com/psoc). For a complete table of the CPU Core registers, refer to the “Summary Table of the Core Registers”...
Page 36: Instruction Set Summary
(in numeric and mnemonic order, respectively), and serves as a quick reference. If more information is needed, the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (refer to http://www.cypress.com/psoc). Table 2-1. Instruction Set Summary Sorted Numerically by Opcode...
Page 37 CPU Core (M8C) Table 2-2. Instruction Set Summary Sorted Alphabetically by Mnemonic Instruction Format Flags Instruction Format Flags Instruction Format Flags 09 4 ADC A, expr C, Z INC [expr] C, Z POP X 0A 6 ADC A, [expr] C, Z INC [X+expr] C, Z POP A...
Page 38: Instruction Formats
CPU Core (M8C) Instruction Formats 2.5.2 Two-Byte Instructions The majority of M8C instructions are two bytes in length. The M8C has a total of seven instruction formats which use While these instructions can be divided into categories iden- instruction lengths of one, two, and three bytes. All instruc- tical to the one-byte instructions, this would not provide a tion bytes are fetched from the program memory (Flash), useful distinction between the three two-byte instruction for-...
Page 39: Three-Byte Instructions
CPU Core (M8C) 2.5.3 Three-Byte Instructions The first instruction format, shown in the first row of Table 2-5, is used by the LJMP and LCALL instructions. The three-byte instruction formats are the second most These instructions change program execution uncondition- prevalent instruction formats.
Page 40: Source Direct
CPU Core (M8C) 2.6.2 Source Direct For these instructions, the source address is stored in operand 1 of the instruction. During instruction execution, the address is used to retrieve the source value from RAM or register address space. The result of these instructions is placed in either the M8C A or X register as indicated by the instruction’s opcode.
Page 41: Destination Direct
CPU Core (M8C) 2.6.4 Destination Direct For these instructions, the destination address is stored in the machine code of the instruction. The source for the operation is either the M8C A or X register as indicated by the instruction’s opcode. All instructions using the Destination Direct address- ing mode are two bytes in length.
Page 42: Destination Indexed Source Immediate
CPU Core (M8C) 2.6.7 Destination Indexed Source Immediate For these instructions, the destination offset from the X register is stored in operand 1 of the instruction. The source value is stored in operand 2 of the instruction. All instructions using the Destination Indexed Source Immediate addressing mode are three bytes in length.
Page 43: Source Indirect Post Increment
CPU Core (M8C) 2.6.9 Source Indirect Post Increment Only one instruction uses this addressing mode. The source address stored in operand 1 is actually the address of a pointer. During instruction execution, the pointer’s current value is read to determine the address in RAM where the source value is found.
Page 44: Register Definitions
CPU Core (M8C) Register Definitions The following register is associated with the CPU Core (M8C). The register description has an associated register table show- ing the bit structure. The bits that are grayed out in the table are reserved bits and are not detailed in the register description that follows.
Page 45: Supervisory Rom (Srom)
Supervisory ROM (SROM) This chapter discusses the Supervisory ROM (SROM) functions and its associated registers. For a complete table of the SROM registers, refer to the “Summary Table of the Core Registers” on page 32. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page Architectural Description...
Page 46: Additional Srom Feature
Supervisory ROM (SROM) The SWBootReset function is executed whenever the halt SROM is entered with an M8C accumulator value of 00h; 2. SSCOP: mov [KEY1], 3ah the SRAM parameter block is not used as an input to the mov X, SP function.
Page 47: Readblock Function
Supervisory ROM (SROM) 3.1.2.2 ReadBlock Function Table 3-4. SRAM Map Post SWBootReset (00h) The ReadBlock function is used to read 64 contiguous bytes Address from Flash: a block. The number of blocks in a device is the total number of bytes divided by 64. Refer to Table 3-5 0x00 0x00...
Page 48: Writeblock Function
Supervisory ROM (SROM) 3.1.2.3 WriteBlock Function 3.1.2.4 EraseBlock Function The WriteBlock function is used to store data in the Flash. The EraseBlock function is used to erase a block of 64 con- Data is moved 64 bytes at a time from SRAM to Flash using tiguous bytes in Flash.
Page 49: Protectblock Function
Supervisory ROM (SROM) 3.1.2.5 ProtectBlock Function 3.1.2.6 TableRead Function The PSoC devices offer Flash protection on a block-by- The TableRead function gives the user access to part-spe- block basis. Table 3-9 lists the protection modes available. cific data stored in the Flash during manufacturing. The In the table, ER and EW are used to indicate the ability to Flash for these tables is separate from the program Flash perform external reads and writes (that is, by an external...
Page 50: Checksum Function
Supervisory ROM (SROM) 3.1.2.8 Checksum Function 3.1.2.10 Calibrate1 Function The Checksum function calculates a 16-bit checksum over a While the Calibrate1 function is a completely separate func- user specifiable number of blocks, within a single Flash tion from Calibrate0, they perform the same function, which bank starting at block zero.
Page 51: Register Definitions
Supervisory ROM (SROM) Register Definitions The following registers are associated with the Supervisory ROM (SROM) and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.
Page 52: Fls_Pr1 Register
Supervisory ROM (SROM) 3.2.2 FLS_PR1 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,FAh FLS_PR Bank[1:0] RW : 00 The Flash Program Register 1 (FLS_PR1) is used to specify Bits 1 and 0: Bank[1:0].
Page 53: Clocking
Supervisory ROM (SROM) Clocking  Successful programming and erase operations, on the 2M T --------------- - CLOCK – Equation 3 Flash, require that the CLOCK and DELAY parameters be set correctly. To determine the proper value for the DELAY parameter only, the CPU speed must be considered. How- ever, three factors should be used to determine the proper Using the correct values for B, M, and T, in the equation value for CLOCK: operating temperature, CPU speed, and...
Page 54 Supervisory ROM (SROM) Document # 001-20559 Rev. *D...
Page 55: Ram Paging
RAM Paging This chapter explains the PSoC device’s use of RAM Paging and its associated registers. For a complete table of the RAM Paging registers, refer to the “Summary Table of the Core Registers” on page 32. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page Architectural Description...
Page 56: Stack Operations
RAM Paging 4.1.2 Stack Operations Therefore, all interrupt service routine code starts execution in SRAM Page 0. If it is necessary for the ISR to change to As mentioned previously, the paging architecture's reset another SRAM page, it can be accomplished by changing state puts the PSoC in a mode that is identical to that of a the values of the CPU_F[7:6] bits to enable the special 256 byte PSoC device.
Page 57: Index Memory
RAM Paging When the RETI instruction is executed, to end the ISR, the After reset, the PgMode bits are set to 00b. In this mode, previous value of the CPU_F register is restored, restoring index memory accesses are forced to SRAM Page 0, just as the previous page mode.
Page 58: Register Definitions
RAM Paging Register Definitions The following registers are associated with RAM Paging and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.
Page 59: Cpu_F Register
RAM Paging 4.2.2 CPU_F Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,F7h CPU_F PgMode[1:0] Carry Zero RL : 02 LEGEND L The AND F, expr; OR F, expr; and XOR F, expr flag instructions can be used to modify this register. x An ‘x’...
Page 60 RAM Paging Document # 001-20559 Rev. *D...
Page 61: Interrupt Controller
Interrupt Controller This chapter presents the Interrupt Controller and its associated registers. The interrupt controller provides a mechanism for a hardware resource in PSoC devices, to change program execution to a new address without regard to the current task being performed by the code being executed.
Page 62: Posted Versus Pending Interrupts
Interrupt Controller 5. The ISR executes. Note that interrupts are disabled 5.1.1 Posted versus Pending Interrupts since GIE = 0. In the ISR, interrupts can be re-enabled if An interrupt is posted when its interrupt conditions occur. desired, by setting GIE = 1 (take care to avoid stack This results in the flip-flop in Figure 5-1 clocking in a ‘1’.
Page 63: Application Description
Interrupt Controller Application Description The interrupt controller and its associated registers allow the user’s code to respond to an interrupt from almost every func- tional block in the PSoC devices. Interrupts for all the digital blocks and each of the analog columns are available, as well as interrupts for supply voltage, sleep, variable clocks, and a general GPIO (pin) interrupt.
Page 64: Register Definitions
Interrupt Controller Register Definitions The following registers are associated with the Interrupt Controller and are listed in address order. The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.
Page 65: Int_Clr1 Register
Interrupt Controller 5.3.1.2 INT_CLR1 Register 5.3.1.3 INT_CLR3 Register Bit 3: DCB03. This bit allows posted DCB03 interrupts to Bit 0: I2C. This bit allows posted I2C interrupts to be read, be read, cleared, or set for row 0 block 3. cleared, or set.
Page 66: Int_Msk0 Register
Interrupt Controller 5.3.2.2 INT_MSK0 Register For additional information, refer to the INT_MSK0 register on page 104. Bit 7: VC3. This bit allows posted VC3 interrupts to be 5.3.2.3 INT_MSK1 Register read, masked, or set. Bit 3: DCB03. This bit allows posted DCB03 interrupts to Bit 6: Sleep.
Page 67: Cpu_F Register
Interrupt Controller 5.3.4 CPU_F Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,F7h CPU_F PgMode[1:0] Carry Zero RL : 02 LEGEND L The AND F, expr; OR F, expr; and XOR F, expr flag instructions can be used to modify this register. x An “x”...
Page 68 Interrupt Controller Document # 001-20559 Rev. *D...
Page 69: General Purpose Io (Gpio)
General Purpose IO (GPIO) This chapter discusses the General Purpose IO (GPIO) and its associated registers, which is the circuit responsible for inter- facing to the IO pins of a PSoC device. The GPIO blocks provide the interface between the M8C core and the outside world. They offer a large number of configurations to support several types of input/output (IO) operations for both digital and ana- log systems.
Page 70: Global Io
General Purpose IO (GPIO) 6.1.2 Global IO 6.1.3 Analog Input The GPIO ports are also used to interconnect signals to and Analog signals can pass into the PSoC device core from from the digital PSoC blocks, as global inputs or outputs. PSoC device pins through the block’s AOUT pin.
Page 71: Gpio Block Interrupts
General Purpose IO (GPIO) 6.1.4 GPIO Block Interrupts pin transitions, if not already transitioned, appropriately high or low, to match the Interrupt mode configuration. Once this Each GPIO block can be individually configured for interrupt happens, the INTO line pulls low to assert the GPIO inter- capability.
Page 72: Register Definitions
General Purpose IO (GPIO) Register Definitions The following registers are associated with the General Purpose IO (GPIO) and are listed in address order. The register descriptions in this section have an associated register table showing the bit structure for that register. For a complete table of GPIO registers, refer to the “Summary Table of the Core Registers”...
Page 73: Prtxgs Registers
General Purpose IO (GPIO) 6.2.3 PRTxGS Registers Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,xxh PRTxGS Global Select[7:0] RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, “Summary Table of the Core Registers”...
Page 74: Prtxdmx Registers
General Purpose IO (GPIO) 6.2.4 PRTxDMx Registers Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,xxh PRTxDM Drive Mode 2[7:0] RW : FF 1,xxh PRTxDM Drive Mode 0[7:0] RW : 00 1,xxh PRTxDM Drive Mode 1[7:0]...
Page 75: Prtxicx Registers
General Purpose IO (GPIO) 6.2.5 PRTxICx Registers Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,xxh PRTxIC0 Interrupt Control 0[7:0] RW : 00 1,xxh PRTxIC1 Interrupt Control 1[7:0] RW : 00 LEGEND xx An “x”...
Page 76 General Purpose IO (GPIO) Document # 001-20559 Rev. *D...
Page 77: Analog Output Drivers
Analog Output Drivers This chapter presents the Analog Output Drivers and their associated register. The analog output drivers provide a means for driving analog signals off the PSoC device. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 47.
Page 78: Register Definitions
Analog Output Drivers Register Definitions The following register is associated with the Analog Output Drivers. The register description has an associated register table showing the bit structure of the register. The bits that are grayed out in the table below are reserved bits and are not detailed in the register description that follows.
Page 79: Internal Main Oscillator (Imo)
Internal Main Oscillator (IMO) This chapter presents the Internal Main Oscillator (IMO) and its associated registers. The IMO produces clock signals of 24 MHz and 48 MHz. For a complete table of the IMO registers, refer to the “Summary Table of the Core Registers” on page For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page Architectural Description...
Page 80: Register Definitions
Internal Main Oscillator (IMO) Register Definitions The following registers are associated with the Internal Main Oscillator (IMO). The register descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.
Page 81: Osc_Cr2 Register
Internal Main Oscillator (IMO) 8.3.2 OSC_CR2 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access OSC_CR 1,E2h PLLGAIN EXTCLKEN RSVD SYSCLKX2DIS RW : 00 The Oscillator Control Register 2 (OSC_CR2) is used to this clock source.
Page 82 Internal Main Oscillator (IMO) Document # 001-20559 Rev. *D...
Page 83: Internal Low Speed Oscillator (Ilo)
Internal Low Speed Oscillator (ILO) This chapter briefly explains the Internal Low Speed Oscillator (ILO) and its associated register. The Internal Low Speed Oscillator produces a 32 kHz clock. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page Architectural Description...
Page 84 Internal Low Speed Oscillator (ILO) Document # 001-20559 Rev. *D...
Page 85: External Crystal Oscillator (Eco)
External Crystal Oscillator (ECO) This chapter briefly explains the External Crystal Oscillator (ECO) and its associated registers. The 32.768 kHz external crys- tal oscillator circuit allows the user to replace the internal low speed oscillator with a more precise time source at low cost and low power.
Page 86: Eco External Components
External Crystal Oscillator (ECO) 5. The ECO becomes the selected source at the end of the An error of 1 pF in C1 and C2 gives about a 3 ppm error in one-second interval on the edge created by the sleep frequency.
Page 87: Register Definitions
External Crystal Oscillator (ECO) 10.3 Register Definitions The following registers are associated with the External Crystal Oscillator and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The bits that are grayed out in the tables below are reserved bits and are not detailed in the register descriptions.
Page 88: Osc_Cr0 Register
External Crystal Oscillator (ECO) 10.3.2 OSC_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,E0h OSC_CR 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed[2:0] RW : 00 The Oscillator Control Register 0 (OSC_CR0) is used to Bits 2 to 0: CPU Speed[2:0].
Page 89: Eco_Tr Register
External Crystal Oscillator (ECO) 10.3.3 ECO_TR Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,EBh ECO_TR PSSDC[1:0] W : 00 The External Crystal Oscillator Trim Register (ECO_TR) It is strongly recommended that the user not alter the sets the adjustment for the 32.768 kHz External Crystal register value.
Page 90 External Crystal Oscillator (ECO) Document # 001-20559 Rev. *D...
Page 91: Phase-Locked Loop (Pll)
Phase-Locked Loop (PLL) This chapter presents the Phase-Locked Loop (PLL) and its associated registers. For a complete table of the PLL registers, refer to the “Summary Table of the Core Registers” on page 32. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 11.1...
Page 92: Osc_Cr0 Register
Phase-Locked Loop (PLL) 11.2.1 OSC_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,E0h OSC_CR 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed[2:0] RW : 00 The Oscillator Control Register 0 (OSC_CR0) is used to The reset value for the CPU Speed bits is zero;...
Page 93: Osc_Cr2 Register
Phase-Locked Loop (PLL) 11.2.2 OSC_CR2 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access OSC_CR SYSCLKX2 1,E2h PLLGAIN EXTCLKEN RSVD RW : 00 The Oscillator Control Register 2 (OSC_CR2) is used to this clock source.
Page 94 Phase-Locked Loop (PLL) Document # 001-20559 Rev. *D...
Page 95: Sleep And Watchdog
Sleep and Watchdog This chapter discusses the Sleep and Watchdog operations and their associated registers. For a complete table of the Sleep and Watchdog registers, refer to the “Summary Table of the Core Registers” on page 32. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 12.1...
Page 96: Application Description
Sleep and Watchdog The reset state of the sleep timer is a count value of all Note 3 On wake up, the instruction immediately after the zeros. There are two ways to reset the sleep timer. Any sleep instruction is executed before the interrupt service hardware reset (that is, POR, XRES, or Watchdog Reset routine (if enabled).
Page 97: Register Definitions
Sleep and Watchdog 12.3 Register Definitions The following registers are associated with Sleep and Watchdog and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The bits that are grayed out in the tables below are reserved bits and are not detailed in the register descriptions.
Page 98: Cpu_Scr1 Register
Sleep and Watchdog 12.3.3 CPU_SCR1 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,FEh CPU_SC IRESS SLIMO ECO EXW * ECO EX * IRAMDIS # : 00 LEGEND An “x”...
Page 99: Cpu_Scr0 Register
Sleep and Watchdog 12.3.4 CPU_SCR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,FFh CPU_SC GIES WDRS PORS Sleep STOP # : XX LEGEND X The value for power on reset is unknown. An “x”...
Page 100: Osc_Cr0 Register
Sleep and Watchdog 12.3.5 OSC_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,E0h OSC_CR 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed[2:0] RW : 00 The Oscillator Control Register 0 (OSC_CR0) is used to Bits 2 to 0: CPU Speed[2:0].
Page 101: Ilo_Tr Register
Sleep and Watchdog 12.3.6 ILO_TR Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,E9h ILO_TR Bias Trim[1:0] Freq Trim[3:0] W : 00 The Internal Low Speed Oscillator Trim Register (ILO_TR) Table 12-3.
Page 102: Timing Diagrams
Sleep and Watchdog 12.4 Timing Diagrams 12.4.1 Sleep Sequence The Sleep bit, in the CPU_SCR0 register, is an input into the The system-wide PD signal controls three major circuit sleep logic circuit. This circuit is designed to sequence the blocks: the Flash memory module, the Internal Main Oscilla- device into and out of the hardware sleep state.
Page 103: Wake Up Sequence
Sleep and Watchdog 12.4.2 Wake Up Sequence Once asleep, the only event that can wake the system up is 2. At the following positive edge of the 32 kHz clock, the an interrupt. The Global Interrupt Enable of the CPU flag system-wide PD signal is negated.
Page 104: Bandgap Refresh
Sleep and Watchdog 12.4.3 Bandgap Refresh 12.4.4 Watchdog Timer During normal operation, the bandgap circuit provides a On device boot up, the Watchdog Timer (WDT) is initially voltage reference (VRef) to the system, for use in the analog disabled. The PORS bit in the System Control Register con- blocks, Flash, and low voltage detect (LVD) circuitry.
Page 105: Power Consumption
Sleep and Watchdog In practical application, it is important to know that the While the CLK32K can be turned off in Sleep mode, this watchdog timer interval can be anywhere between two and mode is not useful since it makes it impossible to restart three times the sleep timer interval.
Page 106 Sleep and Watchdog Document # 001-20559 Rev. *D...
Page 107: Section C: Register Reference
Section C: Register Reference The Register Reference section discusses the registers of the PSoC device. It lists all the registers in mapping tables, in address order. For easy reference, each register is linked to the page of a detailed description located in the next chapter. This section encompasses the following chapter: ■...
Page 108: Register Map Bank 0 Table: User Space
Section C: Register Reference Register Map Bank 0 Table: User Space PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR ASD11CR0 PRT1IE ASD11CR1 PRT1GS ASD11CR2 PRT1DM2 ASD11CR3 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 ASC21CR0 ASC21CR1 ASC21CR2 I2C_CFG ASC21CR3 I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3...
Page 109: Register Map Bank 1 Table: Configuration Space
Section C: Register Reference CPU_SCR0 Gray fields are reserved. # Access is bit specific. Register Map Bank 1 Table: Configuration Space PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 ASD11CR0 PRT1DM1 ASD11CR1 PRT1IC0 ASD11CR2 PRT1IC1 ASD11CR3 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 GDI_O_IN GDI_E_IN...
Page 110 Section C: Register Reference FLS_PR1 CPU_SCR1 CPU_SCR0 Gray fields are reserved. # Access is bit specific. Document # 001-20559 Rev. *D...
Page 111: Register Details
Register Details This chapter is a reference for all the PSoC device registers in address order, for Bank 0 and Bank 1. The most detailed descriptions of the PSoC registers are in the Register Definitions section of each chapter. The registers that are in both banks are incorporated with the Bank 0 registers, designated with an ‘x’, rather than a ‘0’...
Page 112: Register Conventions
Register Details Register Conventions The following table lists the register conventions that are specific to this chapter. Register Conventions Convention Example Description ‘x’ in a register name ACBxxCR1 Multiple instances/address ranges of the same register R : 00 Read register or bit(s) W : 00 Write register or bit(s) RL : 00...
Page 113: Bank 0 Registers
0,00h 13.2 Bank 0 Registers The following registers are all in bank 0 and are listed in address order. An ‘x’ before the comma in the register’s address indi- cates that the register can be accessed independent of the XIO bit in the CPU_F register. Registers that are in both Bank 0 and Bank 1 are listed in address order in Bank 0.
Page 114: Prtxie
0,01h 13.2.2 PRTxIE Port Interrupt Enable Register Individual Register Names and Addresses: 0,01h PRT0IE : 0,01h PRT1IE : 0,05h PRT2IE : 0,09h PRT3IE : 0,0Dh Access : POR RW : 00 Bit Name Interrupt Enables[7:0] This register is used to enable or disable the interrupt enable internal to the GPIO block. For additional information, refer to the “Register Definitions”...
Page 115: Prtxgs
0,02h 13.2.3 PRTxGS Port Global Select Register Individual Register Names and Addresses: 0,02h PRT0GS : 0,02h PRT1GS : 0,06h PRT2GS : 0,0Ah PRT3GS : 0,0Eh Access : POR RW : 00 Bit Name Global Select[7:0] This register is used to select the block for connection to global inputs or outputs. For additional information, refer to the “Register Definitions”...
Page 116: Prtxdm2
0,03h 13.2.4 PRTxDM2 Port Drive Mode Bit 2 Register Individual Register Names and Addresses: 0,03h PRT0DM2 : 0,03h PRT1DM2 : 0,07h PRT2DM2 : 0,0Bh PRT3DM2 : 0,0Fh Access : POR RW : FF Bit Name Drive Mode 2[7:0] This register is one of three registers whose combined value determines the unique Drive mode of each bit in a GPIO port. In this register, there are eight possible drive modes for each port pin.
Page 117: Dxbxxdr0
0,20h 13.2.5 DxBxxDR0 Digital Basic/Communication Type B Block Data Register 0 Individual Register Names and Addresses: 0,20h DBB00DR0 : 0,20h DBB01DR0 : 0,24h DCB02DR0 : 0,28h DCB03DR0 : 0,2Ch Access : POR R : 00 Bit Name Data[7:0] This register is the data register for a digital block. The use of this register is dependent on which function is selected for its block.
Page 118: Dxbxxdr1
0,21h 13.2.6 DxBxxDR1 Digital Basic/Communication Type B Block Data Register 1 Individual Register Names and Addresses: 0,21h DBB00DR1 : 0,21h DBB01DR1 : 0,25h DCB02DR1 : 0,29h DCB03DR1 : 0,2Dh Access : POR W : 00 Bit Name Data[7:0] This register is the data register for a digital block. The use of this register is dependent on which function is selected for its block.
Page 119: Dxbxxdr2
0,22h 13.2.7 DxBxxDR2 Digital Basic/Communication Type B Block Data Register 2 Individual Register Names and Addresses: 0,22h DBB00DR2 : 0,22h DBB01DR2 : 0,26h DCB02DR2 : 0,2Ah DCB03DR2 : 0,2Eh Access : POR RW* : 00 Bit Name Data[7:0] This register is the data register for a digital block. The use of this register is dependent on which function is selected for its block.
Page 120: Dxbxxcr0 (Timer Control)
0,23h 13.2.8 DxBxxCR0 (Timer Control) Digital Basic/Communication Type B Block Control Register 0 Individual Register Names and Addresses: 0,23h DBB00CR0 : 0,23h DBB01CR0 : 0,27h DCB02CR0 : 0,2Bh DCB03CR0 : 0,2Fh Access : POR RW : 0 RW : 0 RW : 0 Bit Name TC Pulse Width...
Page 121: Dxbxxcr0 (Counter Control)
0,23h 13.2.9 DxBxxCR0 (Counter Control) Digital Basic/Communication Type B Block Control Register 0 Individual Register Names and Addresses: 0,23h DBB00CR0: 0,23h DBB01CR0: 0,27h DCB02CR0: 0,2Bh DCB03CR0: 0,2Fh Access : POR RW : 0 Bit Name Enable This register is the Control register for a counter, if the DxBxxFN register is configured as a ‘001’.
Page 122: Dxbxxcr0 (Dead Band Control)
0,23h 13.2.10 DxBxxCR0 (Dead Band Control) Digital Basic/Communication Type B Block Control Register 0 Individual Register Names and Addresses: 0,23h DBB00CR0: 0,23h DBB01CR0: 0,27h DCB02CR0: 0,2Bh DCB03CR0: 0,2Fh Access : POR RW : 0 RW : 0 RW : 0 Bit Name Bit Bang Clock Bit Bang Mode...
Page 123: Dxbxxcr0 (Crcprs Control)
0,23h 13.2.11 DxBxxCR0 (CRCPRS Control) Digital Basic/Communication Type B Block Control Register 0 Individual Register Names and Addresses: 0,23h DBB00CR0: 0,23h DBB01CR0: 0,27h DCB02CR0: 0,2Bh DCB03CR0: 0,2Fh Access : POR RW : 0 RW : 0 Bit Name Pass Mode Enable This register is the Control register for a CRCPRS, if the DxBxxFN...
Page 124: Dcbxxcr0 (Spim Control)
0,2Bh 13.2.12 DCBxxCR0 (SPIM Control) Digital Communication Type B Block Control Register 0 Individual Register Names and Addresses: 0,2Bh DCB02CR0: 0,2Bh DCB03CR0: 0,2Fh Access : POR RW : 0 R : 0 R : 0 R : 1 R : 0 RW : 0 RW : 0 RW : 0...
Page 125: Dcbxxcr0 (Spis Control)
0,2Bh 13.2.13 DCBxxCR0 (SPIS Control) Digital Communication Type B Block Control Register 0 Individual Register Names and Addresses: 0,2Bh DCB02CR0: 0,2Bh DCB03CR0: 0,2Fh Access : POR RW : 0 R : 0 R : 0 R : 1 R : 0 RW : 0 RW : 0 RW : 0...
Page 126: Dcbxxcr0 (Uart Transmitter Control)
0,2Bh 13.2.14 DCBxxCR0 (UART Transmitter Control) Digital Communication Type B Block Control Register 0 Individual Register Names and Addresses: 0,2Bh DCB02CR0: 0,2Bh DCB03CR0: 0,2Fh Access : POR R : 0 R : 1 RW : 0 RW : 0 RW : 0 Bit Name TX Complete TX Reg Empty...
Page 127: Dcbxxcr0 (Uart Receiver Control)
0,2Bh 13.2.15 DCBxxCR0 (UART Receiver Control) Digital Communication Type B Block Control Register 0 Individual Register Names and Addresses: 0,2Bh DCB02CR0: 0,2Bh DCB03CR0: 0,2Fh Access : POR R : 0 R : 0 R : 0 R : 0 R : 0 RW : 0 RW : 0 RW : 0...
Page 128: Amx_In
0,60h 13.2.16 AMX_IN Analog Input Select Register Individual Register Names and Addresses: 0,60h AMX_IN: 0,60h 2 COLUMN Access : POR RW : 0 RW : 0 Bit Name ACI1[1:0] ACI0[1:0] This register controls the analog muxes that feed signals in from port pins into the analog column. Use the register tables above, in addition to the detailed register bit descriptions below, to determine which bits are reserved for some smaller PSoC devices.
Page 129: Arf_Cr
0,63h 13.2.17 ARF_CR Analog Reference Control Register Individual Register Names and Addresses: 0,63h ARF_CR: 0,63h Access : POR RW : 0 RW : 0 RW : 0 Bit Name REF[2:0] PWR[2:0] This register is used to configure various features of the configurable analog references. In the table above, note that the reserved bit is a gray table cell and is not described in the bit description section below.
Page 130: Cmp_Cr0
0,64h 13.2.18 CMP_CR0 Analog Comparator Bus 0 Register Individual Register Names and Addresses: 0,64h CMP_CR0: 0,64h Access : POR R : 0 RW : 0 Bit Name COMP[1:0] AINT[1:0] This register is used to poll the analog column comparator bits and select column interrupts. Use the register tables above, in addition to the detailed register bit descriptions below, to determine which bits are reserved for some smaller PSoC devices.
Page 131: Asy_Cr
0,65h 13.2.19 ASY_CR Analog Synchronization Control Register Individual Register Names and Addresses: 0,65h ASY_CR: 0,65h Access : POR W : 0 RW : 0 RW : 0 RW : 0 Bit Name SARCNT[2:0] SARSIGN SARCOL[1:0] SYNCEN This register is used to control SAR operation, except for the SYNCEN bit, which is associated with analog register write stall- ing.
Page 132: Cmp_Cr1
0,66h 13.2.20 CMP_CR1 Analog Comparator Bus 1 Register Individual Register Names and Addresses: 0,66h CMP_CR1: 0,66h Access : POR RW : 0 RW : 0 Bit Name CLDIS[1] CLDIS[0] This register is used to override the analog column comparator synchronization. By default, the analog comparator bus is synchronized by the column clock and driven to the digital comparator bus for use in the digital array and the interrupt controller.
Page 133: Saradc_Dl
0,67h 13.2.21 SARADC_DL SAR8 ADC Conversion Low Byte Results Register Individual Register Names and Addresses: 0,67h SARADC_DL : 0,67h Access : POR RW : 00 Bit Name Data[7:0] This register is the raw conversion data register of the SAR8 ADC module. For additional information, refer to the “Register Definitions”...
Page 134: Saradc_Cr0
0,69h 13.2.22 SARADC_CR0 SAR8 ADC Control Register 0 Individual Register Names and Addresses: 0,69h SARADC_CR0 : 0,69h Access : POR RW : 00 RW : 1 RC : 0 RC : 0 Bit Name ADC Channel[3:0] Data Ready Start/Busy ADCEN This register is used to control normal ADC operation and show ADC status.
Page 135: Saradc_Cr1
0,6Ah 13.2.23 SARADC_CR1 SAR8 ADC Control Register 1 Individual Register Names and Addresses: 0,6Ah SARADC_CR1 : 0,6Ah Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name PWRSELADC PWRSELR2R Align Source[1:0] Align Enable This register is used to control normal ADC operation and show ADC status.
Page 136: Tmp_Drx
x,6Ch 13.2.24 TMP_DRx Temporary Data Register Individual Register Names and Addresses: x,6Ch TMP_DR0 : x,6Ch TMP_DR1 : x,6Dh TMP_DR2 : x,6Eh TMP_DR3 : x,6Fh Access : POR RW : 00 Bit Name Data[7:0] This register is used to enhance the performance in multiple SRAM page PSoC devices. All bits in this register are reserved for PSoC devices with 256 bytes of SRAM.
Page 137: Acbxxcr3
x,70h 13.2.25 ACBxxCR3 Analog Continuous Time Type B Block Control Register 3 Individual Register Names and Addresses: x,70h ACB00CR3 : x,70h ACB01CR3 : x,74h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name LPCMPEN CMOUT INSAMP...
Page 138: Acbxxcr0
x,71h 13.2.26 ACBxxCR0 Analog Continuous Time Type B Block Control Register 0 Individual Register Names and Addresses: x,71h ACB00CR0 : x,71h ACB01CR0 : x,75h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name RTapMux[3:0] Gain RTopMux...
Page 139 x,71h 13.2.26 ACBxxCR0 (continued) RBotMux[1:0] Encoding for feedback resistor select. Bits [1:0] are overridden if bit 1 of the ACBxxCR3 register is set. In that case, the bottom of the resistor string is connected across columns. Note that available mux inputs vary by individual PSoC block. In the table below, only columns ACB00 and ACB01 are used by the 2 column analog PSoC blocks.
Page 140: Acbxxcr1
x,72h 13.2.27 ACBxxCR1 Analog Continuous Time Type B Block Control Register 1 Individual Register Names and Addresses: x,72h ACB00CR1 : x,72h ACB01CR1 : x,76h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name AnalogBus CompBus NMux[2:0]...
Page 141 x,72h 13.2.27 ACBxxCR1 (continued) PMux[2:0] Encoding for positive input select. Note that available mux inputs vary by individual PSoC block. The following table is used by the 2 column analog PSoC blocks. ACB00 ACB01 000b RefLo 001b Port Inputs Port Inputs 010b ACB01 ACB00...
Page 142: Acbxxcr2
x,73h 13.2.28 ACBxxCR2 Analog Continuous Time Type B Block Control Register 2 Individual Register Names and Addresses: x,73h ACB00CR2 : x,73h ACB01CR2 : x,77h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name CPhase...
Page 143: Asdxxcr0
x,84h 13.2.29 ASDxxCR0 Analog Switch Cap Type D Block Control Register 0 Individual Register Names and Addresses: x,84h ASD11CR0 : x,84h Access : POR RW : 0 RW : 0 RW : 0 RW : 00 Bit Name FCap ClockPhase ASign ACap[4:0] This register is one of four registers used to configure a type D switched capacitor PSoC block.
Page 144: Asdxxcr1
x,85h 13.2.30 ASDxxCR1 Analog Switch Cap Type D Block Control Register 1 Individual Register Names and Addresses: x,85h ASD11CR1 : x,85h Access : POR RW : 0 RW : 00 Bit Name AMux[2:0] BCap[4:0] This register is one of four registers used to configure a type D switched capacitor PSoC block. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m=row index, n=column index;...
Page 145: Asdxxcr2
x,86h 13.2.31 ASDxxCR2 Analog Switch Cap Type D Block Control Register 2 Individual Register Names and Addresses: x,86h ASD11CR2 : x,86h Access : POR RW : 0 RW : 0 RW : 0 RW : 00 Bit Name AnalogBus CompBus AutoZero CCap[4:0] This register is one of four registers used to configure a type D switched capacitor PSoC block.
Page 146: Asdxxcr3
x,87h 13.2.32 ASDxxCR3 Analog Switch Cap Type D Block Control Register 3 Individual Register Names and Addresses: x,87h ASD11CR3 : x,87h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name ARefMux[1:0] FSW1...
Page 147: Ascxxcr0
x,94h 13.2.33 ASCxxCR0 Analog Switch Cap Type C Block Control Register 0 Individual Register Names and Addresses: x,94h ASC21CR0 : x,94h Access : POR RW : 0 RW : 0 RW : 0 RW : 00 Bit Name FCap ClockPhase ASign ACap[4:0] This register is one of four registers used to configure a type C switched capacitor PSoC block.
Page 148: Ascxxcr1
x,95h 13.2.34 ASCxxCR1 Analog Switch Cap Type C Block Control Register 1 Individual Register Names and Addresses: x,95h ASC21CR1 : x,95h Access : POR RW : 0 RW : 00 Bit Name ACMux[2:0] BCap[4:0] This register is one of four registers used to configure a type C switched capacitor PSoC block. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m=row index, n=column index;...
Page 149: Ascxxcr2
x,96h 13.2.35 ASCxxCR2 Analog Switch Cap Type C Block Control Register 2 Individual Register Names and Addresses: x,96h ASC21CR2 : x,96h Access : POR RW : 0 RW : 0 RW : 0 RW : 00 Bit Name AnalogBus CompBus AutoZero CCap[4:0] This register is one of four registers used to configure a type C switched capacitor PSoC block.
Page 150: Ascxxcr3
x,97h 13.2.36 ASCxxCR3 Analog Switch Cap Type C Block Control Register 3 Individual Register Names and Addresses: x,97h ASC21CR3 : x,97h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name ARefMux[1:0] FSW1 FSW0...
Page 151: Rdixri
x,B0h 13.2.37 RDIxRI Row Digital Interconnect Row Input Register Individual Register Names and Addresses: x,B0h RDI0RI : x,B0h Access : POR RW : 0 Bit Name RI0[1:0] This register is used to control the input mux that determines which global inputs drive the row inputs. The ‘x’...
Page 152: Rdixsyn
x,B1h 13.2.38 RDIxSYN Row Digital Interconnect Synchronization Register Individual Register Names and Addresses: x,B1h RDI0SYN : x,B1h Access : POR RW : 0 Bit Name RI0SYN This register is used to control the input synchronization. The ‘x’ in the digital register’s name represents the digital row index. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Page 153: Rdixis
x,B2h 13.2.39 RDIxIS Row Digital Interconnect Input Select Register Individual Register Names and Addresses: x,B2h RDI0IS : x,B2h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name BCSEL[1:0] This register is used to configure the inputs to the digital row LUTS and select a broadcast driver from another row if present. The ‘x’...
Page 154: Rdixlt0
x,B3h 13.2.40 RDIxLT0 Row Digital Interconnect Logic Table Register 0 Individual Register Names and Addresses: x,B3h RDI0LT0 : x,B3h Access : POR RW : 0 RW : 0 Bit Name LUT1[3:0] LUT0[3:0] This register is used to select the logic function of the digital row LUTS. The ‘x’...
Page 155: Rdixlt1
x,B4h 13.2.41 RDIxLT1 Row Digital Interconnect Logic Table Register 1 Individual Register Names and Addresses: x,B4h RDI0LT1 : x,B4h Access : POR RW : 0 RW : 0 Bit Name LUT3[3:0] LUT2[3:0] This register is used to select the logic function of the digital row LUTS. The ‘x’...
Page 156: Rdixro0
x,B5h 13.2.42 RDIxRO0 Row Digital Interconnect Row Output Register 0 Individual Register Names and Addresses: x,B5h RDI0RO0 : x,B5h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name...
Page 157: Rdixro1
x,B6h 13.2.43 RDIxRO1 Row Digital Interconnect Row Output Register 1 Individual Register Names and Addresses: x,B6h RDI0RO1 : x,B6h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name...
Page 158: I2C_Cfg
0,D6h 13.2.44 I2C_CFG C Configuration Register Individual Register Names and Addresses: 0,D6h I2C_CFG: 0,D6h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name PSelect Bus Error IE Stop IE Clock Rate[1:0] Enable Master...
Page 159: I2C_Scr
0,D7h 13.2.45 I2C_SCR C Status and Control Register Individual Register Names and Addresses: 0,D7h I2C_SCR: 0,D7h Access : POR RC : 0 RC : 0 RC : 0 RW : 0 RC : 0 RW : 0 RC : 0 RC : 0 Bit Name Bus Error...
Page 160 0,D7h I2C_SCR 13.2.45 (continued) Byte Complete Transmit/Receive Mode: No completed transmit/receive since last cleared by firmware. Any Start detect or a write to the Start or Restart generate bits, when operating in Master mode, also clears the bit. Transmit Mode: Eight bits of data have been transmitted and an ACK or NACK has been received.
Page 161: I2C_Dr
0,D8h 13.2.46 I2C_DR C Data Register Individual Register Names and Addresses: 0,D8h I2C_DR: 0,D8h Access : POR RW : 00 Bit Name Data[7:0] This register provides read/write access to the Shift register. This register is read only for received data and write only for transmitted data. For additional information, refer to the “Register Definitions”...
Page 162: I2C_Mscr
0,D9h 13.2.47 I2C_MSCR C Master Status and Control Register Individual Register Names and Addresses: 0,D9h I2C_MSCR: 0,D9h Access : POR R : 0 R : 0 RW : 0 RW : 0 Bit Name Bus Busy Master Mode Restart Gen Start Gen This register implements I2C framing controls and provides Bus Busy status.
Page 163: Int_Clr0
0,DAh 13.2.48 INT_CLR0 Interrupt Clear Register 0 Individual Register Names and Addresses: 0,DAh INT_CLR0: 0,DAh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name Sleep GPIO SAR8 ADC...
Page 164 0,DAh 13.2.48 INT_CLR0 (continued) Analog 1 Read 0 No posted interrupt for analog columns. Read 1 Posted interrupt present for analog columns Write 0 AND ENSWINT = 0 Clear posted interrupt if it exists. Write 1 AND ENSWINT = 0 No effect. Write 0 AND ENSWINT = 1 No effect.
Page 165: Int_Clr1
0,DBh 13.2.49 INT_CLR1 Interrupt Clear Register 1 Individual Register Names and Addresses: 0,DBh INT_CLR1: 0,DBh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name DCB03 DCB02 DBB01 DBB00 This register is used to clear posted interrupts for digital blocks or generate interrupts. When bits in this register are read, a ‘1’ is returned for every bit position that has a corresponding posted interrupt.
Page 166: Int_Clr3
0,DDh 13.2.50 INT_CLR3 Interrupt Clear Register 3 Individual Register Names and Addresses: 0,DDh INT_CLR3: 0,DDh Access : POR RW : 0 Bit Name This register is used to enable the I2C interrupt sources’ ability to clear posted interrupts. When bits in this register are read, a ‘1’ is returned for every bit position that has a corresponding posted interrupt. When bits in this register are written with a ‘0’...
Page 167: Int_Msk3
0,DEh 13.2.51 INT_MSK3 Interrupt Mask Register 3 Individual Register Names and Addresses: 0,DEh INT_MSK3: 0,DEh Access : POR RW : 0 RW : 0 Bit Name ENSWINT This register is used to enable the I2C’s ability to create pending interrupts and enable software interrupts. When an interrupt is masked off, the mask bit is ‘0’.
Page 168: Int_Msk0
0,E0h 13.2.52 INT_MSK0 Interrupt Mask Register 0 Individual Register Names and Addresses: 0,E0h INT_MSK0: 0,E0h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name Sleep GPIO SAR8 ADC...
Page 169: Int_Msk1
0,E1h 13.2.53 INT_MSK1 Interrupt Mask Register 1 Individual Register Names and Addresses: 0,E1h INT_MSK1: 0,E1h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name DCB03 DCB02 DBB01 DBB00 This register is used to enable the individual sources’ ability to create pending interrupts for digital blocks. When an interrupt is masked off, the mask bit is ‘0’.
Page 170: Int_Vc
0,E2h 13.2.54 INT_VC Interrupt Vector Clear Register Individual Register Names and Addresses: 0,E2h INT_VC: 0,E2h Access : POR RC : 00 Bit Name Pending Interrupt[7:0] This register returns the next pending interrupt and clears all pending interrupts when written. For additional information, refer to the “Register Definitions”...
Page 171: Res_Wdt
0,E3h 13.2.55 RES_WDT Reset Watchdog Timer Register Individual Register Names and Addresses: 0,E3h RES_WDT: 0,E3h Access : POR W : 00 Bit Name WDSL_Clear[7:0] This register is used to clear the watchdog timer and clear both the watchdog timer and the sleep timer. For additional information, refer to the “Register Definitions”...
Page 172: Dec_Dh
0,E4h 13.2.56 DEC_DH Decimator Data High Register Individual Register Names and Addresses: 0,E4h DEC_DH: 0,E4h Access : POR RC : XX Bit Name Data High Byte[7:0] This register is a dual purpose register and is used to read the high byte of the decimator’s output or clear the decimator. When a hardware reset occurs, the internal state of the decimator is reset, but the output data registers (DEC_DH and DEC_DL) are not.
Page 173: Dec_Dl
0,E5h 13.2.57 DEC_DL Decimator Data Low Register Individual Register Names and Addresses: 0,E5h DEC_DL: 0,E5h Access : POR RC : XX Bit Name Data Low Byte[7:0] This register is a dual purpose register and is used to read the low byte of the decimator’s output or clear the decimator. When a hardware reset occurs, the internal state of the decimator is reset, but the output data registers (DEC_DH and DEC_DL) are not.
Page 174: Dec_Cr0
0,E6h 13.2.58 DEC_CR0 Decimator Control Register 0 Individual Register Names and Addresses: 0,E6h DEC_CR0: 0,E6h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name IGEN[1:0] ICLKS0 DCOL[1:0] DCLKS0 This register contains control bits to access hardware support for ADC operation. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section.
Page 175: Dec_Cr1
0,E7h 13.2.59 DEC_CR1 Decimator Control Register 1 Individual Register Names and Addresses: 0,E7h DEC_CR1: 0,E7h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name ECNT IDEC...
Page 176: Mulx_X
0,E8h 13.2.60 MULx_X Multiply Input X Register Individual Register Names and Addresses: MUL0_X : 0,E8h Access : POR W : XX Bit Name Data[7:0] This register is one of two multiplicand registers for the signed 8-bit multiplier in the PSoC MAC. For additional information, refer to the “Register Definitions”...
Page 177: Mulx_Y
0,E9h 13.2.61 MULx_Y Multiply Input Y Register Individual Register Names and Addresses: MUL0_Y : 0,E9h Access : POR W : XX Bit Name Data[7:0] This register is one of two multiplicand registers for the signed 8-bit multiplier in the PSoC MAC. For additional information, refer to the “Register Definitions”...
Page 178: Mulx_Dh
0,EAh 13.2.62 MULx_DH Multiply Result High Byte Register Individual Register Names and Addresses: MUL0_DH : 0,EAh Access : POR R : XX Bit Name Data[7:0] This register holds the most significant byte of the 16-bit product. For additional information, refer to the “Register Definitions”...
Page 179: Mulx_Dl
0,EBh 13.2.63 MULx_DL Multiply Result Low Byte Register Individual Register Names and Addresses: MUL0_DL : 0,EBh Access : POR R : XX Bit Name Data[7:0] This register holds the least significant byte of the 16-bit product. For additional information, refer to the “Register Definitions”...
Page 180: Macx_X/Accx_Dr1
0,ECh 13.2.64 MACx_X/ACCx_DR1 Accumulator Data Register 1 Individual Register Names and Addresses: MAC0_X/ACC0_DR1 : 0,ECh Access : POR RW : 00 Bit Name Data[7:0] This is the multiply accumulate X register and the second byte of the accumulated value. For additional information, refer to the “Register Definitions”...
Page 181: Macx_Y/Accx_Dr0
0,EDh 13.2.65 MACx_Y/ACCx_DR0 Accumulator Data Register 0 Individual Register Names and Addresses: MAC0_Y/ACC0_DR0 : 0,EDh Access : POR RW : 00 Bit Name Data[7:0] This is the multiply accumulate Y register and the first byte of the accumulated value. For additional information, refer to the “Register Definitions”...
Page 182: Macx_Cl0/Accx_Dr3
0,EEh 13.2.66 MACx_CL0/ACCx_DR3 Accumulator Data Register 3 Individual Register Names and Addresses: MAC0_CL0/ACC0_DR3 : 0,EEh Access : POR RW : 00 Bit Name Data[7:0] This is an accumulator clear register and the fourth byte of the accumulated value. For additional information, refer to the “Register Definitions”...
Page 183: Macx_Cl1/Accx_Dr2
0,EFh 13.2.67 MACx_CL1/ACCx_DR2 Accumulator Data Register 2 Individual Register Names and Addresses: MAC0_CL1/ACC0_DR2 : 0,EFh Access : POR RW : 00 Bit Name Data[7:0] This is an accumulator clear register and the third byte of the accumulated value. For additional information, refer to the “Register Definitions”...
Page 184: Cpu_F
x,F7h 13.2.68 CPU_F M8C Flag Register Individual Register Names and Addresses: x,F7h CPU_F: x,F7h Access : POR RL : 0 RL : 0 RL : 0 RL : 0 RL : 0 Bit Name PgMode[1:0] Carry Zero This register provides read access to the M8C flags. The AND f, expr;...
Page 185: Cpu_Scr1
x,FEh 13.2.69 CPU_SCR1 System Status and Control Register 1 Individual Register Names and Addresses: x,FEh CPU_SCR1: x,FEh Access : POR R : 0 R : 0 RW : 0 RW : 0 Bit Name IRESS ECO EXW ECO EX IRAMDIS This register is used to convey the status and control of events related to internal resets and watchdog reset.
Page 186: Cpu_Scr0
x,FFh 13.2.70 CPU_SCR0 System Status and Control Register 0 Individual Register Names and Addresses: x,FFh CPU_SCR0: x,FFh Access : POR R : 0 RC : 0 RC : 1 RW : 0 RW : 0 Bit Name GIES WDRS PORS Sleep STOP This register is used to convey the status and control of events for various functions of a PSoC device.
Page 187: Bank 1 Registers
1,00h 13.3 Bank 1 Registers The following registers are all in bank 1 and are listed in address order. Registers that are in both Bank 0 and Bank 1 are listed in address order in the section titled “Bank 0 Registers” on page 13.3.1 PRTxDM0 Port Drive Mode Bit Register 0...
Page 188: Prtxdm1
1,01h 13.3.2 PRTxDM1 Port Drive Mode Bit Register 1 Individual Register Names and Addresses: 1,01h PRT0DM1 : 1,01h PRT1DM1 : 1,05h PRT2DM1 : 1,09h PRT3DM1 : 1,0Dh Access : POR RW : FF Bit Name Drive Mode 1[7:0] This register is one of three registers whose combined value determines the unique Drive mode of each bit in a GPIO port. In register PRTxDM1 there are eight possible drive modes for each port pin.
Page 189: Prtxic0
1,02h 13.3.3 PRTxIC0 Port Interrupt Control Register 0 Individual Register Names and Addresses: 1,02h PRT0IC0 : 1,02h PRT1IC0 : 1,06h PRT2IC0 : 1,0Ah PRT3IC0 : 1,0Eh Access : POR RW : 00 Bit Name Interrupt Control 0[7:0] This register is one of two registers whose combined value determine the unique Interrupt mode of each bit in a GPIO port. In register PRTxIC0 there are four possible interrupt modes for each port pin.
Page 190: Prtxic1
1,03h 13.3.4 PRTxIC1 Port Interrupt Control Register 1 Individual Register Names and Addresses: 1,03h PRT0IC1 : 1,03h PRT1IC1 : 1,07h PRT2IC1 : 1,0Bh PRT3IC1 : 1,0Fh Access : POR RW : 00 Bit Name Interrupt Control 1[7:0] This register is one of two registers whose combined value determine the unique Interrupt mode of each bit in a GPIO port. In register PRTxIC1 there are four possible interrupt modes for each port pin.
Page 191: Dxbxxfn
1,20h 13.3.5 DxBxxFN Digital Basic/Communications Type B Block Function Register Individual Register Names and Addresses: 1,20h DBB00FN : 1,20h DBB01FN : 1,24h DCB02FN : 1,28h DCB03FN : 1,2Ch Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name...
Page 192 1,20h 13.3.5 DxBxxFN (continued) Dead Band: Mode[1:0] are encoded as the Kill Type. (cont.) Synchronous Restart KILL mode Disable KILL mode Asynchronous KILL mode Reserved UART: Mode[0] signifies the Direction. Receiver Transmitter Mode[1] signifies the Interrupt Type. Interrupt on TX Reg Empty Interrupt on TX Complete SPI: Mode[0] signifies the Type.
Page 193: Dxbxxin
1,21h 13.3.6 DxBxxIN Digital Basic/Communications Type B Block Input Register Individual Register Names and Addresses: 1,21h DBB00IN : 1,21h DBB01IN : 1,25h DCB02IN : 1,29h DCB03IN : 1,2Dh Access : POR RW : 0 RW : 0 Bit Name Data Input[3:0] Clock Input[3:0] These registers are used to select the data and clock inputs.
Page 194 1,21h 13.3.6 DxBxxIN (continued) Clock Input[3:0] Clock disabled (low) Row broadcast net Previous block primary output (low for DBB00) SYSCLKX2 CLK32K Row output 0 Row output 1 Row output 2 Row output 3 Row input 0 Row input 1 Row input 2 Row input 3 Document # 001-20559 Rev.
Page 195: Dxbxxou
1,22h 13.3.7 DxBxxOU Digital Basic/Communications Type B Block Output Register Individual Register Names and Addresses: 1,22h DBB00OU : 1,22h DBB01OU : 1,26h DCB02OU : 1,2Ah DCB03OU : 1,2Eh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name...
Page 196 1,22h 13.3.7 DxBxxOU (continued) AUX IO Select[1:0] SPI Slave Source for SS_ Input if AUXEN =1 (cont.) Force SS_ Active Reserved Reserved Reserved OUTEN Enable Primary Function Output Driver Disabled Enabled Output Select[1:0] Row Output Select for Primary Function Output Row Output 0 Row Output 1 Row Output 2...
Page 197: Clk_Cr0
1,60h 13.3.8 CLK_CR0 Analog Column Clock Control Register 0 Individual Register Names and Addresses: 1,60h CLK_CR0: 1,60h Access : POR RW : 0 RW : 0 Bit Name AColumn1[1:0] AColumn0[1:0] This register is used to select the clock source for an individual analog column. Each column has two bits that select the column clock input source.
Page 198: Clk_Cr1
1,61h 13.3.9 CLK_CR1 Analog Clock Source Control Register 1 Individual Register Names and Addresses: 1,61h CLK_CR1: 1,61h Access : POR RW : 0 RW : 0 RW : 0 Bit Name SHDIS ACLK1[2:0] ACLK0[2:0] This register is used to select the clock source for an individual analog column. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Page 199: Abf_Cr0
1,62h 13.3.10 ABF_CR0 Analog Output Buffer Control Register 0 Individual Register Names and Addresses: 1,62h ABF_CR0: 1,62h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name ACol1Mux ABUF1EN ABUF0EN Bypass This register controls analog input muxes from Port 0.
Page 200: Amd_Cr0
1,63h 13.3.11 AMD_CR0 Analog Modulation Control Register 0 Individual Register Names and Addresses: 1,63h AMD_CR0: 1,63h Access : POR RW : 0 Bit Name AMOD0[2:0] This register is used to select the modulator bits used with each column. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. Reserved bits should always be written with a value of ‘0’.
Page 201: Amd_Cr1
1,66h 13.3.12 AMD_CR1 Analog Modulation Control Register 1 Individual Register Names and Addresses: 1,66h AMD_CR1: 1,66h Access : POR RW : 0 Bit Name AMOD1[2:0] This register is used to select the modulator bits used with each column. Note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits should always be written with a value of ‘0’.
Page 202: Alt_Cr0
1,67h 13.3.13 ALT_CR0 Analog LUT Control Register 0 Individual Register Names and Addresses: 1,67h ALT_CR0: 1,67h Access : POR RW : 0 RW : 0 Bit Name LUT1[3:0] LUT0[3:0] This register is used to select the logic function. For additional information, refer to the “Register Definitions”...
Page 203: Saradc_Trs
1,A8h 13.3.14 SARADC_TRS SAR8 ADC Auto Align/Trigger Source Register Individual Register Names and Addresses: 1,A8h SARADC_TRS : 1,A8h Access : POR RW : 00 RW : 00 RW : 00 RW : 00 Bit Name DCB03_HL[1:0] DCB02_HL[1:0] DBB01_HL[1:0] DBB00_HL[1:0] This register is where the ADC auto align/trigger source is set. Select any digital blocks in digital ROW0 as the align/trigger source for ADC conversion.
Page 204: Saradc_Trcl
1,A9h 13.3.15 SARADC_TRCL SAR8 ADC Low Channel Comparator Data Register Individual Register Names and Addresses: 1,A9h SARADC_TRCL : 1,A9h Access : POR RW : 00 Bit Name CMP_L[7:0] This register is the ADC auto align/trigger comparator data register. A trigger occurs when the low channel trigger is enabled, a selected digital block is enabled, and the selected digital block’s DR0 data is equal to the data of this register.
Page 205: Saradc_Trch
1,AAh 13.3.16 SARADC_TRCH SAR8 ADC High Channel Comparator Data Register Individual Register Names and Addresses: 1,AAh SARADC_TRCH : 1,AAh Access : POR RW : 00 Bit Name CMP_H[7:0] This register is the ADC auto align/trigger comparator data register. A trigger occurs when the high channel trigger is enabled, a selected digital block is enabled, and the selected digital block’s DR0 data is equal to the data of this register.
Page 206: Saradc_Cr2
1,ABh 13.3.17 SARADC_CR2 SAR8 ADC Control Register 2 Individual Register Names and Addresses: 1,ABh SARADC_CR2 : 1,ABh Access : POR RW : 0 RW : 0 RW : 0 RW : 02 Bit Name Test Enable Free Run Scale Size[2:0] ADC Clock[2:0] The SAR8 ADC Control Register 2 (SARADC_CR2) is used to control ADC settings.
Page 207: Saradc_Lcr
1,ACh 13.3.18 SARADC_LCR SAR8 ADC Reference Voltage Generator Control Register Individual Register Names and Addresses: 1,ACh SARADC_LCR : 1,ACh Access : POR RW : 00 Bit Name DA_L[7:0] This register Is the ADC DA register used for reference voltage generation control. It is write only in Test mode. For additional information, refer to the “Register Definitions”...
Page 208: Gdi_O_In
1,D0h 13.3.19 GDI_O_IN Global Digital Interconnect Odd Inputs Register Individual Register Names and Addresses: 1,D0h GDI_O_IN: 1,D0h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name GIONOUT7...
Page 209: Gdi_E_In
1,D1h 13.3.20 GDI_E_IN Global Digital Interconnect Even Inputs Register Individual Register Names and Addresses: 1,D1h GDI_E_IN: 1,D1h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name GIENOUT7...
Page 210: Gdi_O_Ou
1,D2h 13.3.21 GDI_O_OU Global Digital Interconnect Odd Outputs Register Individual Register Names and Addresses: 1,D2h GDI_O_OU: 1,D2h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name GOOUTIN7...
Page 211: Gdi_E_Ou
1,D3h 13.3.22 GDI_E_OU Global Digital Interconnect Even Outputs Register Individual Register Names and Addresses: 1,D3h GDI_E_OU: 1,D3h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name GOEUTIN7...
Page 212: Osc_Go_En
1,DDh 13.3.23 OSC_GO_EN Oscillator to Global Outputs Enable Register Individual Register Names and Addresses: 1,DDh OSC_GO_EN: 1,DDh Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name SLPINT...
Page 213: Osc_Cr4
1,DEh 13.3.24 OSC_CR4 Oscillator Control Register 4 Individual Register Names and Addresses: 1,DEh OSC_CR4: 1,DEh Access : POR RW : 0 Bit Name VC3 Input Select[1:0] This register selects the input clock to variable clock 3 (VC3). In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. Reserved bits should always be written with a value of ‘0’.
Page 214: Osc_Cr3
1,DFh 13.3.25 OSC_CR3 Oscillator Control Register 3 Individual Register Names and Addresses: 1,DFh OSC_CR3: 1,DFh Access : POR RW : 00 Bit Name VC3 Divider[7:0] This register selects the divider value for variable clock 3 (VC3). The output frequency of the VC3 Clock Divider is the input frequency divided by the value in this register, plus one. For exam- ple, if this register contains 07h, the clock frequency output from the VC3 Clock Divider is one eighth the input frequency.
Page 215: Osc_Cr0
1,E0h 13.3.26 OSC_CR0 Oscillator Control Register 0 Individual Register Names and Addresses: 1,E0h OSC_CR0: 1,E0h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 RW : 0 Bit Name 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed[2:0] This register is used to configure various features of internal clock sources and clock nets.
Page 216: Osc_Cr1
1,E1h 13.3.27 OSC_CR1 Oscillator Control Register 1 Individual Register Names and Addresses: 1,E1h OSC_CR1: 1,E1h Access : POR RW : 0 RW : 0 Bit Name VC1 Divider[3:0] VC2 Divider[3:0] This register selects the divider value for variable clocks 1 and 2 (VC1 and VC2). For additional information, refer to the “Register Definitions”...
Page 217: Osc_Cr2
1,E2h 13.3.28 OSC_CR2 Oscillator Control Register 2 Individual Register Names and Addresses: 1,E2h OSC_CR2: 1,E2h Access : POR RW : 0 RW : 0 RW : 0 RW : 0 Bit Name PLLGAIN EXTCLKEN RSVD SYSCLKX2DIS This register is used to configure various features of internal clock sources and clock nets. In OCD mode (OCDM=1), bits [1:0] have no effect.
Page 218: Vlt_Cr
1,E3h 13.3.29 VLT_CR Voltage Monitor Control Register Individual Register Names and Addresses: 1,E3h VLT_CR: 1,E3h Access : POR RW : 0 RW : 0 RW : 0 Bit Name PORLEV[1:0] LVDTBEN VM[2:0] This register is used to set the trip points for POR, LVD, and the supply pump. Note that reserved bits are grayed table cells and are not described in the bit description section.
Page 219: Vlt_Cmp
1,E4h 13.3.30 VLT_CMP Voltage Monitor Comparators Register Individual Register Names and Addresses: 1,E4h VLT_CMP: 1,E4h Access : POR R : 0 R : 0 R : 0 Bit Name PUMP PPOR This register is used to read the state of internal supply voltage monitors. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section.
Page 220: Imo_Tr
1,E8h 13.3.31 IMO_TR Internal Main Oscillator Trim Register Individual Register Names and Addresses: 1,E8h IMO_TR: 1,E8h Access : POR W : 00 Bit Name Trim[7:0] This register is used to manually center the oscillator’s output to a target frequency. It is strongly recommended that the user not alter this register’s values. The value in this register should not be changed.
Page 221: Ilo_Tr
1,E9h 13.3.32 ILO_TR Internal Low Speed Oscillator Trim Register Individual Register Names and Addresses: 1,E9h ILO_TR: 1,E9h Access : POR W : 0 W : 0 Bit Name Bias Trim[1:0] Freq Trim[3:0] This register sets the adjustment for the Internal Low Speed Oscillator (ILO). It is strongly recommended that the user not alter this register’s values.
Page 222: Bdg_Tr
1,EAh 13.3.33 BDG_TR Bandgap Trim Register Individual Register Names and Addresses: 1,EAh BDG_TR: 1,EAh Access : POR RW : 0 RW : 1 RW : 8 Bit Name AGNDBYP TC[1:0] V[3:0] This register is used to adjust the bandgap and add an RC filter to AGND. Note that reserved bits are grayed table cells and are not described in the bit description section.
Page 223: Eco_Tr
1,EBh 13.3.34 ECO_TR External Crystal Oscillator Trim Register Individual Register Names and Addresses: 1,EBh ECO_TR: 1,EBh Access : POR W : 0 Bit Name PSSDC[1:0] This register sets the adjustment for the 32.768 kHz External Crystal Oscillator. The value in this register should not be changed. The value is used to trim the 32.768 kHz external crystal oscillator and is set to the device specific, best value during boot.
Page 224: Fls_Pr1
1,FAh 13.3.35 FLS_PR1 Flash Program Register 1 Individual Register Names and Addresses: 1,FAh FLS_PR1: 1,FAh Access : POR RW : 0 Bit Name Bank[1:0] This register is used to specify which Flash bank should be used for SROM operations. In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below. Reserved bits should always be written with a value of ‘0’.
Page 225: Section D: Digital System
Section D: Digital System The configurable Digital System section discusses the digital components of the PSoC device and the registers associated with those components. This section encompasses the following chapters: ■ Global Digital Interconnect (GDI) on page 165 ■ Row Digital Interconnect (RDI) on page 171 ■...
Page 226: Digital Register Summary
Section D: Digital System Digital Register Summary The table below lists all the PSoC registers for the digital system in address order (Add. column) within their system resource configuration. The bits that are grayed out are reserved bits. If these bits are written, they should always be written with a value of ‘0’.
Page 227 Section D: Digital System Summary Table of the Digital Registers (continued) Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,2Ch DCB03DR0 Data[7:0] # : 00 0,2Dh DCB03DR1 Data[7:0] W : 00 DCB03DR2 0,2Eh Data[7:0]...
Page 228 Section D: Digital System Document # 001-20559 Rev. *D...
Page 229: Global Digital Interconnect (Gdi)
Global Digital Interconnect (GDI) This chapter discusses the Global Digital Interconnect (GDI) and its associated registers. The PSoC devices, CY8C24533, CY8C23533, CY8C23433CY8C24633, have the exact same global digital interconnect options, varying only in the number of 8-bit ports connected to the globals, as all PSoC CY8C2xxxx devices (except for the CY8C25122 and CY8C26xxx devices). For a complete table of the GDI registers, refer to the “Summary Table of the Digital Registers”...
Page 230: 28-Pin Global Interconnect
Global Digital Interconnect (GDI) 14.1.1 28-Pin Global Interconnect Because up to two ports are connected to a single global bus, there is a one-to-many mapping between individual For the 28-pin PSoC device, there are three 8-bit ports. nets in a global bus and port pins. For example, if GIE[1] is Therefore, there are two ports connected to the even global used to bring an input signal into a digital PSoC block, either buses and one port connected to the odd global buses.
Page 231: Register Definitions
Global Digital Interconnect (GDI) 14.2 Register Definitions The following registers are associated with the Global Digital Interconnect and are listed in address order. Each register description has an associated register table showing the bit structure for that register. For a complete table of GDI registers, refer to the “Summary Table of the Digital Registers”...
Page 232: Gdi_X_Ou Registers
Global Digital Interconnect (GDI) 14.2.2 GDI_x_OU Registers Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,D2h GDI_O_OU GOOUTIN7 GOOUTIN6 GOOUTIN5 GOOUTIN4 GOOUTIN3 GOOUTIN2 GOOUTIN1 GOOUTIN0 RW : 00 1,D3h GDI_E_OU GOEUTIN7 GOEUTIN6...
Page 233: Array Digital Interconnect (Adi)
Array Digital Interconnect (ADI) This chapter presents the Array Digital Interconnect (ADI). The digital PSoC array uses a scalable architecture that is designed to support from one to four digital PSoC rows, as defined in the Row Digital Interconnect (RDI) chapter on page 171.
Page 234 Array Digital Interconnect (ADI) Document # 001-20559 Rev. *D...
Page 235: Row Digital Interconnect (Rdi)
Row Digital Interconnect (RDI) This chapter explains the Row Digital Interconnect (RDI) and its associated registers. This chapter discusses a single digital PSoC block row. It does not discuss the functions, inputs, or outputs for individual digital PSoC blocks. Therefore, the informa- tion contained here is valid for 1 row configurations.
Page 236 Row Digital Interconnect (RDI) As shown in Figure 16-2, there is a keeper connected to the Notice on the left side of Figure 16-2 that global inputs row broadcast net and each of the row outputs. The keeper (GIE[n] and GIO[n]) are inputs to 4-to-1 multiplexers. The sets the value of these nets to ‘1’...
Page 237: Register Definitions
Row Digital Interconnect (RDI) 16.2 Register Definitions The following registers are associated with the Row Digital Interconnect (RDI) and are listed in address order. Each register description has an associated register table showing the bit structure for that register. For a complete table of RDI registers, refer to the “Summary Table of the Digital Registers”...
Page 238: Rdixis Register
Row Digital Interconnect (RDI) 16.2.3 RDIxIS Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,B2h RDI0IS BCSEL[1:0] RW : 00 LEGEND x An “x” before the comma in the address field indicates that the register exists in both register banks. The Row Digital Interconnect Input Select Register (RDIxIS) Bits 5 and 4: BCSEL[1:0].
Page 239: Rdixltx Registers
Row Digital Interconnect (RDI) 16.2.4 RDIxLTx Registers Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,B3h RDI0LT0 LUT1[3:0] LUT0[3:0] RW : 00 x,B4h RDI0LT1 LUT3[3:0] LUT2[3:0] RW : 00 LEGEND x An “x”...
Page 240: Rdixrox Registers
Row Digital Interconnect (RDI) 16.2.5 RDIxROx Registers Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,B5h RDI0RO0 GOO5EN GOO1EN GOE5EN GOE1EN GOO4EN GOO0EN GOE4EN GOE0EN RW : 00 x,B6h RDI0RO1 GOO7EN GOO3EN...
Page 241: Digital Blocks
Digital Blocks This chapter covers the configuration and use of the digital PSoC blocks and their associated registers. For a complete table of the Digital PSoC Block registers, refer to the “Summary Table of the Digital Registers” on page 162. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 17.1...
Page 242: Input Multiplexers
Digital Blocks Finally, the block’s outputs are controlled by the output reg- 5. Bypass synchronization. This should be a very rare ister, which ends in OU. selection; because if clocks are not synchronized, they may fail set up to CPU read and write commands. How- Each digital PSoC block also has three data registers (DR0, ever, it is possible for an external pin to asynchronously DR1, and DR2) and one control register (CR0).
Page 243: Clock Resynchronization Summary
Digital Blocks Table 17-1. AUXCLK Bit Selections 17.1.6 Timer Function Code Description Usage A timer consists of a period register, a synchronous down Bypass Use this setting only when SYSCLKX2 (48 MHz) is counter, and a capture/compare register, all of which are selected.
Page 244: Counter Function
Digital Blocks 17.1.7 Counter Function 17.1.7.2 Block Interrupt The counter block has a selection of two interrupt sources. A counter consists of a period register, a synchronous down interrupt on terminal count (TC) and interrupt on compare counter, and a compare register. The counter function is may be selected in Mode bit 0 of the function register.
Page 245: Usability Exceptions
Digital Blocks The dead band has two inputs: a PWM reference signal and 3. If the period (of either the high time or the low time of a KILL signal. The PWM reference signal may be derived the reference input) is less than the programmed dead from one of two sources.
Page 246: Usability Exceptions
Digital Blocks Figure 17-4. CRCPRS LFSR Structure FB Tri-State Bus (Data input for CRC, if PRS, force to logic ‘0’.) DATA (To next block, if chained.) (From previous block DO, if chained.) MSB Tri-State Bus MSB SEL is determined by a priority decode of the MSB, of the polynomial across all blocks of a CRCPRS function.
Page 247: Spi Protocol Function
Digital Blocks 17.1.10 SPI Protocol Function The Serial Peripheral Interface (SPI) is a Motorola™ specification for implementing full-duplex synchronous serial communi- cation between devices. The 3-wire protocol uses both edges of the clock to enable synchronous communication, without the need for stringent set up and hold requirements. Figure 17-5 shows the basic signals in a simple connection.
Page 248: Usability Exceptions
Digital Blocks 17.1.11.1 Usability Exceptions When SS_ is negated, the SPIS ignores any MOSI/SCLK input from the master. In addition, the SPIS state machine The following are usability exceptions for the SPI protocol is reset, and the MISO output is forced to idle at logic 1. This function.
Page 249: Asynchronous Transmitter And Receiver Functions
Digital Blocks 17.1.13 Asynchronous Transmitter and Receiver Functions The Asynchronous Transmitter and Receiver functions are illustrated in Figure 17-6. Figure 17-6. Asynchronous Transmitter and Receiver Block Diagram PSoC RS232 Drivers/Receivers such as MAX232 DCBxx DCBxx CMOS Input RS232 Output CMOS Output RS232 Input 17.1.13.1 Asynchronous Transmitter Function...
Page 250: Usability Exceptions
Digital Blocks There are two formats supported: A 10-bit frame size includ- 17.1.13.5 Usability Exceptions ing one start bit, eight data bits, and one stop bit or an 11-bit The following are usability exceptions for the asynchronous frame size including one start bit, eight data bits, one parity receiver function.
Page 251: Register Definitions
Digital Blocks 17.2 Register Definitions The following registers are associated with the Digital Blocks and listed in address order. Note that there are two banks of reg- isters associated with the PSoC device. Bank 0 encompasses the user registers (Data and Control registers, and Interrupt Mask registers) for the device and Bank 1 encompasses the Configuration registers for the device.
Page 252: Dxbxxdrx Registers
Digital Blocks 17.2.1 DxBxxDRx Registers Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,xxh DxBxxDR0 Data[7:0] # : 00 0,xxh DxBxxDR1 Data[7:0] W : 00 0,xxh DxBxxDR2 Data[7:0] # : 00 LEGEND # Access is bit specific.
Page 253: Counter Register Definitions
Digital Blocks 17.2.1.2 Counter Register Definitions There are three 8-bit Data registers and a 2-bit Control register. Table 17-6 explains the meaning of these registers in the con- text of the counter operation. Note that the descriptions of the registers are dependent on the enable/disable state of the block.
Page 254: Crcprs Register Definitions
Digital Blocks 17.2.1.4 CRCPRS Register Definitions There are three 8-bit Data registers and one 2-bit Control register. Table 17-8 explains the meaning of these registers in the context of CRCPRS operation. Note that in the CRCPRS function, a write to the DR2 Seed register is also loaded simultane- ously into DR0.
Page 255: Spi Slave Register Definitions
Digital Blocks 17.2.1.6 SPI Slave Register Definitions There are three 8-bit Data registers and one 8-bit Control/Status register. Table 17-10 explains the meaning of these registers in the context of SPIS operation. Table 17-10. SPIS Data Register Descriptions Name Function Description Shifter Not readable or writeable.
Page 256: Dxbxxcr0 Register
Digital Blocks 17.2.2 DxBxxCR0 Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,xxh DxBxxCR0 Function Control/Status bits for selected function[6:0] Enable # : 00 LEGEND Access is bit specific. Refer to the register detail for additional information. xx An “x”...
Page 257: Int_Msk1 Register
Digital Blocks Interrupt Mask Register The following register is the interrupt mask register for the digital blocks. 17.2.3 INT_MSK1 Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,E1h INT_MSK1 DCB03 DCB02...
Page 258 Digital Blocks For additional information, refer to the DxBxxFN register on page 127. Table 17-14. DxBxxFN Function Registers [7]: Data Invert 1 == Invert block’s data input 0 == Do not invert block’s data input [6]: BCEN 1 == Enable 0 == Disable [5]: End Single 1 == Block is not chained or is at the end of a chain...
Page 259: Dxbxxin Registers
Digital Blocks 17.2.5 DxBxxIN Registers Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,xxh DxBxxIN Data Input[3:0] Clock Input[3:0] RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, “Digital Register Summary”...
Page 260: Dxbxxou Registers
Digital Blocks 17.2.6 DxBxxOU Registers Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,xxh DxBxxOU AUXCLK AUXEN AUX IO Select[1:0] OUTEN Output Select[1:0] RW : 00 LEGEND xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers, “Digital Register Summary”...
Page 261 Digital Blocks The following table summarizes the available selections of SPI slave does not have a defined auxiliary output, so this the AUXCLK bits. bit is used, in conjunction with the AUX IO Select bits to con- trol the Slave Select input signal (SS_). When this bit is set, the SS_ input is forced active;...
Page 262: Timing Diagrams
Digital Blocks 17.3 Timing Diagrams The timing diagrams in this section are presented according to their functionality and are in the following order. ■ “Timer Timing” on page 198 ■ “SPIM Timing” on page 203 ■ “Counter Timing” on page 199 ■...
Page 263: Counter Timing
Digital Blocks A limitation is that capture does not work with the block clock of 48 MHz. (A fundamental limitation to timer capture operation is the fact the GPIO inputs are currently synchronized to the 24 MHz system clock). Figure 17-7. Multi-Block Timing Reload occurs Example of multi-block timer counting when all blocks...
Page 264: Dead Band Timing
Digital Blocks 17.3.3 Dead Band Timing Enable/Disable Operation. Initially both outputs are low. Normal Operation. Figure 17-9 shows typical dead band There are no critical timing requirements for enabling the timing. The incoming reference edge can occur up to one 24 block because dead band processing does not start until the MHz system clock before the edge of the block clock.
Page 265: Kill Operation
Digital Blocks If the width of the PWM low time is reduced to a point where Figure 17-13. Synchronous Restart KILL Mode it is equal to the dead band period, the corresponding phase, PHI2, disappears altogether. Note that after the ris- Short KILL, outputs off for Operation resumes on remainder of current cycle.
Page 266: Crcprs Timing
Digital Blocks 17.3.4 CRCPRS Timing 17.3.5 SPI Mode Timing Figure 17-15 shows the SPI modes, which are typically Enable/Disable Operation. Same as Timer Enable/Dis- defined as 0,1, 2, or 3. These mode numbers are an encod- able Operation (“Timer Timing” on page 198) ing of two control bits: Clock Phase and Clock Polarity.
Page 267: Spim Timing
Digital Blocks 17.3.6 SPIM Timing Enable/Disable Operation. As soon as the block is config- Normal Operation. Typical timing for an SPIM transfer is ured for SPIM, the primary output is the MSb or LSb of the shown in Figure 17-16 Figure 17-17.
Page 268 Digital Blocks Figure 17-17. Typical SPIM Timing in Mode 2 and 3 Last bit of received Shifter is loaded Free running, data is valid on this with the next Shifter is loaded Set up time internal bit rate edge and is latched byte.
Page 269 Digital Blocks Figure 17-18. SPI Status Timing for Modes 0 and 1 SS Forced Low Transfer in Progress SCLK (Mode 0) SCLK (Mode 1) SS Toggled on a Message Basis Transfer in Progress Transfer in Progress SCLK (Mode 0) SCLK (Mode 1) SS Toggled on Each Byte Transfer in Progress Transfer in Progress...
Page 270: Spis Timing
Digital Blocks 17.3.7 SPIS Timing Enable/Disable Operation. As soon as the block is config- When the block is disabled, the MISO output reverts to its ured for SPI slave and before enabling, the MISO output is idle '1' state. All internal states are reset (including CR0 sta- set to idle at logic 1.
Page 271 Digital Blocks Figure 17-21. Typical SPIS Timing in Modes 2 and 3 Shifter is loaded with Last bit of received data is valid Shifter is first byte (by leading on this edge and is latched into loaded with First edge of the SCLK). the RX Buffer register.
Page 272 Digital Blocks Figure 17-22. Mode 0 and 1 Transfer in Progress SCLK (Mode 1) SS Toggled on a Message Basis Transfer in Progress Transfer in Progress SCLK (Mode 0) SCLK (Mode 1) SS Toggled on Each Byte Transfer in Progress Transfer in Progress SCLK (Mode 0) SCLK (Mode 1)
Page 273: Transmitter Timing
Digital Blocks 17.3.8 Transmitter Timing Enable/Disable Operation. As soon as the block is config- When the block is disabled, the clock is immediately gated ured for the transmitter and before enabling, the primary low. All internal states are reset (including CR0 status) to output is set to idle at logic 1, the mark state.
Page 274 Digital Blocks Figure 17-25 shows a detail of the Tx Buffer load timing. The TX Reg Empty indicates that a new byte can be written to data bits are shifted out on each of the subsequent clocks. the TX Buffer register. When the block is enabled, this status Following the eighth bit, if parity is enabled, the parity bit is bit is immediately asserted.
Page 275: Receiver Timing
Digital Blocks 17.3.9 Receiver Timing Enable/Disable Operation. As soon as the block is config- When this occurs, the reset is negated to the clock divider ured for receiver and before enabling, the primary output is and the 3-bit counter starts an up-count. The block clock is connected to the data input (RXD).
Page 276 Digital Blocks As shown in Figure 17-28, the internal bit clock (CCLK) runs slower than the external TX bit clock and the STOP bit is sam- pled later than the actual center point. After the STOP bit is sampled, the 24 MHz reset pulse forces the receiver back to an idle state.
Page 277 Digital Blocks Framing Error status indicates that the STOP bit associated This means that although the new data is not available, the with a given byte was not received correctly (expecting a '1', previous data has been overwritten because the latch was but received a '0').
Page 278 Digital Blocks Document # 001-20559 Rev. *D...
Page 279: Section E: Analog System
Section E: Analog System The configurable Analog System section discusses the analog components of the PSoC device and the registers associated with those components. Note that the analog output drivers are described in the PSoC Core section, Analog Output Drivers chapter on page 13, because they are part of the core input and output signals.
Page 280: Application Description
Section E: Analog System Application Description bus at any one time, with the user having control of this output through register settings. 3. The local outputs (OUT, GOUT, and LOUT in the Contin- PSoC blocks are user configurable system resources. On- uous Time blocks) are routed to neighbor blocks.
Page 281: Analog Register Summary
Section E: Analog System Analog Register Summary The table below lists all the PSoC registers for the analog system in address order within their system resource configuration. The bits that are grayed out are reserved bits. If these bits are written, they should always be written with a value of ‘0’. The naming conventions for the SC and CT registers and their arrays of PSoC blocks are detailed in their respective table title rows.
Page 282 Section E: Analog System Summary Table of the Analog Registers (continued) Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access SAR8 ADC PSoC BLOCK REGISTERS (page SARADC_DL 0,67h Data[7:0] RW : 00 0,69h SARADC_CR0 ADC Channel[3:0]...
Page 283: Analog Interface
Analog Interface This chapter explains the Analog Interface and its associated registers. The analog system interface is a collection of system level interfaces to the analog array and analog reference block. For a complete table of the analog interface registers, refer to “Summary Table of the Analog Registers”...
Page 284: Analog Data Bus Interface
Analog Interface 18.1.1 Analog Data Bus Interface Table 18-1. A and B Inputs for Each Column Comparator LUT Output The Analog Data Bus Interface isolates the analog array and Comparator analog system interface registers from the CPU system data LUT Output bus, to reduce bus loading.
Page 285: Analog Column Clock Generation
Analog Interface 18.1.3 Analog Column Clock Generation Figure 18-3. Column Clock Resynchronize on an IO Write Write new clock All clocks are The analog array switched capacitor blocks require a two- selection. restarted in phase. phase, non-overlapping clock. The switched capacitor blocks are arranged two to a column (a third block in the col- CPUCLK umn is a continuous time block).
Page 286: Analog Modulator Interface (Mod Bits)
Analog Interface The ICLKS bits, which are split between the DEC_CR0 and Figure 18-4. Synchronized Write to a DAC Register DEC_CR1 registers, are used to select a source for the Stall is released here. incremental gating signal. The four IGEN bits are used to CPUCLK independently enable the gating function on a column-by- nerated)
Page 287: Architectural Description
Analog Interface 18.3.1.1 Architectural Description The architectural description for the SAR hardware accelerator is illustrated in Figure 18-5. Figure 18-5. SAR Hardware Accelerator System Analog Data Bus Data Bus Read Switched Capacitor Block Micro SAR Accelerator DAC Register Input Mux Accelerator Latch Comparator...
Page 288 Analog Interface The programming for the DAC6 block is as follows: Bits [6:4] SAR Count Value CR0: mov reg[ASD11CR0], a0h These three bits are used to initialize a 3-bit counter to // Full Feedback, ACap Value = > sequence the 6 bits of the SAR algorithm. Typically, the user // Start with Sign = 1 initializesx this register to ‘6’.
Page 289 Analog Interface To represent the true sign of the input voltage, you must invert the sign of the result from the DAC register. Therefore, the result becomes Sign = 0, Magnitude = 12, which is (3.75 – 2.5)/32 * 12 + 2.5 = 2.96875. The error is 31.25 mV, or less that one LSb of 39 mV.
Page 290: Sar Timing
Analog Interface 18.3.1.3 SAR Timing Another important function of the SAR hardware is to syn- The rising edge of PHI1 is also the optimal time to write the chronize the IO read (the point at which the comparator DAC register for maximum settling time. The timing from the value is used to make the SAR decision) to when the analog positive edge of PHI1 to the start of the IO write is 4.5 comparator bus is valid.
Page 291: Register Definitions
Analog Interface 18.4 Register Definitions The following registers are associated with the Analog Interface and are listed in address order. Each register description has an associated register table showing the bit structure for that register. For a complete table of analog interface registers, refer to the “Summary Table of the Analog Registers”...
Page 292: Cmp_Cr1 Register
Analog Interface Bit 3: SARSIGN. This bit is the SAR sign selection and Bit 0: SYNCEN. This bit is to synchronize CPU data writes optionally inverts the comparator input to the SAR accelera- to Switched Capacitor (SC) block operation in the analog tor.
Page 293: Dec_Cr0 Register
Analog Interface 18.4.4 DEC_CR0 Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access DEC_CR0 0,E6h IGEN[1:0] ICLKS0 DCOL[1:0] DCLKS0 RW : 00 The Decimator Control Register 0 (DEC_CR0) contains con- Bits 2 and 1: DCOL[1:0].
Page 294: Clk_Cr0 Register
Analog Interface 18.4.6 CLK_CR0 Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access CLK_CR0 AColumn1[1:0] AColumn0[1:0] RW : 0 1,60h The Analog Clock Source Control Register 0 (CLK_CR0) is Bits 3 and 2: AColumn1[1:0].
Page 295: Amd_Cr0 Register
Analog Interface 18.4.8 AMD_CR0 Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access AMD_CR0 AMOD0[2:0] RW : 00 1,63h The Analog Modulation Control Register 0 (AMD_CR0) is Bits 2 to 0: AMOD0[2:0]. These bits control the selection used to select the modulator bits used with each column.
Page 296 Analog Interface Document # 001-20559 Rev. *D...
Page 297: Analog Array
Analog Array This chapter presents the Analog Array, which has no registers directly associated with it. This chapter is important because it discusses the block and column level interconnects that exist in the analog PSoC array. 19.1 Architectural Description The analog array is designed to allow interaction between Figure 19-1.
Page 298: Nmux Connections General Overview
Analog Array 19.1.1 NMux Connections General Overview The NMux is an 8-to-1 mux, which determines the source for The numbers in Figure 19-2, which are associated with each the inverting (also called negative) input of Continuous Time arrow, are the corresponding NMux select line values for the PSoC blocks.
Page 299: Pmux Connections General Overview
Analog Array 19.1.2 PMux Connections General Overview The PMux is an 8-to-1 mux, which determines the source for The numbers in Figure 19-3, which are associated with each the non-inverting (also called positive) input of Continuous arrow, are the corresponding PMux select line values for the Time PSoC blocks.
Page 300: Rbotmux Connections General Overview
Analog Array 19.1.3 RBotMux Connections General Overview The RBotMux connections in the figure below are the mux The logic statements in Figure 19-4 are the RBotMux con- inputs for the bottom of the resistor string, see Figure 22-1 nections that are selected by the combination of the RBot- on page 250.
Page 301: Amux Connections General Overview
Analog Array 19.1.4 AMux Connections General Overview The AMux connections in the figure below are the mux The numbers in Figure 19-5, which are associated with each inputs for controlling both the A and C capacitor branches. arrow, are the corresponding AMux select line values for the The high order bit, ACMux[2], selects one of two inputs for data in the ACMux portion of the register.
Page 302: Cmux Connections General Overview
Analog Array 19.1.5 CMux Connections General Overview The CMux connections in the figure below are the mux The CMux connections are described in detail in the inputs for controlling the C capacitor branches. The high ASCxxCR1 register on page 84, bits ACMux[2:0]. The num- order bit, ACMux[2], selects one of two inputs for the C bers in the figure, which are associated with each arrow, are branch, which is used to control both the AMux and CMux.
Page 303: Bmux Sc/Sd Connections General Overview
Analog Array 19.1.6 BMux SC/SD Connections General Overview The BMux SC/SD connections in the figure below are the The numbers in Figure 19-7, which are associated with each mux inputs for controlling the B capacitor branches. (See arrow, are the corresponding BMux select line values for the Figure 23-1 on page 256 Figure 23-2 on page 257.) The...
Page 304 Analog Array Document # 001-20559 Rev. *D...
Page 305: Analog Input Configuration
Analog Input Configuration This chapter discusses the Analog Input Configuration and its associated registers. For a complete table of analog input con- figuration registers, refer to the “Summary Table of the Analog Registers” on page 217. For a quick reference of all PSoC reg- isters in address order, refer to the Register Details chapter on page 20.1...
Page 306: Two Column Analog Input Configuration
Analog Input Configuration 20.1.1 Two Column Analog Input Configuration The two column analog input configuration is detailed in Figure 20-2, along with the analog driver and pin specifics. Figure 20-2. Two Column PSoC Analog Pin Block Diagram P0[7] P0[6] 8 Pin Part P0[5] P0[4] P0[3]...
Page 307: Register Definitions
Analog Input Configuration 20.2 Register Definitions The following registers are associated with Analog Input Configuration and are listed in address order. Each register descrip- tion has an associated register table showing the bit structure for that register. For a complete table of the analog input config- uration registers, refer to the “Summary Table of the Analog Registers”...
Page 308 Analog Input Configuration Document # 001-20559 Rev. *D...
Page 309: Analog Reference
Analog Reference This chapter discusses the Analog Reference generator and its associated register. The reference generator establishes a set of three internally fixed reference voltages for AGND, RefHi, and RefLo. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 21.1 Architectural Description...
Page 310: Register Definitions
Analog Reference 21.2 Register Definitions The following register is associated with the Analog Reference. For a complete table of all analog registers, refer to the “Sum- mary Table of the Analog Registers” on page 217. The register description below has an associated register table showing the bit structure. Only certain bits are accessible to be read or written.
Page 311 Analog Reference Table 21-2. REF[2:0]: AGND, RefHi, and RefLo Operating Parameters AGND RefHi RefLo Notes [2:0] Source Voltage Source Voltage Source Voltage 000b Vdd/2 2.5 V Vdd/2+Vbg 3.8 V Vdd/2-Vbg 1.2 V 5.0 V System 1.65 V 2.95 V 0.35 V 3.3 V System 001b P2[4]...
Page 312 Analog Reference Document # 001-20559 Rev. *D...
Page 313: Continuous Time Psoc Block
Continuous Time PSoC Block This chapter discusses the Analog Continuous Time PSoC Block and its associated registers. This block supports program- mable gain or attenuation opamp circuits; instrumentation amplifiers, using two CT blocks (differential gain); and modest response-time analog comparators. For a complete table of the Continuous Time PSoC Block registers, refer to the “Sum- mary Table of the Analog Registers”...
Page 314 Continuous Time PSoC Block Figure 22-1. Analog Continuous Time Block Diagram TestMux LPCMPEN RefHi RefLo AGND Gain ABUS AnalogBus CompCap PMuxOut CBUS Latch Block Inputs CBUS Driver Port Input Transparent, PHI1 or PHI2 ABUS GOUT AGND PMux NMux RTopMux Block Inputs AGND LOUT RefHi, RefLo...
Page 315: Register Definitions
Continuous Time PSoC Block 22.2 Register Definitions The following registers are associated with the Continuous Time (CT) PSoC Block and are listed in address order. Each reg- ister description has an associated register table showing the bit structure for that register. For a complete table of the CT PSoC Block registers, refer to the “Summary Table of the Analog Registers”...
Page 316 Continuous Time PSoC Block Bit 1: INSAMP. This bit is used to connect the resistors of two continuous time blocks as part of a three-opamp instru- mentation amplifier. The INSAMP bit must be high for the three-opamp instrumentation amplifier (see Figure 22-3).
Page 317: Acbxxcr0 Register
Continuous Time PSoC Block 22.2.2 ACBxxCR0 Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,71h ACB00CR0 RTapMux[3:0] Gain RTopMux RBotMux[1:0] RW : 00 x,75h ACB01CR0 RTapMux[3:0] Gain RTopMux RBotMux[1:0] RW : 00 LEGEND...
Page 318: Acbxxcr2 Register
Continuous Time PSoC Block 22.2.4 ACBxxCR2 Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,73h ACB00CR2 CPhase CLatch CompCap TMUXEN TestMux[1:0] PWR[1:0] RW : 00 x,77h ACB01CR2 CPhase CLatch CompCap TMUXEN...
Page 319: Switched Capacitor Psoc Block
Switched Capacitor PSoC Block This chapter presents the Analog Switched Capacitor Block and its associated registers. The analog Switched Capacitor (SC) blocks are built around a low offset, low noise operational amplifier. For a complete table of the Switched Capacitor PSoC Block registers, refer to the “Summary Table of the Analog Registers”...
Page 320 Switched Capacitor PSoC Block Figure 23-1. Analog Switch Cap Type C PSoC Blocks  *AutoZero BQTA 16,32 0,1,…,30,31 C  +!AutoZero) * FSW1 C Inputs  * FSW0 ACMux 0,1,…,30,31 C   +AutoZero A Inputs RefHi   RefLo !AutoZero AGND ARefMux...
Page 321: Application Description
Switched Capacitor PSoC Block Figure 23-2. Analog Switch Cap Type D PSoC Blocks  *AutoZero 16,32 0,1,…,30,31 C  +!AutoZero) BQTA * FSW1  * FSW0 A Mux 0,1,…,30,31 C   +AutoZero A Inputs  RefHi  RefLo !AutoZero AGND AnalogBus ARefMux...
Page 322: Register Definitions
Switched Capacitor PSoC Block 23.3 Register Definitions The following registers are associated with the Switched Capacitor (SC) PSoC Block and are listed in address order. Each register description has an associated register table showing the bit structure for that register. For a complete table of SC PSoC Block registers, refer to the “Summary Table of the Analog Registers”...
Page 323: Ascxxcr0 Register
Switched Capacitor PSoC Block Analog Switch Cap Type C PSoC Block Control Registers In the tables below, an “x” before the comma in the address field (in the "Add." column) indicates that the register exists in both register banks. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m=row index and n=column index.
Page 324: Ascxxcr1 Register
Switched Capacitor PSoC Block 23.3.2 ASCxxCR1 Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,95h ASC21CR1 ACMux[2:0] BCap[4:0] RW : 00 LEGEND x An “x” before the comma in the address field indicates that the register exists in both register banks. The Analog Switch Cap Type C Block Control Register 1 Bits 4 to 0: BCap[4:0].
Page 325: Ascxxcr3 Register
Switched Capacitor PSoC Block 23.3.4 ASCxxCR3 Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,97h ASC21CR3 ARefMux[1:0] FSW1 FSW0 BMuxSC[1:0] PWR[1:0] RW : 00 LEGEND x An “x” before the comma in the address field indicates that the register exists in both register banks. The Analog Switch Cap Type C Block Control Register 3 Bit 4: FSW0.
Page 326: Asdxxcr0 Register
Switched Capacitor PSoC Block Analog Switch Cap Type D PSoC Block Control Registers In the tables below, an “x” before the comma in the address field (in the "Add." column) indicates that the register exists in both register banks. The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m=row index and n=column index.
Page 327: Asdxxcr1 Register
Switched Capacitor PSoC Block 23.3.6 ASDxxCR1 Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,85h ASD11CR1 AMux[2:0] BCap[4:0] RW : 00 LEGEND x An “x” before the comma in the address field indicates that the register exists in both register banks. The Analog Switch Cap Type D Block Control Register 1 Bits 4 to 0: BCap[4:0].
Page 328: Asdxxcr3 Register
Switched Capacitor PSoC Block 23.3.8 ASDxxCR3 Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x,87h ASD11CR3 ARefMux[1:0] FSW1 FSW0 BMuxSD PWR[1:0] RW : 00 LEGEND x An “x” before the comma in the address field indicates that the register exists in both register banks. The Analog Switch Cap Type D Block Control Register 3 Bit 3: BSW.
Page 329: Sar8 Adc Psoc Block
SAR8 ADC PSoC Block This chapter briefly discusses the SAR8 ADC PSoC Block and its associated registers. For a complete table of the SAR8 ADC registers, refer to the “Summary Table of the Analog Registers” on page 217. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 24.1...
Page 330: Register Definitions
SAR8 ADC PSoC Block 24.2 Register Definitions The following registers are associated with the SAR8 ADC PSoC Block and are listed in address order. The register descrip- tions below have an associated register table showing the bit structure. The bits that are grayed out in the register tables are reserved bits and are not detailed in the register descriptions that follow. Reserved bits should always be written with a value of ‘0’.
Page 331: Saradc_Cr1 Register
SAR8 ADC PSoC Block 24.2.3 SARADC_CR1 Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,6Ah SARADC_CR1 PWRSELADC PWRSELR2R Align Source [1:0] Align Enable RW : 0 The SAR8 ADC Control Register 1 (SARADC_CR1) is used We define a 16-bit comparator in cases when the PWM is 16 to control normal ADC operation and show ADC status.
Page 332: Saradc_Trs Register
SAR8 ADC PSoC Block Bit 7: PWRSELADC. When ‘0’, ADC analog block obtains Bits 2 and 1: Align Source[1:0]. When ‘00‘, low and high power supply from inside VPWR. When ‘1’, ADC analog channels are completely independent. Both can trigger block obtains power supply from P3[0].
Page 333: Saradc_Trcl Register
SAR8 ADC PSoC Block 24.2.5 SARADC_TRCL Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,A9h SARADC_TRCL CMP_L[7:0] RW : 00 The SAR8 ADC Low Channel Comparator Data Register. Bits 7 to 0: CMP_L[7:0].
Page 334: Saradc_Cr2 Register
SAR8 ADC PSoC Block 24.2.7 SARADC_CR2 Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,ABh SARADC_CR2 Test Enable Free Run Scale Size[2:0] ADC Clock[2:0] RW : 0 The SAR8 ADC Control Register 2 (SARADC_CR2) is used Bits 2 to 0: ADC Clock[2:0].
Page 335: Section F: System Resources
Section F: System Resources The System Resources section discusses the system resources that are available for the PSoC device and the registers associated with those resources. This section encompasses the following chapters: ■ Digital Clocks on page 275 ■ Internal Voltage Reference on page 311 ■...
Page 336: System Resources Register Summary
Section F: System Resources System Resources Register Summary The table below lists all the PSoC registers for the system resources, in address order, within their system resource configu- ration. The bits that are grayed out are reserved bits. If these bits are written, they should always be written with a value of ‘0’. Note that the CY8C24533, CY8C23533, CY8C23433CY8C24633 are 1 digital row and 2 analog column devices.
Page 337 Section F: System Resources Summary Table of the System Resource Registers (continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access INTERNAL VOLTAGE REFERENCE REGISTER (page 1,EAh BDG_TR AGNDBYP TC[1:0] V[3:0] RW : 00 SYSTEM RESET REGISTERS (page...
Page 338 Section F: System Resources Document # 001-20559 Rev. *D...
Page 339: Digital Clocks
Digital Clocks This chapter discusses the Digital Clocks and their associated registers. It serves as an overview of the clocking options available in the PSoC devices. For detailed information on specific oscillators, see the individual oscillator chapter in the sec- tion called “PSoC Core”...
Page 340 Digital Clocks Figure 25-1. Overview of PSoC Clock Sources P1[4] SYSCLKX2 Disable (EXTCLK Input) PLL Lock Enable IMO Trim Register OSC_CR2[0] OSC_CR0[6] IMO_TR[7:0] Clock SYSCLKX2 Doubler Internal Main Oscillator Phase OSC_CR2[2] (IMO) Locked SYSCLK Loop EXTCLK (PLL) Clock Divider CPU_SCR1[4] OSC_CR0[2:0] Slow IMO Option CPUCLK...
Page 341: Khz Crystal Oscillator
Digital Clocks 25.1.3 32.768 kHz Crystal Oscillator Figure 25-2. Operation of the Clock Doubler 21 ns Nominal The PSoC may be configured to use an external crystal. The crystal oscillator is discussed in detail in the chapter “Exter- nal Crystal Oscillator (ECO)” on page Extenal Clock 25.1.4 External Clock...
Page 342: Psoc Device Distinctions
Digital Clocks Figure 25-3. Switch from IMO to the External Clock with a CPU Clock Divider of Two or Greater Extenal Clock SYSCLK CPUCLK IOW_ EXTCLK bit IMO is External clock is deselected selected Figure 25-4. Switch from IMO to External Clock with the CPU Running with a CPU Clock Divider of One External Clock SYSCLK CPUCLK...
Page 343: Register Definitions
Digital Clocks 25.3 Register Definitions The following registers are associated with the Digital Clocks and are listed in address order. Each register description has an associated register table showing the bit structure for that register. For a complete table of digital clock registers, refer to the “Summary Table of the System Resource Registers”...
Page 344: Osc_Go_En Register
Digital Clocks 25.3.3 OSC_GO_EN Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,DDh OSC_GO_ SLPINT SYSCLKX2 SYSCLK CLK24M CLK32K RW : 00 Oscillator Global Outputs Enable Register Bit 6: VC3. This bit enables the driving of the VC3 clock (OSC_GO_EN) is used to enable tri-state buffers that con- onto GOE[6].
Page 345: Osc_Cr3 Register
Digital Clocks 25.3.5 OSC_CR3 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,DFh OSC_CR VC3 Divider[7:0] RW : 00 The Oscillator Control Register 3 (OSC_CR3) selects the The VC3 clock net can generate a system interrupt. Once divider value for variable clock 3 (VC3).
Page 346: Osc_Cr0 Register
Digital Clocks 25.3.6 OSC_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,E0h OSC_CR 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed[2:0] RW : 00 The Oscillator Control Register 0 (OSC_CR0) is used to tion on the supported frequencies for externally supplied configure various features of internal clock sources and clocks.
Page 347: Osc_Cr1 Register
Digital Clocks 25.3.7 OSC_CR1 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1,E1h OSC_CR VC1 Divider[3:0] VC2 Divider[3:0] RW : 00 The Oscillator Control Register 1 (OSC_CR1) selects the Table 25-7.
Page 348: Osc_Cr2 Register
Digital Clocks 25.3.8 OSC_CR2 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access OSC_CR SYSCLKX2 1,E2h PLLGAIN EXTCLKEN RSVD RW : 00 The Oscillator Control Register 2 (OSC_CR2) is used to If an external clock is enabled, PLL mode should be off.
Page 349: Multiply Accumulate (Mac)
Multiply Accumulate (MAC) This chapter presents the Multiply Accumulate (MAC) and its associated registers. The MAC block is a fast 8-bit multiplier or a fast 8-bit multiplier with 32-bit accumulate. For a complete table of the MAC registers, refer to the “Summary Table of the System Resource Registers”...
Page 350: Application Description
Multiply Accumulate (MAC) 26.2 Application Description 26.2.2 Accumulation After Multiplication Accumulation of products is a feature that is implemented on 26.2.1 Multiplication with No top of simple multiplication. When using the MAC to accu- mulate the products of successive multiplications, two 8-bit Accumulation signed values are used for input.
Page 351: Register Definitions
Multiply Accumulate (MAC) 26.3 Register Definitions The following registers are associated with the MAC PSoC Block and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The ‘X’ in the Access column of some register tables signify that the value after power on reset is unknown.
Page 352: Mulx_Dh Register
Multiply Accumulate (MAC) 26.3.3 MULx_DH Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,EAh MUL0_DH Data[7:0] R : XX LEGEND X The value after power on reset is unknown. The Multiply Result High Byte Register (MULx_DH) holds For additional information, refer to the MULx_DH register on...
Page 353: Macx_Y/Accx_Dr0 Register
Multiply Accumulate (MAC) 26.3.6 MACx_Y/ACCx_DR0 Register Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access MAC0_Y/ 0,EDh Data[7:0] RW : 00 ACC0_DR0 The Accumulator Data Register 0 (MACx_Y/ACCx_DR0) is When this register is written, the product of the written value the multiply accumulate Y register and the first byte of the and the current value of the MACx_X register is calculated, accumulated value.
Page 354 Multiply Accumulate (MAC) Document # 001-20559 Rev. *D...
Page 355: Decimator
Decimator This chapter explains the PSoC Decimator block and its associated registers. The decimator block is a hardware assist for digital signal processing applications. The decimator is used for delta-sigma ADCs and incremental ADCs. For a complete table of the decimator registers, refer to the “Summary Table of the System Resource Registers”...
Page 356 Decimator Figure 27-2. The principle of operation of a Sinc2 decimation filter is inferred in Figure 27-2 and Equation 1. The decimator’s custom data path follows the Accumulation stage of Figure 27-2, in principle. The Differentiation is accomplished with external firmware in user modules.Sinc Filter Block Diagram Accumulation...
Page 357: Register Definitions
Decimator 27.2 Register Definitions The following registers are associated with the Decimator and listed in address order. Each register description has an asso- ciated register table showing the bit structure for that register. The bits that are grayed out in the tables are reserved bits and are not detailed in the register description that follows.
Page 358: Dec_Cr0 Register
Decimator 27.2.3 DEC_CR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,E6h DEC_CR IGEN[1:0] ICLKS0 DCOL[1:0] DCLKS0 RW : 00 The Decimator Control Register 0 (DEC_CR0) contains con- Bits 2 and 1: DCOL[1:0].
Page 359: I2C
This chapter explains the I C™ block and its associated registers. The I2C communications block is a serial processor designed to implement a complete I2C slave or master. For a complete table of the I2C registers, refer to the “Summary Table of the System Resource Registers”...
Page 360: Application Description
Figure 28-1. Basic I C Data Transfer with 7-Bit Address Format START 7-Bit Address 8-Bit Data ACK/ STOP NACK 28.2 Application Description 28.2.1 Slave Operation Assuming Slave mode is enabled, it is continually listening If there is an address match, the RW bit determines how the to or on the bus for a start condition.
Page 361: Master Operation
28.2.2 Master Operation To prepare for a Master mode transaction, the PSoC device When the interrupt occurs in Slave mode, the PSoC determines if the bus is free. This is done by polling the Bus- device determines that the Start command was unsuc- Busy status.
Page 362: Register Definitions
28.3 Register Definitions The following registers are associated with I2C and are listed in address order. Each register description has an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.
Page 363 Bit 4: Stop IE (Interrupt Enable). When this bit is set, a Bit 0: Enable Slave. When the slave is enabled, the block master or slave can interrupt on stop detection. The status generates an interrupt on any start condition and an address bit associated with this interrupt is the Stop Status bit in the byte that it receives, indicating the beginning of an I2C Slave Status and Control register.
Page 364: I2C_Scr Register
28.3.2 I2C_SCR Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Stop Byte I2C_SCR 0,D7h Bus Error Lost Arb Address Transmit # : 00 Status Complete LEGEND Table 28-4 # Access is bit specific.
Page 365 Bit 6: Lost Arb. This bit is set when I2C bus contention is No further interrupts occur until the next address is received. detected, during a Master mode transfer. Contention occurs If the address does match, firmware must ACK the received when a master is writing a ‘1’...
Page 366: I2C_Dr Register
Slave Transmitter: In receive mode, the bit is set after the eight bits of data are received. When this bit is set, an interrupt is generated at ‘0’: ACK. The master wants to read another byte. The these data sampling points, which are associated with the slave loads the next byte into the I2C_DR register and SCL input clock rising (see details in the Timing section).
Page 367 There are three possible outcomes as a result of setting the Other cases where the Start bit is used to generate a Start Start Gen bit. condition are as follows. 1. The bus is free and the start condition is generated suc- 1.
Page 368: Timing Diagrams
28.4 Timing Diagrams 28.4.1 Clock Generation Figure 28-4 illustrates the I2C input clocking scheme. The SYSCLK pin is an input into a four-stage ripple divider that pro- vides the baud rate selections. When the block is disabled, all internal state is held in a reset state. When either the Master or Slave Enable bits in the I2C_CFG register are set, the reset is synchronously released and the clock generation is enabled.
Page 369: Status Timing
28.4.3 Status Timing Figure 28-6 illustrates the interrupt timing for Byte Com- Figure 28-7 shows the timing for Stop Status. This bit is set plete, which occurs on the positive edge of the ninth clock (and the interrupt occurs) two clocks after the synchronized (byte + ACK/NACK) in transmit mode and on the positive and filtered SDA line transitions to a ‘1’, when the SCL line is edge of the eighth clock in receive mode.
Page 370: Master Start Timing
28.4.4 Master Start Timing When firmware writes the Start Gen command, hardware resynchronizes this bit to SYSCLK, to ensure a minimum of a full SYSCLK of set up time to the next clock edge. When the start is initiated, the SCL line is left high for 6/14 clocks (correspond- ing to 16/32 times sampling rates).
Page 371: Master Restart Timing
Figure 28-11. Master Stop/Start Chaining CLOCK SDA_IN (Synchronized) STOP START STOP/START DETECT SCL_OUT SDA_OUT 2 Clocks 5/13 Clocks 8/16 Clocks 28.4.5 Master Restart Timing Figure 28-12 shows the Master Restart timing. After the ACK/NACK bit, the clock is held low for a half-bit time (8/16 clocks corresponding to the 16 or 32 times sampling rates), during which time the data is allowed to go high, then a valid start is gen- erated in the following 3 half-bit times as shown.
Page 372: Master/Slave Stall Timing
28.4.7 Master/Slave Stall Timing When a Byte Complete interrupt occurs, the PSoC device firmware must respond with a write to the I2C_SCR register to con- tinue the transfer (or terminate the transfer). The interrupt occurs two clocks after the rising edge of SCL_IN (see “Status Tim- ing”...
Page 373: Master Clock Synchronization
28.4.9 Master Clock Synchronization Figure 28-16 shows the timing associated with Master Clock Synchronization. Clock synchronization is always operational, even if it is the only master on the bus. In which case, it is synchronizing to its own clock. In the wired AND bus, an SCL out- put of ‘0’...
Page 374 Document # 001-20559 Rev. *D...
Page 375: Internal Voltage Reference
Internal Voltage Reference This chapter discusses the Internal Voltage Reference and its associated register. The internal voltage reference provides an absolute value of 1.3V to a variety of subsystems in the PSoC device. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 29.1...
Page 376: Register Definitions
Internal Voltage Reference 29.2 Register Definitions The following register is associated with the Internal Voltage Reference. The Internal Voltage Reference is trimmed for gain and temperature coefficient using the BDG_TR register. The register description below has an associated register table showing the bit structure.
Page 377: System Resets
System Resets This chapter discusses the System Resets and their associated registers. PSoC devices support several types of resets. The various resets are designed to provide error-free operation during power up for any voltage ramping profile, to allow for user- supplied external reset and to provide recovery from errant code operation.
Page 378: Register Definitions
System Resets 30.3 Register Definitions The following registers are associated with the PSoC System Resets and are listed in address order. Each register descrip- tion has an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits and are not detailed in the register descriptions that follow.
Page 379: Cpu_Scr0 Register
System Resets 30.3.2 CPU_SCR0 Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0,FFh CPU_SC GIES WDRS PORS Sleep STOP # : XX LEGEND Access is bit specific. Refer to register detail for additional information. XX The reset value is 10h after POR and 20h after a watchdog reset.
Page 380: Timing Diagrams
System Resets 30.4 Timing Diagrams 30.4.1 Power On Reset 30.4.2 Watchdog Timer Reset A Power on Reset (POR) is triggered whenever the supply The user has the option to enable the Watchdog Timer voltage is below the POR trip point. POR ends once the sup- Reset (WDR), by clearing the PORS bit in the CPU_SCR0 ply voltage rises above this voltage.
Page 381 System Resets Figure 30-3. Key Signals During POR and XRES POR (IPOR followed by PPOR): Reset while POR is high (IMO off), then 511(+) cycles (IMO on), and then the CPU reset is released. XRES is the same, with N=8. CLK32 IPOR PPOR...
Page 382: Reset Details
System Resets 30.4.3 Reset Details Timing and functionality details are summarized in Table 30-1. Figure 30-3 shows some of the relevant signals for IPOR and PPOR, and XRES, while Figure 30-2 shows signaling for WDR . Table 30-1. Details of Functionality for Various Resets Item IPOR (Part of POR) PPOR (Part of POR)
Page 383: Por And Lvd
POR and LVD This chapter briefly discusses the POR and LVD circuits and their associated registers. For a complete table of the POR and LVD registers, refer to the “Summary Table of the System Resource Registers” on page 272. For a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 31.1...
Page 384: Register Definitions
POR and LVD 31.2 Register Definitions The following registers are associated with the POR and LVD, and are listed in address order. The register descriptions below have an associated register table showing the bit structure. The bits that are grayed out in the register tables are reserved bits and are not detailed in the register descriptions that follow. Reserved bits should always be written with a value of ‘0’.
Page 385: Section G: Glossary
Section G: Glossary The Glossary section explains the terminology used in this technical reference manual. Glossary terms are characterized in bold, italic font throughout the text of this manual. In a CPU, a register in which intermediate results are stored. Without an accumulator, it would be accumulator necessary to write the result of each calculation (addition, subtraction, shift, and so on.) to main memory and read them back.
Page 386 Section G: Glossary See Boolean Algebra . API (Application Pro- A series of software routines that comprise an interface between a computer application and gramming Interface) lower-level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. array An array, also known as a vector or list, is one of the simplest data structures in computer pro- gramming.
Page 387 Section G: Glossary A single digit of a binary number. Therefore, a bit may only have a value of ‘0’ or ‘1’. A group of 8 bits is called a byte. Because the PSoC's M8C is an 8-bit microcontroller, the PSoC's native data chunk size is a byte.
Page 388 Section G: Glossary capture To extract information automatically through the use of software or hardware, as opposed to hand-entering of data into a computer file. chaining Connecting two or more 8-bit digital blocks to form 16-, 24-, and even 32-bit functions. Chaining allows certain signals such as Compare, Carry, Enable, Capture, and Gate to be produced from one block to another.
Page 389 Section G: Glossary debugger A hardware and software system that allows the user to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band A period of time when neither of two or more signals are in their active state or in transition.
Page 390 Section G: Glossary firmware The software that is embedded in a hardware device and executed by the CPU. The software may be executed by the end user, but it may not be modified. flag Any of various types of indicators used for identification of a condition or event (for example, a character that signals the termination of a transmission).
Page 391 Section G: Glossary hexidecimal A base 16 numeral system (often abbreviated and called hex), usually written using the symbols 0-9 and A-F. It is a useful system in computers because there is an easy mapping from four bits to a single hex digit. Thus, one can represent every byte as two consecutive hexadecimal digits. Compare the binary, hex, and decimal representations: 0000b = 0001b =...
Page 392 Section G: Glossary interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service rou- A block of code that normal code execution is diverted to when the M8C receives a hardware tine (ISR) interrupt.
Page 393 Section G: Glossary An 8-bit Harvard Architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. macro A programming language macro is an abstraction, whereby a certain textual pattern is replaced according to a defined set of rules.
Page 394 Section G: Glossary NAND See Boolean Algebra . negative edge A transition from a logic 1 to a logic 0. Also known as a falling edge. The routing between devices. nibble A group of four bits, which is one-half of a byte. noise 1.
Page 395 A set of rules. Particularly the rules that govern networked communications. PSoC Cypress Semiconductor’s Programmable System-on-Chip (PSoC). PSoC® is a registered trade- mark and Programmable System-on-Chip™ is a trademark of Cypress. PSoC blocks See analog blocks and digital blocks .
Page 396 Section G: Glossary rising edge See positive edge . An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. routine A block of code, called by another block of code, that may have some general or frequent use. routing Physically connecting objects in a design according to design rules set in the reference library.
Page 397 Section G: Glossary slave device A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface.
Page 398 Section G: Glossary The connection between two blocks of a device created by connecting several blocks/compo- nents in a series, such as a shift register or resistive voltage divider. terminal count The state at which a counter is counted down to zero. threshold The minimum value of a signal that can be detected by the system or sensor under consider- ation.
Page 399 Section G: Glossary watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. waveform The representation of a signal as a plot of amplitude versus time. See Boolean Algebra . Document # 001-20559 Rev.
Page 400 Section G: Glossary Document # 001-20559 Rev. *D...
Page 401: Index
Index address spaces, CPU core 35 addressing modes, M8C 39 28- to 32-pin global interconnect 230 ADI, See array digital interconnect 3.768 kHz clock selection 85 AGNDBYP bit 222, 376 32 kHz clock selection 83, 95 in BDG_TR register 222 32k Select bit 88, 92, 215 AINT bits 130 Align Enable bit 135...
Page 402 Index analog interface 283 in ASDxxCR0 register 143 architecture 283 ASY_CR register 131, 291 column clock generation 285 asynchronous receiver function 249 comparator bus interface 284 asynchronous transmitter function 249 data bus interface 284 AutoZero bit decimator interface 285 in ASCxxCR2 register 149 device distinctions 286 in ASDxxCR2 register 145 incremental ADC interface 285...
Page 403 Index CLatch bit 142 address spaces 35 CLK_CR0 register 197, 294 addressing modes 39 CLK_CR1 register 198, 294 instruction formats 38 CLK24M bit 212 instruction set summary 36–37 CLK32K bit 212 internal M8C registers 35 Clock Input bits overview 35 in DxBxxIN register 194 register definitions 44 Clock Phase bit in DCBxxCR0 124, 125...
Page 404 Index DCB03_HL bits dead band timing 264 in SARADC_TRS register 203 receiver timing 275 DCB0x bit SPI mode timing 266 in INT_CLR1 register 165 SPIM timing 267 in INT_MSK1 register 169 SPIS timing 270 DCBxxCR0 registers 124–127 timer timing 262 DCLKSx bits transmitter timing 273 in DEC_CR0 register 174...
Page 405 Index in DxBxxFN register 191 GIES bit 186 ENSWINT bit 65, 167 GIONOUTx bits EraseAll function in SROM 49 in GDI_O_IN register 208 EraseBlock function in SROM 48 global digital interconnect 229 EXGAIN bit 137 28- to 32-pin global interconnect 230 EXTCLKEN bit 81, 93, 217 architecture 229 external crystal oscillator 85...
Page 406 Index IDEC bit 175 IRESS bit 51, 80, 87, 185 IGEN bits 174 ISx bits 153 ILO_TR register 83, 221 ILO, See internal low speed oscillator IMO_TR register 81, 220 IMO, See internal main oscillator look-up table (LUT) function 284 incremental ADC interface 285 Lost Arb bit 159 index memory page pointer in RAM paging 57...
Page 407 Index PRTxIC1 register 75, 190 PRTxIE register 72, 114 OSC_CR0 register 88, 92, 100, 215, 346 PSelect bit 158 OSC_CR1 register 216, 347 PSoC core OSC_CR2 register 81, 93, 217, 348 architecture 31 OSC_CR3 register 214, 345 overview 18 OSC_CR4 register 213, 344 PSoC device OSC_GO_EN register 212, 344 characteristics 20...
Page 408 Index CPU core 44 features 329 decimator 357 register definitions 330 digital blocks 251 SARADC_CR0 register 134, 330 digital clocks 343 SARADC_CR1 register 135, 331 external crystal oscillator 87 SARADC_CR2 register 206, 334 general purpose IO 72 SARADC_DL register 133, 330 global digital interconnect 231 SARADC_LCR register 207, 334 I2C 362...
Page 409 Index started, getting 21 TC bits STOP bit 186 in BDG_TR register 222 Stop IE bit 158 TC Pulse Width bit 120 Stop Status bit 159 temperature sensing in analog 303 summary of registers Test Enable bit analog system 281 in SARADC_CR2 register 206 digital system 226 TestMux bits 142...
Page 410 Index watchdog timer reset 380 WDRS bit 186 WDSL_Clear bits 171 WriteBlock function in SROM 48 XIO bit 44, 59, 184 Zero bit 44, 59, 184 Document # 001-20559 Rev. *D...

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Cypress PSoC CY8C24533 Technical Reference Manual

Section A: Overview

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