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Cypress CYW43455 Manual

Single-chip 5g wifi ieee 802.11n/ac mac/ baseband/ radio with integrated bluetooth 5.0
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Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as "Cypress" document as this is the
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to offer the product to new and existing customers as part of the Infineon product
portfolio.
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The fact that Infineon offers the following product as part of the Infineon product
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when appropriate, and any changes will be set out on the document history page.
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  • Page 1 Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio.
  • Page 2 Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number.
  • Page 3 Switch CYW43455 BT_REG_ON UART Bluetooth Host I/F BT_DEV_W AKE BT_HOST_W AKE 2. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface. Document Number: 002-15051 Rev. *O Page 2 of 118...

  • Page 4: Table Of Contents

    2. Power Supplies and Power Management ..7 8.6 JTAG/SWD Interface ..........41 2.1 Power Supply Topology ........7 9. WLAN Host Interfaces ........42 2.2 CYW43455 PMU Features ........7 9.1 SDIO v3.0 ............42 2.3 WLAN Power Management ....... 10 9.2 SDIO Pins ............42 2.4 PMU Sequencing ..........
  • Page 5 CYW43455 19. Power-Up Sequence and Timing ....113 15.7 General Spurious Emissions Specifications ..89 19.1 Sequencing of Reset and Regulator Control 16. Internal Regulator Electrical Specifications. 94 Signals .............113 16.1 Core Buck Switching Regulator ......94 20. Package Information ........115 16.2 3.3V LDO (LDO3P3) .........

  • Page 6: Cyw43455 Overview

    2.4 LNA 5 GHz 2.4 GHz WLAN: 5 GHz: iPA, iLNA, eLG, eTR 2 GHz: iPA, iLNA, eLG, iTR BT:  Shared LNA, iTR Diplexer 3. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface. Document Number: 002-15051 Rev. *O Page 5 of 121...

  • Page 7: Standards Compliance

    CCXv5 ❐ WFAEC ❐ IEEE 802.15.2 Coexistence Compliance (on-silicon solution compliant with IEEE 3-wire requirements) ■ The CYW43455 supports the following future drafts/standards: IEEE 802.11r (fast roaming between APs) ■ IEEE 802.11w (secure management frames) ■ IEEE 802.11 Extensions: ■...

  • Page 8: Power Supplies And Power Management

    Figure 3 Figure 4 show the regulators and a typical power topology7. 4. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface. Document Number: 002-15051 Rev. *O Page 7 of 121...
  • Page 9 WL VDDM (SRAMs + AOS) BT VDDM BT Digital Power switch No power switch 5. The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface. Document Number: 002-15051 Rev. *O Page 8 of 121...
  • Page 10 CYW43455 Figure 4. Typical Power Topology (Page 2 of 2) CYW43455 Shaded areas are internal to the device. BTLDO2P5 2.5V Max 70 mA BT CLASS 1 PA Avg 15 mA 2.2 µF 10 pF 0402 0201 WL RF – PA (2.4 GHz, 5 GHz) LDO3P3 WL RF –...

  • Page 11: Wlan Power Management

    Slower clock speeds are used wherever possible. The CYW43455 WLAN power states are described as follows: Active mode— All WLAN blocks in the CYW43455 are powered up and fully functional with active carrier sensing and frame trans- ■ mission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer.

  • Page 12: Power-Off Shutdown

    When the CYW43455 is powered on from this state, it is the same as a normal power-up and the device does not retain any information about its state from before it was powered down.

  • Page 13: Frequency References

    In addition, a low-power oscillator (LPO) is provided for lower power mode timing. 3.1 Crystal Interface and Clock Generation The CYW43455 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator including all external components is shown in Figure 5.

  • Page 14: External Frequency Reference

    Figure 6. The internal clock buffer connected to this pin will be turned OFF when the CYW43455 goes into sleep mode. When the clock buffer turns ON and OFF there will be a small impedance variation. Power must be supplied to the WRF_XTAL_VDD1P35 pin.

  • Page 15: Frequency Selection

    19.2, 19.8, 24, 26, 33.6, 37.4, 38.4, and 52 MHz, but also other frequencies in this range, with approximately 80 Hz resolution. The CYW43455 must have the reference frequency set correctly in order for any of the UART or PCM interfaces to function correctly, since all bit timing is derived from the reference frequency.

  • Page 16: External 32.768 Khz Low-Power Oscillator

    CYW43455 3.4 External 32.768 kHz Low-Power Oscillator The CYW43455 uses a secondary low frequency clock for low-power-mode timing. An external 32.768 kHz precision oscillator is required. Table 4. External 32.768 kHz Sleep Clock Specifications Parameter LPO Clock Units Nominal input frequency 32.768...

  • Page 17: Bluetooth Subsystem Overview

    The CYW43455 is a Bluetooth 5.0 + EDR-compliant and, baseband processor with 2.4 GHz transceiver. The CYW43455 is the optimal solution for any Bluetooth voice and/or data application. The Bluetooth subsystem presents a standard host controller interface (HCI) via a high-speed UART and PCM for audio. The CYW43455 incorporates all Bluetooth 5.0 mandatory features include secure simple pairing, sniff subrating, and encryption pause and resume.

  • Page 18: Bluetooth Radio

    4.2 Bluetooth Radio The CYW43455 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band.
  • Page 19 A local oscillator (LO) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The LO generation subblock employs an architecture for high immunity to LO pulling during PA operation. The CYW43455 uses an internal RF and IF loop filter.

  • Page 20: Bluetooth Baseband Core

    ■ Note: The CYW43455 is compatible with the Bluetooth Low Energy operating mode, which provides a dramatic reduction in the power consumption of the Bluetooth radio and baseband. The primary application for this mode is to provide support for low data rate devices, such as sensors and remote controls.

  • Page 21: Link Control Layer

    ❐ 5.6 Test Mode Support The CYW43455 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0. This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence.

  • Page 22: Bluetooth Power Management Unit

    5.7.2 Host Controller Power Management When running in UART mode, the CYW43455 may be configured so that dedicated signals are used for power management hand-shaking between the CYW43455 and the host. The basic power saving functions supported by those hand-shaking signals include the standard Bluetooth defined power savings modes and standby modes of operation.
  • Page 23 CYW43455 Figure 7 shows the startup signaling sequence prior to software download. Figure 7. Startup Signaling Sequence Prior to Software Download Host IOs unconfigured VDDIO Host IOs configured HostResetX BT_DEV_WAKE BTH IOs unconfigured BTH IOs configured BT_REG_ON BT_HOST_WAKE BT_UART_CTS_N Host side drives this line...
  • Page 24 Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on any digital signals in the system and enables the CYW43455 to be fully integrated in an embedded device to take full advantage of the lowest power-saving modes.

  • Page 25: Adaptive Frequency Hopping

    Burst Buffer Operation The CYW43455 has a data buffer that can buffer data being sent over the HCI and audio transports, then send the data at an increased rate. This mode of operation allows the host to sleep for the maximum amount of time, dramatically reducing system current consumption.

  • Page 26: Advanced Bluetooth/Wlan Coexistence

    Information is exchanged between the Bluetooth and WLAN cores without host processor involvement. The CYW43455 also supports Transmit Power Control on the STA together with standard Bluetooth TPC to limit mutual interference and receiver desensitization. Preemption mechanisms are utilized to prevent AP transmissions from colliding with Bluetooth frames.

  • Page 27: Microprocessor And Memory Unit For Bluetooth

    6.2 Reset The CYW43455 has an integrated power-on reset circuit that resets all circuits to a known power-on state. The BT power-on reset (POR) circuit is out of reset after BT_REG_ON goes High. If BT_REG_ON is low, then the POR circuit is held in reset.

  • Page 28: Bluetooth Peripheral Transport Unit

    7.1 SPI Interface The CYW43455 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock rates can be possible. The physical interface between the SPI master and the CYW43455 consists of the four SPI signals (SPI_CSB, SPI_CLK, SPI_SI, and SPI_SO) and one interrupt signal (SPI_INT).
  • Page 29 The CYW43455 may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the CYW43455 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface.
  • Page 30 CYW43455 7.3.7 PCM Interface Timing Short Frame Sync, Master Mode Figure 11. PCM Timing Diagram (Short Frame Sync, Master Mode) PCM_BCLK PCM_SYNC PCM_OUT HIGH IMPEDANCE PCM_IN Table 7. PCM Interface Timing Specifications (Short Frame Sync, Master Mode) Reference Characteristics Minimum...
  • Page 31 CYW43455 Short Frame Sync, Slave Mode Figure 12. PCM Timing Diagram (Short Frame Sync, Slave Mode) PCM_BCLK PCM_SYNC PCM_OUT HIGH IMPEDANCE PCM_IN 4345XCT-DS1X15_f_015_1 Table 8. PCM Interface Timing Specifications (Short Frame Sync, Slave Mode) Reference Characteristics Minimum Typical Maximum Unit PCM bit clock frequency –...
  • Page 32 CYW43455 Long Frame Sync, Master Mode Figure 13. PCM Timing Diagram (Long Frame Sync, Master Mode) PCM_BCLK PCM_SYNC PCM_OUT HIGH IMPEDANCE Bit 0 Bit 1 Bit 0 Bit 1 PCM_IN Table 9. PCM Interface Timing Specifications (Long Frame Sync, Master Mode)
  • Page 33 CYW43455 Long Frame Sync, Slave Mode Figure 14. PCM Timing Diagram (Long Frame Sync, Slave Mode) PCM_BCLK PCM_SYNC PCM_OUT Bit 0 HIGH IMPEDANCE Bit 1 PCM_IN Bit 0 Bit 1 4345XCT-DS1X15_f_017_1 Table 10. PCM Interface Timing Specifications (Long Frame Sync, Slave Mode)
  • Page 34 CYW43455 Short Frame Sync, Burst Mode Figure 15. PCM Burst Mode Timing (Receive Only, Short Frame Sync) PCM_BCLK PCM_SYNC PCM_IN 4345XCT-DS1X15_f_018_1 Table 11. PCM Burst Mode (Receive Only, Short Frame Sync) Reference Characteristics Minimum Typical Maximum Unit PCM bit clock frequency –...
  • Page 35 CYW43455 Long Frame Sync, Burst Mode Figure 16. PCM Burst Mode Timing (Receive Only, Long Frame Sync) PCM_BCLK PCM_SYNC PCM_IN Bit 0 Bit 1 4345XCT-DS1X15_f_019_1 Table 12. PCM Burst Mode (Receive Only, Long Frame Sync) Reference Characteristics Minimum Typical Maximum...

  • Page 36: Uart Interface

    Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The CYW43455 UARTs operate correctly with the host UART as long as the combined baud rate error of the two devices is within ±2%.

  • Page 37: I 2 S Interface

    S WS is low, and right-channel data is transmitted when I S WS is high. Data bits sent by the CYW43455 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the rising edge of I2S_SSCK.
  • Page 38 CYW43455 7.5.1 I S Timing Note: Timing values specified in Table 15 are relative to high and low threshold levels. Table 15. Timing for I S Transmitters and Receivers Transmitter Receiver Lower LImit Upper Limit Lower Limit Upper Limit Notes Min.
  • Page 39 CYW43455 Figure 18. I S Transmitter Timing > 0.35T > 0.35T = 2.0V = 0.8V > 0 < 0.8T SD and WS T = Clock period = Minimum allowed clock period for transmitter T = T is only relevant for transmitters in slave mode.

  • Page 40: Wlan Global Functions

    Prior to OTP programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with the reference board design package. 8.3 GPIO Interface The following number of general-purpose I/O (GPIO) pins are available on the WLAN section of the CYW43455 that can be used to connect to various external devices: WLBGA package – 15 GPIOs ■...

  • Page 41: External Coexistence Interface

    GPS or LTE to manage wireless medium sharing for optimum performance. Figure 20 shows the WCI-2 LTE coexistence interface. See Table 14 for UART baud rate. Figure 20. Cypress GCI or BT-SIG WCI-2 LTE Coexistence Interface LTE\IC SECI_OUT / BT_TXD / GPIO5 UART_IN WLAN...

  • Page 42: Uart Interface

    8.6 JTAG/SWD Interface The CYW43455 supports IEEE 1149.1 JTAG boundary scan and reduced pin-count Serial Wire Debug (SWD) mode to access the chip’s internal blocks and backplane for system bring-up and debugging. This interface allows Cypress engineers to assist customers with proprietary debug and characterization test tools.

  • Page 43: Wlan Host Interfaces

    9. WLAN Host Interfaces 9.1 SDIO v3.0 All three package options of the CYW43455 WLAN section provide support for SDIO version 3.0, including the new UHS-I modes: DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling).
  • Page 44 CYW43455 Figure 23. Signal Connections to SDIO Host (SD 1-Bit Mode) DATA SD Host CYW43455 Note: Per Section 6 of the SDIO specification, pull-ups in the 10 kΩ to 100 kΩ range are required on the four DATA lines and the CMD line.

  • Page 45: Pci Express Interface

    9.3 PCI Express Interface Note: The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface. The PCI Express (PCIe) core on the CYW43455 is a high-performance serial I/O interconnect that is protocol compliant and electrically compatible with the PCI Express Base Specification v2.0.

  • Page 46: Transaction Layer Interface

    9.4 Transaction Layer Interface The PCIe core employs a packet-based protocol to transfer data between the host and CYW43455 device, delivering new levels of performance and features. The upper layer of the PCIe is the Transaction Layer. The Transaction layer is primarily responsible for assembly and disassembly of Transaction Layer Packets (TLPs).
  • Page 47 DC common mode voltage from the receiver. The range of AC capacitance allowed is 75 nF to 200 nF. 9.4.8 Configuration Space The PCIe function in the CYW43455 implements the configuration space as defined in the PCI Express Base Specification v2.0. Document Number: 002-15051 Rev. *O...

  • Page 48: Wireless Lan Mac And Phy

    RX A-MPDU TX A-MPDU MAC-PHY Interface The CYW43455 WLAN media access controller (MAC) supports features specified in the IEEE 802.11 base standard, and amended by IEEE 802.11n. The key MAC features include: Enhanced MAC for supporting IEEE 802.11ac features ■...
  • Page 49 CYW43455 10.1.1 PSM The programmable state machine (PSM) is a microcoded engine, which provides most of the low-level control to the hardware, to implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flow control operations, which are predom- inant in implementations of communication protocols.
  • Page 50 CYW43455 10.1.5 IFS The IFS module contains the timers required to determine interframe space timing including RIFS timing. It also contains multiple backoff engines required to support prioritized access to the medium as specified by WMM. The interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the PHY. These timers provide precise timing to the TXE to begin frame transmission.

  • Page 51: Ieee 802.11Ac Phy

    CYW43455 10.2 IEEE 802.11ac PHY The CYW43455 WLAN Digital PHY is designed to comply with IEEE 802.11ac and IEEE 802.11a/b/g/n single-stream specifications to provide wireless LAN connectivity supporting data rates from 1 Mbps to 433.3 Mbps for low-power, high-performance handheld applications.

  • Page 52: Wlan Radio Subsystem

    11. WLAN Radio Subsystem The CYW43455 includes an integrated dual-band WLAN RF transceiver that has been optimized for use in 2.4 GHz and 5 GHz Wireless LAN systems. It has been designed to provide low-power, low-cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM or 5 GHz U-NII bands.
  • Page 53 CYW43455 Figure 27. Radio Functional Block Diagram WL DAC WL PA WL PGA WL TXLPF WL TX G-Mixer WL DAC WL A-PA WL A-PAD WL A-PGA WL TXLPF WL TX A-Mixer Voltage WLAN BB Regulators WL ADC WL A-LNA11 WL A-LNA12...

  • Page 54: Ball Map And Pin Descriptions

    CYW43455 12. Ball Map and Pin Descriptions 12.1 Ball Map Figure 28. 140-Ball WLBGA Map—Bottom View (Balls Facing Up) SDIO_DAT LDO_VDDB LDO_VDD1 SR_VDDBA PCIE_TDN PCIE_RDN PCIE_RDP SDIO_CLK VOUT_3P3 SR_PVSS AT5V PCIE_RXT PCIE_REF PCIE_CLK SDIO_DAT SDIO_DAT VOUT_BTL VOUT_LNL VOUT_CLD VOUT_PCI PCIE_TDP...

  • Page 55: Pin List By Pin Number

    CYW43455 12.2 Pin List by Pin Number Table 18 lists CYW43455 pins by pin number. For a list of CYW43455 pins by pin name, see Table 19 Table 18. Pin List by Pin Number (continued) Table 18. Pin List by Pin Number...
  • Page 56 CYW43455 Table 18. Pin List by Pin Number (continued) Table 18. Pin List by Pin Number (continued) Ball Name Ball Name RF_SW_CTRL_2 BT_CLK_REQ WRF_XTAL_GND1P2 BT_PLLVSS WRF_XTAL_XON BT_IFVSS BT_PCM_CLK BT_LNAVDD1P2 BT_I2S_DO WRF_GPAIO_OUT BT_PCM_OUT WRF_AFE_GND WRF_GENERAL2_GND BT_GPIO_4 WRF_RFIN_5G BT_GPIO_3 BT_DEV_WAKE – FM_PLLVDD1P2...

  • Page 57: Pin List By Pin Name

    CYW43455 12.3 Pin List by Pin Name Table 19 lists CYW43455 pins by pin name. For a list of CYW43455 pins by pin number, see Table Table 19. Pin List by Pin Name (continued) Table 19. Pin List by Pin Name...
  • Page 58 CYW43455 Table 19. Pin List by Pin Name (continued) Table 19. Pin List by Pin Name (continued) Name Ball Name Ball PCIE_VSS VSSC PCI_PME_L WL_REG_ON PERST_L WRF_AFE_GND PMU_AVSS WRF_AFE_VDD1P35 RF_SW_CTRL_0 WRF_EXT_TSSIA RF_SW_CTRL_1 WRF_GENERAL2_GND RF_SW_CTRL_2 WRF_GENERAL_GND RF_SW_CTRL_3 WRF_GPAIO_OUT RF_SW_CTRL_4 WRF_PAOUT_2G RF_SW_CTRL_5...

  • Page 59: Pin Descriptions

    RF_SW_CTRL_7 RF_SW_CTRL_8 WLAN PCI Express Interface Note: The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface. PCIE_CLKREQ_L PCIe clock request signal which indicates when the REFCLK to the PCIe interface can be gated.
  • Page 60 CYW43455 Table 20. Signal Descriptions (continued) Signal Name WLBGA Ball Type Description PCI_PME_L PCI power management event output. Used to request a change in the device or system power state. The assertion and deassertion of this signal is asynchronous to the PCIe reference clock.
  • Page 61 CYW43455 Table 20. Signal Descriptions (continued) Signal Name WLBGA Ball Type Description JTAG/SWD Interface JTAG_SEL JTAG select. This pin must be connected to ground if the JTAG/SWD interface is not used. It must be high to select SWD OR JTAG. When JTAG_SEL = 1:...
  • Page 62 Miscellaneous WL_REG_ON Used by PMU to power-up or power down the internal CYW43455 regulators used by the WLAN section. Also, when deasserted, this pin holds the WLAN section in reset. This pin has an internal 200 kΩ pull-down resistor that is enabled by default.
  • Page 63 CYW43455 Table 20. Signal Descriptions (continued) Signal Name WLBGA Ball Type Description BT_PLLVDD1P2 Bluetooth RF PLL power supply. FM Transceiver Supplies FM_RFVDD1P2 FM RF power supply. FM_PLLVDD1P2 FM PLL power supply. WLAN Supplies WRF_SYNTH_VDD3P3 Synthesizer VDD 3.3 V supply. WRF_PA_VDD3P3 2 GHz and 5 GHz PA 3.3 V VBAT supply.

  • Page 64: Wlan Gpio Signals And Strapping Options

    CYW43455 Table 20. Signal Descriptions (continued) Signal Name WLBGA Ball Type Description PMU_AVSS Quiet ground. BT_PAVSS Bluetooth PA ground. BT_LNAVSS Bluetooth LNA ground. BT_IFVSS Bluetooth IF block ground. BT_PLLVSS Bluetooth PLL ground. FM_PLLVSS FM PLL ground. FM_RFVSS FM RF ground.
  • Page 65 BT_GPIO_3 is set to pad function 0). When the Pad Function Control register is set to 0, the BT_GPIOs do not have specific functions assigned to them and behave as generic GPIOs. The A_GPIO_X pins described below are multiplexed behind the CYW43455's PCM and I S interface pins.
  • Page 66 CYW43455 The multiplexed GPIO signals are described in Table Table 23. Multiplexed GPIO Signals Pin Name Type Description UART_CTS_N Host UART clear to send. UART_RTS_N Device UART request to send. UART_RXD Device UART receive data. UART_TXD Host UART transmit data.

  • Page 67: I/O States

    CYW43455 12.6 I/O States The following notations are used in Table I: Input signal ■ O: Output signal ■ I/O: Input/Output signal ■ PU = Pulled up ■ PD = Pulled down ■ NoPull = Neither pulled up nor pulled down ■...
  • Page 68 CYW43455 Table 24. I/O States (continued) Power-down Out-of-Reset; Low Power (WL_REG_ON High and (BT_REG_ON and Before SW Download Name Keeper Active Mode State/Sleep (All Pow- BT_REG_ON = 0) and Power Rail WL_REG_ON Held (BT_REG_ON High; er Present) VDDIOs Are Present...
  • Page 69 CYW43455 Table 24. I/O States (continued) Power-down Out-of-Reset; Low Power (WL_REG_ON High and (BT_REG_ON and Before SW Download Name Keeper Active Mode State/Sleep (All Pow- BT_REG_ON = 0) and Power Rail WL_REG_ON Held (BT_REG_ON High; er Present) VDDIOs Are Present...
  • Page 70 CYW43455 Table 24. I/O States (continued) Power-down Out-of-Reset; Low Power (WL_REG_ON High and (BT_REG_ON and Before SW Download Name Keeper Active Mode State/Sleep (All Pow- BT_REG_ON = 0) and Power Rail WL_REG_ON Held (BT_REG_ON High; er Present) VDDIOs Are Present...

  • Page 71: Dc Characteristics

    CYW43455 13. DC Characteristics Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. 13.1 Absolute Maximum Ratings Caution! The absolute maximum ratings in Table 25 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration.

  • Page 72: Recommended Operating Conditions And Dc Characteristics

    – – 1. The CYW43455 is functional across this range of voltages. Optimal RF performance specified in the data sheet, however, is guaranteed only for 3.2 V < VBAT < 4.8 V. 2. The maximum continuous voltage is 5.25 V.

  • Page 73: Bluetooth Rf Specifications

    CYW43455 14. Bluetooth RF Specifications Note: Values in this data sheet are design goals and are subject to change based on device characterization results. Unless otherwise stated, limit values apply for the conditions specified in Table 26 Table 28. Typical values apply for the following conditions: VBAT = 3.6 V...
  • Page 74 CYW43455 Table 29. Bluetooth Receiver RF Specifications (continued) Parameter Conditions Minimum Typical Maximum Unit C/I 1-MHz adjacent to image channel GFSK, 0.1% BER – – –20 /4-DQPSK, 0.1% BER C/I co-channel – – /4-DQPSK, 0.1% BER C/I 1 MHz adjacent channel –...
  • Page 75 CYW43455 Table 29. Bluetooth Receiver RF Specifications (continued) Parameter Conditions Minimum Typical Maximum Unit 824–849 MHz WCDMA – –11 – 880–915 MHz E-GSM – –10 – 880–915 MHz WCDMA – –10 – 1710–1785 MHz GSM1800 – –16 – 1710–1785 MHz WCDMA –...
  • Page 76 CYW43455 Table 29. Bluetooth Receiver RF Specifications (continued) Parameter Conditions Minimum Typical Maximum Unit Spurious Emissions 30 MHz–1 GHz – –95 –62 1–12.75 GHz – –70 –47 851–894 MHz – –147 – dBm/Hz 925–960 MHz – –147 – dBm/Hz 1805–1880 MHz –...
  • Page 77 CYW43455 Table 30. Bluetooth Transmitter RF Specifications (continued) Parameter Conditions Minimum Typical Maximum Unit Out-of-Band Noise Floor 65–108 MHz FM RX – –147 – dBm/Hz 776–794 MHz CDMA2000 – –146 – dBm/Hz 869–960 MHz cdmaOne, GSM850 – –146 – dBm/Hz 925–960 MHz...
  • Page 78 CYW43455 Table 32. BLE RF Specifications Parameter Conditions Minimum Typical Maximum Unit Frequency range – 2402 – 2480 RX sense GFSK, 0.1% BER, 1 Mbps – –96.5 – TX power – – – Mod Char: delta F1 average – Mod Char: delta F2 max.

  • Page 79: Wlan Rf Specifications

    15. WLAN RF Specifications 15.1 Introduction The CYW43455 includes an integrated dual-band direct conversion radio that supports the 2.4 GHz and the 5 GHz bands. This section describes the RF characteristics of the 2.4 GHz and 5 GHz radio. Note: Values in this section of the data sheet are design goals and are subject to change based on device characterization results.

  • Page 80: Wlan 2.4 Ghz Receiver Performance Specifications

    CYW43455 15.3 WLAN 2.4 GHz Receiver Performance Specifications Note: The specifications shown in the following table are provided at the chip port, unless otherwise defined. Table 34. WLAN 2.4 GHz Receiver Performance Specifications Parameter Condition/Notes Minimum Typical Maximum Unit Frequency range –...
  • Page 81 CYW43455 Table 34. WLAN 2.4 GHz Receiver Performance Specifications (continued) Parameter Condition/Notes Minimum Typical Maximum Unit Blocking level for 3 dB RX sensi- 776–794 MHz (CDMA2000): tivity degradation (without Blocker frequency = 794 MHz – –16 – external filtering) 824–849 MHz...
  • Page 82 CYW43455 Table 34. WLAN 2.4 GHz Receiver Performance Specifications (continued) Parameter Condition/Notes Minimum Typical Maximum Unit Adjacent channel rejection-DSSS Desired and interfering signal 30 MHz apart (Difference between interfering 1 Mbps DSSS –74 dBm – – and desired signal at 8% PER for 2 Mbps DSSS –74 dBm...

  • Page 83: Wlan 2.4 Ghz Transmitter Performance Specifications

    CYW43455 15.4 WLAN 2.4 GHz Transmitter Performance Specifications Note: Unless otherwise noted, the values shown in the following table are provided at the WLAN chip port output. Table 35. WLAN 2.4 GHz Transmitter Performance Specifications Parameter Condition/Notes Minimum Typical Maximum...

  • Page 84: Wlan 5 Ghz Receiver Performance Specifications

    CYW43455 15.5 WLAN 5 GHz Receiver Performance Specifications Note: Unless otherwise noted, the values shown in the following table are provided at the chip port input. Table 36. WLAN 5 GHz Receiver Performance Specifications Parameter Condition/Notes Minimum Typical Maximum Unit Frequency range –...
  • Page 85 CYW43455 Table 36. WLAN 5 GHz Receiver Performance Specifications (continued) Parameter Condition/Notes Minimum Typical Maximum Unit RX sensitivity IEEE 802.11ac 40 MHz channel spacing for all MCS rates (10% PER for 4096 octet PSDU) MCS0 – –92.3 – Defined for default parameters: MCS1 –...
  • Page 86 CYW43455 Table 36. WLAN 5 GHz Receiver Performance Specifications (continued) Parameter Condition/Notes Minimum Typical Maximum Unit Blocking level for 3 dB RX sensitivity 776–794 MHz (CDMA2000): degradation (without external Blocker frequency = 794 MHz – –21 – filtering) 824–849 MHz...
  • Page 87 CYW43455 Table 36. WLAN 5 GHz Receiver Performance Specifications (continued) Parameter Condition/Notes Minimum Typical Maximum Unit Adjacent channel rejection 6 Mbps OFDM –79 dBm – – (Difference between interfering and 9 Mbps OFDM –78 dBm – – desired signal (20 MHz apart) at 12 Mbps –76 dBm...

  • Page 88: Wlan 5 Ghz Transmitter Performance Specifications

    CYW43455 15.6 WLAN 5 GHz Transmitter Performance Specifications Note: Unless otherwise noted, the values shown in the following table are provided at the WLAN chip port output. Table 37. WLAN 5 GHz Transmitter Performance Specifications Parameter Condition/Notes Minimum Typical Maximum...

  • Page 89: General Spurious Emissions Specifications

    CYW43455 15.7 General Spurious Emissions Specifications This section provides the TX and RX spurious emissions specifications for both the WLAN 2.4 GHz and 5 GHz bands. The recom- mended spectrum analyzer settings for the spurious emissions specifications are provided in Table Table 38.
  • Page 90 CYW43455 2.4 GHz Band Spurious Emissions 20 MHz Channel Spacing Note: Possible AFE combinations are as follows. The AFE=VCO/16 specifications for channel 2442 are listed in Table Table 39. 2.4 GHz Band, 20 MHz Channel Spacing TX Spurious Emissions Specifications Frequency (Fch;...
  • Page 91 CYW43455 5 GHz Band Spurious Emissions 20 MHz Channel Spacing Note: Possible AFE combinations are as follows. The AFE=VCO/18 specifications for channels 5180, 5500, and 5825 are listed in Table Table 40. 5 GHz Band, 20 MHz Channel Spacing TX Spurious Emissions Specifications...
  • Page 92 CYW43455 40 MHz Channel Spacing Note: Possible AFE combinations are as follows. The AFE=VCO/9 specifications for channels 5190, 5510, and 5795 are listed in Table Table 41. 5 GHz Band, 40 MHz Channel Spacing TX Spurious Emissions Specifications CH5190m CH5510m...
  • Page 93 CYW43455 80 MHz Channel Spacing Note: Possible AFE combinations are as follows. The AFE=VCO/6 specifications for channels 5210, 5530, and 5775 are listed in Table Table 42. 5 GHz Band, 80 MHz Channel Spacing TX Spurious Emissions Specifications CH5210q CH5530q...

  • Page 94: Internal Regulator Electrical Specifications

    CYW43455 16. Internal Regulator Electrical Specifications 16.1 Core Buck Switching Regulator Note: Values in this data sheet are design goals and are subject to change based on device characterization results. Note: Functional operation is not guaranteed outside of the specification limits provided in this section.

  • Page 95: Ldo (Ldo3P3)

    CYW43455 16.2 3.3V LDO (LDO3P3) Table 45. LDO3P3 Specifications Specification Notes Min. Typ. Max. Units Input supply voltage, V Min. = V + 0.2V = 3.5V dropout voltage 5.25 requirement must be met under maximum load for performance specifications. Output current –...

  • Page 96: Ldo (Btldo2P5)

    CYW43455 16.3 2.5V LDO (BTLDO2P5) Table 46. BTLDO2P5 Specifications Specification Notes Min. Typ. Max. Units Input supply voltage Min. = 2.5V + 0.2V = 2.7V. 5.25 Dropout voltage requirement must be met under maximum load for performance specifications. Nominal output voltage Default = 2.5V.

  • Page 97: Cldo

    CYW43455 16.4 CLDO Table 47. CLDO Specifications Specification Notes Min. Typ. Max. Units Input supply voltage, V Min. = 1.2 + 0.15V = 1.35V dropout voltage 1.35 requirement must be met under maximum load. Output current – – Output voltage, V Programmable in 10 mV steps.

  • Page 98: Lnldo

    CYW43455 16.5 LNLDO Table 48. LNLDO Specifications Specification Notes Min. Typ. Max. Units Input supply voltage, Vin Min. V + 0.15V = 1.35V (where V 1.35 1.2V)dropout voltage requirement must be met under maximum load. Output Current – – Output Voltage, V Programmable in 25 mV steps.

  • Page 99: Pcie Ldo

    CYW43455 16.6 PCIe LDO Note: The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface. Table 49. PCIe LDO Specifications Specification Notes Min. Typ. Max. Units Input supply voltage, Vin Min. V + 0.15V = 1.35V (where...

  • Page 100: System Power Consumption

    Table 28: “Recommended Operating Conditions and Characteristics”. 17.1 WLAN Current Consumption The tables in this subsection show the typical, total current consumed by the CYW43455. All values shown are with the Bluetooth core in reset mode with Bluetooth off. 17.1.1 2.4 GHz Mode Table 50.
  • Page 101 CYW43455 17.1.2 5 GHz Mode Table 51. 5 GHz Mode WLAN Power Consumption = 3.6V, V = 1.8V, T 25°C DDIO Mode BAT , mA IO, uA Sleep Modes Radio off 0.006 Sleep 0.025 IEEE Power Save: DTIM = 1, single RX...

  • Page 102: Bluetooth Current Consumption

    CYW43455 17.2 Bluetooth Current Consumption The Bluetooth and BLE current consumption measurements are shown in Table Note: The WLAN core is in reset (WLAN_REG_ON = low) for all measurements provided in Table Note: The BT current consumption numbers are measured based on GFSK TX output power = 10 dBm.

  • Page 103: Interface Timing And Ac Characteristics

    CYW43455 18. Interface Timing and AC Characteristics 18.1 SDIO Timing 18.1.1 SDIO Default Mode Timing SDIO default mode timing is shown by the combination of Figure 31 Table Figure 31. SDIO Bus Timing (Default Mode) SDIO_CLK Input Output ODLY ODLY...

  • Page 104: Sdio High-Speed Mode Timing

    CYW43455 18.2 SDIO High-Speed Mode Timing SDIO high-speed mode timing is shown by the combination of Figure 32 Table Figure 32. SDIO Bus Timing (High-Speed Mode) 50% VDD SDIO_CLK Input Output ODLY Table 54. SDIO Bus Timing Parameters (High-Speed Mode)
  • Page 105 CYW43455 18.2.1 SDIO Bus Timing Specifications in SDR Modes Clock Timing Figure 33. SDIO Clock Timing (SDR Modes) SDIO_CLK Table 55. SDIO Bus Clock Timing Parameters (SDR Modes) Parameter Symbol Minimum Maximum Unit Comments – – SDR12 mode – SDR25 mode –...
  • Page 106 CYW43455 Card Input Timing Figure 34. SDIO Bus Input Timing (SDR Modes) SDIO_CLK CMD input DAT[3:0] input Table 56. SDIO Bus Input Timing Parameters (SDR Modes) Symbol Minimum Maximum Unit Comments SDR104 Mode – = 10 pF, VCT = 0.975V CARD –...
  • Page 107 CYW43455 Card Output Timing Figure 35. SDIO Bus Output Timing (SDR Modes up to 100 MHz) SDIO_CLK ODLY CMD input DAT[3:0] input Table 57. SDIO Bus Output Timing Parameters (SDR Modes up to 100 MHz) Symbol Minimum Maximum Unit Comments –...
  • Page 108 CYW43455 Table 58. SDIO Bus Output Timing Parameters (SDR Modes 100 MHz to 208 MHz) Symbol Minimum Maximum Unit Comments Card output phase Δt –350 +1550 Delay variation due to temp change after tuning 0.60 – = 2.88 ns @ 208 MHz Δt...
  • Page 109 CYW43455 Table 59. SDIO Bus Clock Timing Parameters (DDR50 Mode) Parameter Symbol Minimum Maximum Unit Comments – – DDR50 mode – – 0.2 × tCLK < 4.00 ns (max) @50 MHz, = 10 pF CARD Clock duty cycle – –...

  • Page 110: Pci Express Interface Parameters

    CYW43455 18.3 PCI Express Interface Parameters Note: The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface. Table 61. PCI Express Interface Parameters Parameter Symbol Comments Minimum Typical Maximum Unit General Baud rate –...

  • Page 111: Jtag Timing

    CYW43455 Table 61. PCI Express Interface Parameters (continued) Parameter Symbol Comments Minimum Typical Maximum Unit Absolute delta of DC VTX-CM-DC-ACTIVE-ID Absolute delta of DC – common-model voltage LE-DELTA common-model voltage during L0 and electrical idle during L0 and electrical idle.

  • Page 112: Swd Timing

    CYW43455 18.5 SWD Timing The probe outputs data to SWDIO on the falling edge of SWDCLK and captures data from SWDIO on the rising edge of SWDCLK. The target outputs data to SWDIO on the rising edge of SWDCLK and captures data from SWDIO on the rising edge of SWDCLK.

  • Page 113: Power-Up Sequence And Timing

    VDDIO in-rush current on the order of 36 mA during the next PMU cold start. Note: The CYW43455 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC and VDDIO have both passed the POR threshold.
  • Page 114 CYW43455 Figure 42. WLAN = OFF, Bluetooth = OFF 32.678 kHz Sleep Clock VBAT* VDDIO WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds. 2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.

  • Page 115: Package Information

    CYW43455 20. Package Information 20.1 Package Thermal Characteristics Table 64. Package Thermal Characteristics Characteristic WLBGA  (°C/W) (value in still air) 38.73  (°C/W) 1.97  (°C/W) 3.16  (°C/W)  (°C/W) 16.21 Maximum Junction Temperature T (°C) 123.6 Maximum Power Dissipation (W) 1.38...

  • Page 116: Mechanical Information

    CYW43455 21. Mechanical Information Figure 45. 140-Ball WLBGA Package Mechanical Information 4345XCT DS1X15 f 055 1 Document Number: 002-15051 Rev. *O Page 115 of 121...
  • Page 117 0.07 0.07 Note: No top-layer metal is allowed in keep-out areas. Note: A DXF file for the WLBGA keep-out area is available for importation into a layout program. Contact Cypress for more information. Document Number: 002-15051 Rev. *O Page 116 of 121...

  • Page 118: Ordering Information

    Downloads & Support site (see Resources). For Cypress documents, replace the “xx” in the document number with the largest number available in the repository to ensure that you have the most current version of the document. Document (or Item) Name...

  • Page 119: Document History Page

    CYW43455 Document History Page Document Title: CYW43455 Single-Chip 5G WiFi IEEE 802.11n/ac MAC/Baseband/ Radio with Integrated Bluetooth 5.0 Document Number: 002-15051 Orig. of Submission Revision Description of Change Change Date – – 10/27/2014 43455-DS100-R Initial release. – – 11/06/2014 43455-DS101-R See the pertinent document for the revision history.
  • Page 120 CYW43455 Document Title: CYW43455 Single-Chip 5G WiFi IEEE 802.11n/ac MAC/Baseband/ Radio with Integrated Bluetooth 5.0 Document Number: 002-15051 6440968 UTSV 03/22/2019 Updated the title as “Single-Chip 5G WiFi IEEE 802.11n/ac MAC/Baseband/ Radio with Integrated Bluetooth 5.0 “. Added footnote for references of PCIe as “The PCIe interface is not brought up on CYW43455 and Cypress's firmware and drivers do not support this interface”.

  • Page 121: Sales, Solutions, And Legal Information

    (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products.

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