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THEORY OF OPERATION
INSTRUCTION
MANUAL
DigItal Multlm*mr
Models
172A. t73A
out
in
the
time
period
of
the
clock
puises
on
INCLK until
the
last
rising
edge
of
INCLK,
-
at which
time
it
will
clock
out
at
30 microseconds.
Therefore,
UPTIME,
the
output
of
U1017,
will
be length
of
the
INCLK pulse
stream
plus
approximately
30 mi*croseconds.
This
is
the
time
in which
data
wi.lI
be flowing
from
the
1722 to
the
OMH.
The beginning
of
a conversion
is
started
by clocking
DOWNCLK with
UPTIME
in
flip-flop
Ul015A.
The
beginning
of
downtime
also
defines
the
time
when
the
flag
is
set
high,
that
is,
when
data
has finished
being
updated.
Setting
the
flag
low during
data
change
time,
or
re-
setting
the
flag,
is
accomplished
in
two ways:
FR or
UPDATE.
Downtime
also
gates
DOWNCLK thru
UlOl4C
& UlOl40
where
it
is
called
GATECLK and goes
to
the
output
register.
Output
Resister.
The output
register
is made up of
shift
registers
U1008A
t B,
,,;,A
& B
IOIOA
& 8,
IOIIA
& 8.
It
is a 32-bit
shift
register,
of
which
only
30 are
used.
Se;ial
data
enters
~10086
and
is clocked
through
all
of
the
shift
registers
by the
parallel
clock,
GATECLK.
At
the
end of
the
clocking
time
all
30 bits
have
been
shifted
in and are
presented
in parallel
to
the
output
buffer.
f.
Output
Drive
and Buffer.
Parallel
data
on the
output
registers
goes
to output
gates
UIOOI
thru
1007 and UlOl2
and
1013.
Here,
the
data
is
gated
with
the
output
strobes
through
drive
transistors
(QIOOI
thru
1030)
to
the
output
connector
PlOO6.
9.
Input
Buffers.
Strobelines
are
buffered
by UllOl
and UllO2
and go out
to
the
output
drive
and buffer
block.
Remote
control
inputs
are
buffered
by UllO4,
Ullll,
Ul105.
UllO4
is a Schmitt
trigger,
which
is
put
on certain
control
lines
to prevent
false
triggering
(see
Schematic
28019E).
NOTE
Additional
information
concerning
the
operation
of
the
Model
I722
is
given
in Section
3.
This
additional
information
is
referenced
to
three
timing
diagrams
provided
in
Section
7 (Timing
Diagrams:
28247E,
28248E
and 28249E).
5-26
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